Georg Sigl - RankMe

195 papers A* 3A 20B 6C 24Misc 6Journal 69Unranked 66

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Influence of Parallelism in Vector-Multiplication Units on Correlation Power Analysis. CoRR Manuel Brosch, Matthias Probst, Stefan Koegler, Georg Sigl
2026	J	`jnl`	Influence of Parallelism in Vector-Multiplication Units on Correlation Power Analysis. ACM Trans. Embed. Comput. Syst. Manuel Brosch, Matthias Probst, Stefan Koegler, Georg Sigl
2025	—	`conf`	A Cyber-Resilient DICE Architecture for Resource-Constrained Devices. ARES (EU Projects Symposium Workshops 1) Utku Budak, Malek Safieh, Fabrizio De Santis, Georg Sigl
2025	—	`conf`	A Horizontal Attack on the Codes and Restricted Objects Signature Scheme (CROSS). CASCADE Jonas Schupp, Georg Sigl
2025	J	`jnl`	A Horizontal Attack on the Codes and Restricted Objects Signature Scheme (CROSS). IACR Cryptol. ePrint Arch. Jonas Schupp, Georg Sigl
2025	Misc	`conf`	A Lightweight Firmware Resilience Engine for Real-Time Operating Systems. CSR Utku Budak, Fabrizio De Santis, Osman Yasar, Malek Safieh, Georg Sigl
2025	C	`conf`	Fault Detection in the Control- and Data-Path of Neural Networks. FDTC Matthias Probst, Manuel Brosch, Augustin Ewald, Michael Gruber, Georg Sigl
2025	J	`jnl`	High-Performance FPGA Accelerator for the Post-quantum Signature Scheme CROSS. IACR Cryptol. ePrint Arch. Patrick Karl, Francesco Antognazza, Alessandro Barenghi, Gerardo Pelosi, Georg Sigl
2025	A	`conf`	Multi-Partner Project: Open-Source Design Tools for Co-Development of AI Algorithms and AI Chips: (Initial Stage). DATE Mehdi B. Tahoori, Jürgen Becker, Jörg Henkel, Wolfgang Kunz, Ulf Schlichtmann, Georg Sigl, Jürgen Teich, Norbert Wehn
2025	J	`jnl`	Optimizing the Post Quantum Signature Scheme CROSS for Resource Constrained Devices. IACR Cryptol. ePrint Arch. Jonas Schupp, Marco Gianvecchio, Alessandro Barenghi, Patrick Karl, Gerardo Pelosi, Georg Sigl
2025	J	`jnl`	Performance and Communication Cost of Hardware Accelerators for Hashing in Post-Quantum Cryptography. ACM Trans. Embed. Comput. Syst. Patrick Karl, Jonas Schupp, Georg Sigl
2025	J	`jnl`	ProbeNav - Fast, precise and repeatable positioning of electromagnetic probes for local Side-Channel Attacks. IACR Cryptol. ePrint Arch. Matthias Probst, Alexander Wiesent, Michael Gruber, Georg Sigl
2025	J	`jnl`	Side-Channel Analysis of Integrate-and-Fire Neurons Within Spiking Neural Networks. IEEE Trans. Circuits Syst. I Regul. Pap. Matthias Probst, Manuel Brosch, Georg Sigl
2025	Misc	`conf`	Special Session - Hardware-Software Co-Design for Machine Learning Systems Made Open-Source. CODES+ISSS Mehdi B. Tahoori, Vincent Meyers, Mahboobe Sadeghipour Roodsari, Huashuangyang Xu, Jürgen Becker, Tanja Harbaum, Felix Frombach, Julian Höfer, Georgios Sotiropoulos, Jörg Henkel, Zeynep Demirdag, Heba Khdr, Hassan Nassar, Ulf Schlichtmann, Johannes Geier, Philipp van Kempen, Georg Sigl, Stefan Koegler, Matthias Probst, Jürgen Teich, Frank Hannig, Muhammad Sabih, Batuhan Sesli, Norbert Wehn, Lukas Steiner, Wolfgang Kunz, Mohamed Shelkamy Ali
2024	Misc	`conf`	A Lightweight Firmware Resilience Engine for IoT Devices Leveraging Minimal Processor Features. CSR Utku Budak, Fabrizio De Santis, Georg Sigl
2024	J	`jnl`	A Masked Hardware Accelerator for Feed-Forward Neural Networks With Fixed-Point Arithmetic. IEEE Trans. Very Large Scale Integr. Syst. Manuel Brosch, Matthias Probst, Matthias Glaser, Georg Sigl
2024	—	`conf`	DOMREP II. HOST Matthias Probst, Manuel Brosch, Michael Gruber, Georg Sigl
2024	A	`conf`	EMDRIVE Architecture: Embedded Distributed Computing and Diagnostics from Sensor to Edge. DATE Patrick Schmidt, Iuliia Topko, Matthias Stammler, Tanja Harbaum, Jürgen Becker, Rico Berner, Omar Ahmed, Jakub Jagielski, Thomas Seidler, Markus Abel, Marius Kreutzer, Maximilian Kirschner, Victor Pazmino Betancourt, Robin Sehm, Lukas Groth, Andrija Neskovic, Rolf Meyer, Saleh Mulhem, Mladen Berekovic, Matthias Probst, Manuel Brosch, Georg Sigl, Thomas Wild, Matthias Ernst, Andreas Herkersdorf, Florian Aigner, Stefan Hommes, Sebastian Lauer, Maximilian Seidler, Thomas Raste, Gasper Skvarc Bozic, Ibai Irigoyen Ceberio, Muhammad Hassan, Albrecht Mayer
2024	C	`conf`	Fault-Simulation-Based Flip-Flop Classification for Reverse Engineering. DDECS Michael Mildner, Michaela Brunner, Michael Gruber, Johanna Baehr, Georg Sigl
2024	C	`conf`	Hardware Honeypot: Setting Sequential Reverse Engineering on a Wrong Track. DDECS Michaela Brunner, Hye-Hyun Lee, Alexander Hepp, Johanna Baehr, Georg Sigl
2024	J	`jnl`	Post-Quantum Signatures on RISC-V with Hardware Acceleration. ACM Trans. Embed. Comput. Syst. Patrick Karl, Jonas Schupp, Tim Fritzmann, Georg Sigl
2024	—	`conf`	RISC-V Triplet: Tapeouts for Security Applications. NorCAS Jonas Schupp, Patrick Karl, Jens Nöpel, Alexander Hepp, Tim Music, Georg Sigl
2024	A	`conf`	ScanCamouflage: Obfuscating Scan Chains with Camouflaged Sequential and Logic Gates. DATE Tarik Ibrahimpasic, Grace Li Zhang, Michaela Brunner, Georg Sigl, Bing Li, Ulf Schlichtmann
2024	C	`conf`	Switch-Glitch : Location of Fault Injection Sweet Spots by Electro-Magnetic Emanation. FDTC Matthias Probst, Michael Gruber, Manuel Brosch, Tim Music, Georg Sigl
2024	—	`conf`	The Impact of Hash Primitives and Communication Overhead for Hardware-Accelerated SPHINCS+. COSADE Patrick Karl, Jonas Schupp, Georg Sigl
2024	J	`jnl`	Uniform instruction set extensions for multiplications in contemporary and post-quantum cryptography. J. Cryptogr. Eng. Felix Oberhansl, Tim Fritzmann, Thomas Pöppelmann, Debapriya Basu Roy, Georg Sigl
2023	J	`jnl`	CPU to FPGA Power Covert Channel in FPGA-SoCs. IACR Cryptol. ePrint Arch. Mathieu Gross, Robert Kunzelmann, Georg Sigl
2023	B	`conf`	Counterfeit Detection by Semiconductor Process Technology Inspection. ETS Matthias Ludwig, Ann-Christin Bette, Bernhard Lippmann, Georg Sigl
2023	—	`conf`	FPGANeedle: Precise Remote Fault Attacks from FPGA to CPU. ASP-DAC Mathieu Gross, Jonas Krautter, Dennis Gnad, Michael Gruber, Georg Sigl, Mehdi B. Tahoori
2023	J	`jnl`	Hardware Honeypot: Setting Sequential Reverse Engineering on a Wrong Track. CoRR Michaela Brunner, Hye-Hyun Lee, Alexander Hepp, Johanna Baehr, Georg Sigl
2023	J	`jnl`	Side-Channel Analysis of Integrate-and-Fire Neurons within Spiking Neural Networks. IACR Cryptol. ePrint Arch. Matthias Probst, Manuel Brosch, Georg Sigl
2023	J	`jnl`	The Impact of Hash Primitives and Communication Overhead for Hardware-Accelerated SPHINCS+. IACR Cryptol. ePrint Arch. Patrick Karl, Jonas Schupp, Georg Sigl
2022	C	`conf`	A Power Side-Channel Attack on the Reed-Muller Reed-Solomon Version of the HQC Cryptosystem. PQCrypto Thomas Schamberger, Lukas Holzbaur, Julian Renner, Antonia Wachter-Zeh, Georg Sigl
2022	J	`jnl`	A Power Side-Channel Attack on the Reed-Muller Reed-Solomon Version of the HQC Cryptosystem. IACR Cryptol. ePrint Arch. Thomas Schamberger, Lukas Holzbaur, Julian Renner, Antonia Wachter-Zeh, Georg Sigl
2022	A	`conf`	A Pragmatic Methodology for Blind Hardware Trojan Insertion in Finalized Layouts. ICCAD Alexander Hepp, Tiago D. Perez, Samuel Pagliarini, Georg Sigl
2022	J	`jnl`	A Pragmatic Methodology for Blind Hardware Trojan Insertion in Finalized Layouts. CoRR Alexander Hepp, Tiago D. Perez, Samuel Pagliarini, Georg Sigl
2022	—	`conf`	A Second Look at the ASCAD Databases. COSADE Maximilian Egger, Thomas Schamberger, Lars Tebelmann, Florian Lippert, Georg Sigl
2022	J	`jnl`	Breaking TrustZone memory isolation and secure boot through malicious hardware on a modern FPGA-SoC. J. Cryptogr. Eng. Mathieu Gross, Nisha Jacob, Andreas Zankl, Georg Sigl
2022	A	`conf`	Counteract Side-Channel Analysis of Neural Networks by Shuffling. DATE Manuel Brosch, Matthias Probst, Georg Sigl
2022	J	`jnl`	Enhancing the Security of FPGA-SoCs via the Usage of ARM TrustZone and a Hybrid-TPM. ACM Trans. Reconfigurable Technol. Syst. Mathieu Gross, Konrad Hohentanner, Stefan Wiehler, Georg Sigl
2022	A	`conf`	Golden Model-Free Hardware Trojan Detection by Classification of Netlist Module Graphs. DATE Alexander Hepp, Johanna Baehr, Georg Sigl
2022	C	`conf`	Hardware Accelerated FrodoKEM on RISC-V. DDECS Patrick Karl, Tim Fritzmann, Georg Sigl
2022	J	`jnl`	Masked Accelerators and Instruction Set Extensions for Post-Quantum Cryptography. IACR Trans. Cryptogr. Hardw. Embed. Syst. Tim Fritzmann, Michiel Van Beirendonck, Debapriya Basu Roy, Patrick Karl, Thomas Schamberger, Ingrid Verbauwhede, Georg Sigl
2022	J	`jnl`	On the application of Two-Photon Absorption for Laser Fault Injection attacks Pushing the physical boundaries for Laser-based Fault Injection. IACR Trans. Cryptogr. Hardw. Embed. Syst. Bodo Selmke, Maximilian Pollanka, Andreas Duensing, Emanuele Strieder, Hayden Wen, Michael Mittermair, Reinhard Kienberger, Georg Sigl
2022	C	`conf`	Open Source Hardware Design and Hardware Reverse Engineering: A Security Analysis. DSD Johanna Baehr, Alexander Hepp, Michaela Brunner, Maja Malenko, Georg Sigl
2022	J	`jnl`	Post-Quantum Signatures on RISC-V with Hardware Acceleration. IACR Cryptol. ePrint Arch. Patrick Karl, Jonas Schupp, Tim Fritzmann, Georg Sigl
2022	J	`jnl`	ROPAD: Enhancing the Digital Ring Oscillator Probing Attempt Detector for Protecting Irregular Data Buses. IEEE Trans. Very Large Scale Integr. Syst. Seyed Hamidreza Moghadas, Michael Pehl, Georg Sigl
2022	J	`jnl`	TOFU - Toggle Count Analysis made simple. IACR Cryptol. ePrint Arch. Michael Gruber, Georg Sigl
2022	J	`jnl`	Toward a Human-Readable State Machine Extraction. ACM Trans. Design Autom. Electr. Syst. Michaela Brunner, Alexander Hepp, Johanna Baehr, Georg Sigl
2021	C	`conf`	Algebraic Fault Analysis of Subterranean 2.0. FDTC Michael Gruber, Patrick Karl, Georg Sigl
2021	J	`jnl`	Beyond Cache Attacks: Exploiting the Bus-based Communication Structure for Powerful On-Chip Microarchitectural Attacks. ACM Trans. Embed. Comput. Syst. Johanna Sepúlveda, Mathieu Gross, Andreas Zankl, Georg Sigl
2021	J	`jnl`	DOMREP-An Orthogonal Countermeasure for Arbitrary Order Side-Channel and Fault Attack Protection. IEEE Trans. Inf. Forensics Secur. Michael Gruber, Matthias Probst, Patrick Karl, Thomas Schamberger, Lars Tebelmann, Michael Tempelmeier, Georg Sigl
2021	J	`jnl`	Finding the Needle in the Haystack: Metrics for Best Trace Selection in Unsupervised Side-Channel Attacks on Blinded RSA. IEEE Trans. Inf. Forensics Secur. Alexander Kulow, Thomas Schamberger, Lars Tebelmann, Georg Sigl
2021	J	`jnl`	Masked Accelerators and Instruction Set Extensions for Post-Quantum Cryptography. IACR Cryptol. ePrint Arch. Tim Fritzmann, Michiel Van Beirendonck, Debapriya Basu Roy, Patrick Karl, Thomas Schamberger, Ingrid Verbauwhede, Georg Sigl
2021	—	`conf`	Tapeout of a RISC-V crypto chip with hardware trojans: a case-study on trojan design and pre-silicon detectability. CF Alexander Hepp, Georg Sigl
2021	—	`conf`	The Cost of OSCORE and EDHOC for Constrained Devices. CODASPY Stefan Hristozov, Manuel Huber, Lei Xu, Jaro Fietz, Marco Liess, Georg Sigl
2021	J	`jnl`	The Cost of OSCORE and EDHOC for Constrained Devices. CoRR Stefan Hristozov, Manuel Huber, Lei Xu, Jaro Fietz, Marco Liess, Georg Sigl
2020	C	`conf`	A Power Side-Channel Attack on the CCA2-Secure HQC KEM. CARDIS Thomas Schamberger, Julian Renner, Georg Sigl, Antonia Wachter-Zeh
2020	J	`jnl`	A Power Side-Channel Attack on the CCA2-Secure HQC KEM. IACR Cryptol. ePrint Arch. Thomas Schamberger, Julian Renner, Georg Sigl, Antonia Wachter-Zeh
2020	A	`conf`	Efficient Hardware/Software Co-Design for Post-Quantum Crypto Algorithm SIKE on ARM and RISC-V based Microcontrollers. ICCAD Debapriya Basu Roy, Tim Fritzmann, Georg Sigl
2020	A	`conf`	Extending the RISC-V Instruction Set for Hardware Acceleration of the Post-Quantum Scheme LAC. DATE Tim Fritzmann, Georg Sigl, Johanna Sepúlveda
2020	—	`conf`	Logic Locking Induced Fault Attacks. ISVLSI Michaela Brunner, Michael Gruber, Michael Tempelmeier, Georg Sigl
2020	J	`jnl`	Machine learning and structural characteristics for reverse engineering. Integr. Johanna Baehr, Alessandro Bernardini, Georg Sigl, Ulf Schlichtmann
2020	—	`conf`	Protecting RESTful IoT Devices from Battery Exhaustion DoS Attacks. HOST Stefan Hristozov, Manuel Huber, Georg Sigl
2020	J	`jnl`	RISQ-V: Tightly Coupled RISC-V Accelerators for Post-Quantum Cryptography. IACR Cryptol. ePrint Arch. Tim Fritzmann, Georg Sigl, Johanna Sepúlveda
2020	J	`jnl`	RISQ-V: Tightly Coupled RISC-V Accelerators for Post-Quantum Cryptography. IACR Trans. Cryptogr. Hardw. Embed. Syst. Tim Fritzmann, Georg Sigl, Johanna Sepúlveda
2020	J	`jnl`	Review of error correction for PUFs and evaluation on state-of-the-art FPGAs. J. Cryptogr. Eng. Matthias Hiller, Ludwig Kürzinger, Georg Sigl
2020	J	`jnl`	Secure and User-Friendly Over-the-Air Firmware Distribution in a Portable Faraday Cage. CoRR Martin Striegel, Florian Jakobsmeier, Yacov Matveev, Johann Heyszl, Georg Sigl
2020	—	`conf`	Secure and user-friendly over-the-air firmware distribution in a portable faraday cage. WISEC Martin Striegel, Johann Heyszl, Florian Jakobsmeier, Yacov Matveev, Georg Sigl
2020	—	`conf`	Timing Resilience for Efficient and Secure Circuits. ASP-DAC Grace Li Zhang, Michaela Brunner, Bing Li, Georg Sigl, Ulf Schlichtmann
2020	J	`jnl`	TimingCamouflage+: Netlist Security Enhancement With Unconventional Timing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Grace Li Zhang, Bing Li, Meng Li, Bei Yu, David Z. Pan, Michaela Brunner, Georg Sigl, Ulf Schlichtmann
2020	J	`jnl`	TimingCamouflage+: Netlist Security Enhancement with Unconventional Timing (with Appendix). CoRR Grace Li Zhang, Bing Li, Meng Li, Bei Yu, David Z. Pan, Michaela Brunner, Georg Sigl, Ulf Schlichtmann
2019	J	`jnl`	A Calibratable Detector for Invasive Attacks. IEEE Trans. Very Large Scale Integr. Syst. Michael Weiner, Wolfgang Wieser, Emili Lupon, Georg Sigl, Salvador Manich
2019	—	`conf`	A Secure Dual-MCU Architecture for Robust Communication of IIoT Devices. MECO Matthias Niedermaier, Dominik Merli, Georg Sigl
2019	J	`jnl`	A Secure Dual-MCU Architecture for Robust Communication of IIoT Devices. CoRR Matthias Niedermaier, Dominik Merli, Georg Sigl
2019	—	`conf`	Breaking TrustZone Memory Isolation through Malicious Hardware on a Modern FPGA-SoC. ASHES@CCS Mathieu Gross, Nisha Jacob, Andreas Zankl, Georg Sigl
2019	J	`jnl`	Efficient Intrusion Detection on Low-Performance Industrial IoT Edge Node Devices. CoRR Matthias Niedermaier, Martin Striegel, Felix Sauer, Dominik Merli, Georg Sigl
2019	B	`conf`	EyeSec: A Retrofittable Augmented Reality Tool for Troubleshooting Wireless Sensor Networks in the Field. EWSN Martin Striegel, Carsten Rolfes, Johann Heyszl, Fabian Helfert, Maximilian Hornung, Georg Sigl
2019	J	`jnl`	EyeSec: A Retrofittable Augmented Reality Tool for Troubleshooting Wireless Sensor Networks in the Field. CoRR Martin Striegel, Carsten Rolfes, Johann Heyszl, Fabian Helfert, Maximilian Hornung, Georg Sigl
2019	—	`conf`	Improving on State Register Identification in Sequential Hardware Reverse Engineering. HOST Michaela Brunner, Johanna Baehr, Georg Sigl
2019	—	`conf`	Machine learning and structural characteristics for reverse engineering. ASP-DAC Johanna Baehr, Alessandro Bernardini, Georg Sigl, Ulf Schlichtmann
2019	J	`jnl`	Network Scanning and Mapping for IIoT Edge Node Device Security. CoRR Matthias Niedermaier, Florian Fischer, Dominik Merli, Georg Sigl
2019	J	`jnl`	Protecting RESTful IoT Devices from Battery Exhaustion DoS Attacks. CoRR Stefan Hristozov, Manuel Huber, Georg Sigl
2019	J	`jnl`	Secure Physical Enclosures from Covers with Tamper-Resistance. IACR Trans. Cryptogr. Hardw. Embed. Syst. Vincent Immler, Johannes Obermaier, Kuan Kuan Ng, Fei Xiang Ke, JinYu Lee, Yak Peng Lim, Wei Koon Oh, Keng Hoong Wee, Georg Sigl
2019	—	`conf`	Using Hardware Software Codesign for Optimised Implementations of High-Speed and Defence in Depth CAESAR Finalists. HOST Michael Tempelmeier, Maximilian Werner, Georg Sigl
2018	J	`jnl`	18 Seconds to Key Exchange: Limitations of Supersingular Isogeny Diffie-Hellman on Embedded Devices. IACR Cryptol. ePrint Arch. Philipp Koppermann, Eduard Pop, Johann Heyszl, Georg Sigl
2018	A*	`conf`	A measurement system for capacitive PUF-based security enclosures. DAC Johannes Obermaier, Vincent Immler, Matthias Hiller, Georg Sigl
2018	—	`conf`	An embedded key management system for PUF-based security enclosures. MECO Johannes Obermaier, Florian Hauschild, Matthias Hiller, Georg Sigl
2018	—	`conf`	B-TREPID: Batteryless tamper-resistant envelope with a PUF and integrity detection. HOST Vincent Immler, Johannes Obermaier, Martin König, Matthias Hiller, Georg Sigl
2018	—	`conf`	DATA - Differential Address Trace Analysis. Krypto-Tag Samuel Weiser, Andreas Zankl, Raphael Spreitzer, Katja Miller, Stefan Mangard, Georg Sigl
2018	A*	`conf`	DATA - Differential Address Trace Analysis: Finding Address-based Side-Channels in Binaries. USENIX Security Symposium Samuel Weiser, Andreas Zankl, Raphael Spreitzer, Katja Miller, Stefan Mangard, Georg Sigl
2018	—	`conf`	Dividing the threshold: Multi-probe localized EM analysis on threshold implementations. HOST Robert Specht, Vincent Immler, Florian Unterstein, Johann Heyszl, Georg Sigl
2018	—	`conf`	Experimental Power and Performance Evaluation of CAESAR Hardware Finalists. ReConFig Michael Tempelmeier, Georg Sigl, Jens-Peter Kaps
2018	J	`jnl`	Fast FPGA Implementations of Diffie-Hellman on the Kummer Surface of a Genus-2 Curve. IACR Trans. Cryptogr. Hardw. Embed. Syst. Philipp Koppermann, Fabrizio De Santis, Johann Heyszl, Georg Sigl
2018	J	`jnl`	High-Resolution EM Attacks Against Leakage-Resilient PRFs Explained - And An Improved Construction. IACR Cryptol. ePrint Arch. Florian Unterstein, Johann Heyszl, Fabrizio De Santis, Robert Specht, Georg Sigl
2018	B	`conf`	High-Resolution EM Attacks Against Leakage-Resilient PRFs Explained - And an Improved Construction. CT-RSA Florian Unterstein, Johann Heyszl, Fabrizio De Santis, Robert Specht, Georg Sigl
2018	C	`conf`	Locked out by Latch-up? An Empirical Study on Laser Fault Injection into Arm Cortex-M Processors. FDTC Bodo Selmke, Kilian Zinnecker, Philipp Koppermann, Katja Miller, Johann Heyszl, Georg Sigl
2018	—	`conf`	The CAESAR-API in the real world - Towards a fair evaluation of hardware CAESAR candidates. HOST Michael Tempelmeier, Fabrizio De Santis, Georg Sigl, Jens-Peter Kaps
2018	J	`jnl`	The Low Area Probing Detector as a Countermeasure Against Invasive Attacks. IEEE Trans. Very Large Scale Integr. Syst. Michael Weiner, Salvador Manich, Rosa Rodríguez-Montañés, Georg Sigl
2018	B	`conf`	Towards the formal verification of security properties of a Network-on-Chip router. ETS Johanna Sepúlveda, Damian Aboul-Hassan, Georg Sigl, Bernd Becker, Matthias Sauer
2018	—	`conf`	Where Technology Meets Security: Key Storage and Data Separation for System-on-Chips. ESSCIRC Georg Sigl, Mathieu Gross, Michael Pehl
2017	—	`conf`	A security-aware routing implementation for dynamic data protection in zone-based MPSoC. SBCCI Johanna Sepúlveda, Ramon Fernandes, César A. M. Marcon, Daniel Florez, Georg Sigl
2017	—	`conf`	Automatic generation of high-performance modular multipliers for arbitrary mersenne primes on FPGAs. HOST Philipp Koppermann, Fabrizio De Santis, Johann Heyszl, Georg Sigl
2017	A	`conf`	ChaCha20-Poly1305 authenticated encryption for high-speed embedded IoT applications. DATE Fabrizio De Santis, Andreas Schauer, Georg Sigl
2017	A	`conf`	Compromising FPGA SoCs using malicious hardware blocks. DATE Nisha Jacob, Carsten Rolfes, Andreas Zankl, Johann Heyszl, Georg Sigl
2017	—	`conf`	EM Side-Channel Analysis of BCH-based Error Correction for PUF-based Key Generation. ASHES@CCS Lars Tebelmann, Michael Pehl, Georg Sigl
2017	J	`jnl`	Efficient security zones implementation through hierarchical group key management at NoC-based MPSoCs. Microprocess. Microsystems Martha Johanna Sepúlveda, Daniel Flórez, Vincent Immler, Guy Gogniat, Georg Sigl
2017	—	`conf`	Exploiting Bus Communication to Improve Cache Attacks on Systems-on-Chips. ISVLSI Johanna Sepúlveda, Mathieu Gross, Andreas Zankl, Georg Sigl
2017	J	`jnl`	Fast FPGA Implementations of Diffie-Hellman on the Kummer Surface of a Genus-2 Curve. IACR Cryptol. ePrint Arch. Philipp Koppermann, Fabrizio De Santis, Johann Heyszl, Georg Sigl
2017	J	`jnl`	Fast and reliable PUF response evaluation from unsettled bistable rings. Microprocess. Microsystems Robert Hesselbarth, Johann Heyszl, Georg Sigl
2017	A	`conf`	How to Break Secure Boot on FPGA SoCs Through Malicious Hardware. CHES Nisha Jacob, Johann Heyszl, Andreas Zankl, Carsten Rolfes, Georg Sigl
2017	J	`jnl`	How to Break Secure Boot on FPGA SoCs through Malicious Hardware. IACR Cryptol. ePrint Arch. Nisha Jacob, Johann Heyszl, Andreas Zankl, Carsten Rolfes, Georg Sigl
2017	J	`jnl`	Low-latency X25519 hardware implementation: breaking the 100 microseconds barrier. Microprocess. Microsystems Philipp Koppermann, Fabrizio De Santis, Johann Heyszl, Georg Sigl
2017	—	`conf`	Pushing the Limits Further: Sub-Atomic AES. VLSI-SoC (Selected Papers) Markus Stefan Wamser, Georg Sigl
2017	C	`conf`	Pushing the limits further: Sub-atomic AES. VLSI-SoC Markus Stefan Wamser, Georg Sigl
2017	—	`conf`	Securing FPGA SoC configurations independent of their manufacturers. SoCC Nisha Jacob, Jakob Wittmann, Johann Heyszl, Robert Hesselbarth, Florian Wilde, Michael Pehl, Georg Sigl, Kai Fischer
2017	—	`conf`	Take a moment and have some t: Hypothesis testing on raw PUF data. HOST Vincent Immler, Matthias Hiller, Johannes Obermaier, Georg Sigl
2017	J	`jnl`	Timing attack on NoC-based systems: Prime+Probe attack and NoC-based protection. Microprocess. Microsystems Cezar Reinbrecht, Altamiro Amadeu Susin, Lilian Bossuet, Georg Sigl, Johanna Sepúlveda
2017	Misc	`conf`	Towards Protected MPSoC Communication for Information Protection against a Malicious NoC. ICCS Johanna Sepúlveda, Andreas Zankl, Daniel Flórez, Georg Sigl
2017	A	`conf`	Towards post-quantum security for IoT endpoints with NTRU. DATE Oscar M. Guillen, Thomas Pöppelmann, Jose Maria Bermudo Mera, Elena Fuentes Bongenaar, Georg Sigl, Johanna Sepúlveda
2017	—	`conf`	Towards trace-driven cache attacks on Systems-on-Chips - exploiting bus communication. ReCoSoC Johanna Sepúlveda, Mathieu Gross, Andreas Zankl, Georg Sigl
2016	J	`jnl`	A flexible framework for mobile device forensics based on cold boot attacks. EURASIP J. Inf. Secur. Manuel Huber, Benjamin Taubmann, Sascha Wessel, Hans P. Reiser, Georg Sigl
2016	—	`conf`	A security aware routing approach for NoC-based MPSoCs. SBCCI Ramon Fernandes, César A. M. Marcon, Rodrigo Cataldo, Jarbas Silveira, Georg Sigl, Martha Johanna Sepúlveda
2016	J	`jnl`	Algebraic Security Analysis of Key Generation with Physical Unclonable Functions. IACR Cryptol. ePrint Arch. Matthias Hiller, Michael Pehl, Gerhard Kramer, Georg Sigl
2016	—	`conf`	An area-optimized serial implementation of ICEPOLE authenticated encryption schemes. HOST Michael Tempelmeier, Fabrizio De Santis, Jens-Peter Kaps, Georg Sigl
2016	J	`jnl`	Area-Efficient PUF-Based Key Generation on System-on-Chips with FPGAs. J. Circuits Syst. Comput. Stefan Gehrer, Georg Sigl
2016	C	`conf`	Attack on a DFA Protected AES by Simultaneous Laser Fault Injections. FDTC Bodo Selmke, Johann Heyszl, Georg Sigl
2016	C	`conf`	Automated Detection of Instruction Cache Leaks in Modular Exponentiation Software. CARDIS Andreas Zankl, Johann Heyszl, Georg Sigl
2016	J	`jnl`	Cherry-Picking Reliable PUF Bits With Differential Sequence Coding. IEEE Trans. Inf. Forensics Secur. Matthias Hiller, Meng-Day (Mandel) Yu, Georg Sigl
2016	—	`conf`	Enhancing Fault Emulation of Transient Faults by Separating Combinational and Sequential Fault Propagation. ACM Great Lakes Symposium on VLSI Ralph Nyberg, Johann Heyszl, Dietmar Heinz, Georg Sigl
2016	C	`conf`	Fast and Reliable PUF Response Evaluation from Unsettled Bistable Rings. DSD Robert Hesselbarth, Georg Sigl
2016	—	`conf`	Hiding Higher-Order Univariate Leakages by Shuffling Polynomial Masking Schemes: A More Efficient, Shuffled, and Higher-Order Masked AES S-box. TIS@CCS Fabrizio De Santis, Tobias Bauer, Georg Sigl
2016	—	`conf`	MaskVer: a tool helping designers detect flawed masking implementations. IVSW Michael Tempelmeier, Georg Sigl
2016	—	`conf`	Online Reliability Testing for PUF Key Derivation. TrustED@CCS Matthias Hiller, Aysun Gurur Önalan, Georg Sigl, Martin Bossert
2016	—	`conf`	Practical Aspects of Quantization and Tamper-Sensitivity for Physically Obfuscated Keys. CS2@HiPEAC Vincent Immler, Maxim Hennig, Ludwig Kürzinger, Georg Sigl
2016	A	`conf`	Practical evaluation of code injection in encrypted firmware updates. DATE Oscar M. Guillen, Dawin Schmidt, Georg Sigl
2016	—	`conf`	Side channel attack on NoC-based MPSoCs are practical: NoC Prime+Probe attack. SBCCI Cezar Reinbrecht, Altamiro Amadeu Susin, Lilian Bossuet, Georg Sigl, Martha Johanna Sepúlveda
2016	C	`conf`	Squeezing Polynomial Masking in Tower Fields - A Higher-Order Masked AES S-Box. CARDIS Fabrizio De Santis, Tobias Bauer, Georg Sigl
2016	—	`conf`	Towards Efficient Evaluation of a Time-Driven Cache Attack on Modern Processors. ESORICS (2) Andreas Zankl, Katja Miller, Johann Heyszl, Georg Sigl
2016	—	`conf`	Towards Side-Channel Secure Firmware Updates - A Minimalist Anomaly Detection Approach. FPS Oscar M. Guillen, Fabrizio De Santis, Ralf Brederlow, Georg Sigl
2016	—	`conf`	Towards risk aware NoCs for data protection in MPSoCs. ReCoSoC Johanna Sepúlveda, Daniel Florez, Ramon Fernandes, César A. M. Marcon, Guy Gogniat, Georg Sigl
2016	C	`conf`	X25519 Hardware Implementation for Low-Latency Applications. DSD Philipp Koppermann, Fabrizio De Santis, Johann Heyszl, Georg Sigl
2015	B	`conf`	A Lightweight Framework for Cold Boot Based Forensics on Mobile Devices. ARES Benjamin Taubmann, Manuel Huber, Sascha Wessel, Lukas Heim, Hans Peter Reiser, Georg Sigl
2015	C	`conf`	A Petite and Power Saving Design for the AES S-Box. DSD Markus Stefan Wamser, Lukas Holzbaur, Georg Sigl
2015	—	`conf`	Aging effects on ring-oscillator-based physical unclonable functions on FPGAs. ReConFig Stefan Gehrer, Sebastien Leger, Georg Sigl
2015	J	`jnl`	Closing the gap between speed and configurability of multi-bit fault emulation environments for security and safety-critical designs. Microprocess. Microsystems Ralph Nyberg, Johann Heyszl, Dirk Rabe, Georg Sigl
2015	J	`jnl`	Fehlerkorrekturverfahren zur sicheren Schlüsselerzeugung mit Physical Unclonable Functions. Datenschutz und Datensicherheit Matthias Hiller, Michael Pehl, Georg Sigl
2015	—	`conf`	Improving Non-profiled Attacks on Exponentiations Based on Clustering and Extracting Leakage from Multi-channel High-Resolution EM Measurements. COSADE Robert Specht, Johann Heyszl, Martin Kleinsteuber, Georg Sigl
2015	—	`conf`	Low-Area Reed Decoding in a Generalized Concatenated Code Construction for PUFs. ISVLSI Matthias Hiller, Ludwig Kurzinger, Georg Sigl, Sven Müelich, Sven Puchinger, Martin Bossert
2015	J	`jnl`	On Error Correction for Physical Unclonable Functions. CoRR Sven Puchinger, Sven Müelich, Martin Bossert, Matthias Hiller, Georg Sigl
2015	C	`conf`	Precise Laser Fault Injections into 90 nm and 45 nm SRAM-cells. CARDIS Bodo Selmke, Stefan Brummer, Johann Heyszl, Georg Sigl
2015	—	`conf`	Side Channel Attacks on Smartphones and Embedded Devices Using Standard Radio Equipment. COSADE Gabriel Goller, Georg Sigl
2015	—	`conf`	Using the reconfigurability of modern FPGAs for highly efficient PUF-based key generation. ReCoSoC Stefan Gehrer, Georg Sigl
2015	C	`conf`	seTPM: Towards Flexible Trusted Computing on Mobile Devices Based on GlobalPlatform Secure Elements. CARDIS Sergej Proskurin, Michael Weiß, Georg Sigl
2014	—	`conf`	A Low Area Probing Detector for Power Efficient Security ICs. RFIDSec Michael Weiner, Salvador Manich, Georg Sigl
2014	—	`conf`	Ciphertext-Only Fault Attacks on PRESENT. LightSec Fabrizio De Santis, Oscar M. Guillen, Ermin Sakic, Georg Sigl
2014	C	`conf`	Closing the Gap between Speed and Configurability of Multi-bit Fault Emulation Environments for Security and Safety-Critical Designs. DSD Ralph Nyberg, Jürgen Nolles, Johann Heyszl, Dirk Rabe, Georg Sigl
2014	J	`jnl`	Error Correction for Physical Unclonable Functions Using Generalized Concatenated Codes. CoRR Sven Müelich, Sven Puchinger, Martin Bossert, Matthias Hiller, Georg Sigl
2014	J	`jnl`	Hardware Trojans: current challenges and approaches. IET Comput. Digit. Tech. Nisha Jacob, Dominik Merli, Johann Heyszl, Georg Sigl
2014	A	`conf`	Increasing the efficiency of syndrome coding for PUFs with helper data compression. DATE Matthias Hiller, Georg Sigl
2014	—	`conf`	Investigating measurement methods for high-resolution electromagnetic field side-channel analysis. ISIC Robert Specht, Johann Heyszl, Georg Sigl
2014	—	`conf`	On Cache Timing Attacks Considering Multi-core Aspects in Virtualized Embedded Systems. INTRUST Michael Weiß, Benjamin Weggenmann, Moritz August, Georg Sigl
2014	Misc	`conf`	On MILS I/O Sharing Targeting Avionic Systems. EDCC Kevin Mueller, Georg Sigl, Benoit Triquet, Michael Paulitsch
2014	—	`conf`	Reconfigurable PUFs for FPGA-based SoCs. ISIC Stefan Gehrer, Georg Sigl
2014	—	`conf`	Risk management in embedded devices using metering applications as example. WESS Oscar M. Guillen, Ralf Brederlow, Ralph Ledwa, Georg Sigl
2014	C	`conf`	Seesaw: An Area-Optimized FPGA Viterbi Decoder for PUFs. DSD Matthias Hiller, Leandro Rodrigues Lima, Georg Sigl
2013	—	`conf`	A new model for estimating bit error probabilities of Ring-Oscillator PUFs. ReCoSoC Matthias Hiller, Georg Sigl, Michael Pehl
2013	—	`conf`	Breaking through fixed PUF block limitations with differential sequence coding and convolutional codes. TrustED@CCS Matthias Hiller, Michael Weiner, Leandro Rodrigues Lima, Maximilian Birkner, Georg Sigl
2013	J	`jnl`	Clustering Algorithms for Non-Profiled Single-Execution Attacks on Exponentiations. IACR Cryptol. ePrint Arch. Johann Heyszl, Andreas Ibing, Stefan Mangard, Fabrizio De Santis, Georg Sigl
2013	C	`conf`	Clustering Algorithms for Non-profiled Single-Execution Attacks on Exponentiations. CARDIS Johann Heyszl, Andreas Ibing, Stefan Mangard, Fabrizio De Santis, Georg Sigl
2013	A	`conf`	Comprehensive analysis of software countermeasures against fault attacks. DATE Nikolaus Theißing, Dominik Merli, Michael Smola, Frederic Stumpf, Georg Sigl
2013	A	`conf`	Differential scan-path: A novel solution for secure design-for-testability. ITC Salvador Manich, Markus S. Wamser, Oscar M. Guillen, Georg Sigl
2013	—	`conf`	Identities for Embedded Systems Enabled by Physical Unclonable Functions. Number Theory and Cryptography Dominik Merli, Georg Sigl, Claudia Eckert
2013	—	`conf`	Localized electromagnetic analysis of RO PUFs. HOST Dominik Merli, Johann Heyszl, Benedikt Heinz, Dieter Schuster, Frederic Stumpf, Georg Sigl
2013	Misc	`conf`	On the Relationship between Correlation Power Analysis and the Stochastic Approach: An ASIC Designer Perspective. INDOCRYPT Fabrizio De Santis, Michael Kasper, Stefan Mangard, Georg Sigl, Oliver Stein, Marc Stöttinger
2013	J	`jnl`	Protecting PUF Error Correction by Codeword Masking. IACR Cryptol. ePrint Arch. Dominik Merli, Frederic Stumpf, Georg Sigl
2012	—	`conf`	Complementary IBS: Application specific error correction for PUFs. HOST Matthias Hiller, Dominik Merli, Frederic Stumpf, Georg Sigl
2012	—	`conf`	Detection of probing attempts in secure ICs. HOST Salvador Manich, Markus S. Wamser, Georg Sigl
2012	B	`conf`	Localized Electromagnetic Analysis of Cryptographic Implementations. CT-RSA Johann Heyszl, Stefan Mangard, Benedikt Heinz, Frederic Stumpf, Georg Sigl
2012	J	`jnl`	Physical Unclonable Functions. Datenschutz und Datensicherheit Dominik Merli, Georg Sigl
2012	—	`conf`	Reliability bound and channel capacity of IBS-based fuzzy embedders. AHS Matthias Hiller, Fabrizio De Santis, Dominik Merli, Georg Sigl
2012	C	`conf`	Strengths and Limitations of High-Resolution Electromagnetic Field Measurements for Side-Channel Analysis. CARDIS Johann Heyszl, Dominik Merli, Benedikt Heinz, Fabrizio De Santis, Georg Sigl
2011	C	`conf`	A Cost-Effective FPGA-based Fault Simulation Environment. FDTC Angelika Janning, Johann Heyszl, Frederic Stumpf, Georg Sigl
2011	A	`conf`	Keynote address: Design of secure systems - Where are the EDA tools? ICCAD Georg Sigl
2011	—	`conf`	Side-Channel Analysis of PUFs and Fuzzy Extractors. TRUST Dominik Merli, Dieter Schuster, Frederic Stumpf, Georg Sigl
1992	A	`conf`	Accurate net models for placement improvement by network flow methods. ICCAD Konrad Doll, Frank M. Johannes, Georg Sigl
1992	J	`jnl`	Parallel algorithms for slicing based final placement Forschungsberichte, TU Munich Henning Spruth, Georg Sigl, Frank Johannes
1992	—	`conf`	Parallel algorithms for slicing based final placement. EURO-DAC Henning Spruth, Georg Sigl
1992	—	`—`	Plazierung der Zellen bei der Layoutsynthese mittels Partitionierung und quadratischer Optimierung. Georg Sigl
1991	A	`conf`	A New Linear Placement Algorithm for Cell Generation. ICCAD Edgar Auer, Werner L. Schiele, Georg Sigl
1991	A*	`conf`	Analytical Placement: A Linear or a Quadratic Objective Function? DAC Georg Sigl, Konrad Doll, Frank M. Johannes
1991	—	`conf`	DOMINO: Deterministic Placement Improvement with Hill-Climbing Capabilities. VLSI Konrad Doll, Frank M. Johannes, Georg Sigl
1991	J	`jnl`	GORDIAN: VLSI placement by quadratic programming and slicing optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jürgen M. Kleinhans, Georg Sigl, Frank M. Johannes, Kurt Antreich
1991	—	`conf`	Goal oriented slicing enumeration through shape function clipping. EURO-DAC Georg Sigl, Ulf Schlichtmann
1988	A	`conf`	GORDIAN: a new global optimization/rectangle dissection method for cell placement. ICCAD Jürgen M. Kleinhans, Georg Sigl, Frank M. Johannes