Georg Georgakos

26 papers A* 1B 1C 7Journal 5Unranked 12
YearRankTypeTitle / Venue / Authors
2019 — conf
From Device Aging Physics to Automated Circuit Reliability Sign Off.
IRPS
Christian Schlünder, Katja Waschneck, Peter Rotter, Susanne Lachenmann, Hans Reisinger, Franz Ungar, Georg Georgakos
2017 C conf
A new 3-bit burst-error correcting code.
IOLTS
Alexander Klockmann, Georg Georgakos, Michael Gössel
2016 B conf
In situ measurement of aging-induced performance degradation in digital circuits.
ETS
Nasim Pour Aryan, Christian Funke, Jens Bargfrede, Cenk Yilmaz, Doris Schmitt-Landsiedel, Georg Georgakos
2015 — conf
A fWLR test structure and method for device reliability monitoring using product relevant circuits.
IRPS
Rolf-Peter Vollertsen, Georg Georgakos, K. Kölpin, C. Olk
2014 C conf
From an analytic NBTI device model to reliability assessment of complex digital circuits.
IOLTS
Nasim Pour Aryan, A. Listl, Leonhard Heiß, Cenk Yilmaz, Georg Georgakos, Doris Schmitt-Landsiedel
2014 — conf
Power efficient digital IC design for a medical application with high reliability requirements.
PATMOS
Nasim Pour Aryan, Nils Heidmann, Martin Wirnshofer, Nico Hellwege, Jonas Pistor, Dagmar Peters-Drolshagen, Georg Georgakos, Steffen Paul, Doris Schmitt-Landsiedel
2013 A* conf
Reliability challenges for electric vehicles: from devices to architecture and systems software.
DAC
Georg Georgakos, Ulf Schlichtmann, Reinhard Schneider, Samarjit Chakraborty
2013 — conf
Reliability monitoring of digital circuits by in situ timing measurement.
PATMOS
Nasim Pour Aryan, Georg Georgakos, Doris Schmitt-Landsiedel
2012 C conf
Adaptive voltage scaling by in-situ delay monitoring for an image processing circuit.
DDECS
Martin Wirnshofer, Leonhard Heiß, Anil Narayan Kakade, Nasim Pour Aryan, Georg Georgakos, Doris Schmitt-Landsiedel
2012 J jnl
On-Line Supply voltage Scaling Based on
J. Circuits Syst. Comput.
Martin Wirnshofer, Nasim Pour Aryan, Leonhard Heiß, Doris Schmitt-Landsiedel, Georg Georgakos
2011 C conf
A variation-aware adaptive voltage scaling technique based on in-situ delay monitoring.
DDECS
Martin Wirnshofer, Leonhard Heiß, Georg Georgakos, Doris Schmitt-Landsiedel
2010 J jnl
Aging-aware Timing Analysis of Combinatorial Circuits on Gate Level (Alterungsanalyse von kombinatorischen Schaltungen auf Gatterebene).
it Inf. Technol.
Dominik Lorenz, Georg Georgakos, Ulf Schlichtmann
2009 C conf
Aging analysis of circuit timing considering NBTI and HCI.
IOLTS
Dominik Lorenz, Georg Georgakos, Ulf Schlichtmann
2009 — conf
Fast stability analysis of large-scale SRAM arrays and the impact of NBTI degradation.
ESSCIRC
Stefan Drapatz, Thomas Fischer, Karl Hofmann, Ettore Amirante, Peter Huber, Martin Ostermayr, Georg Georgakos, Doris Schmitt-Landsiedel
2008 — conf
A Design Space Comparison of 6T and 8T SRAM Core-Cells.
PATMOS
Florian Bauer, Georg Georgakos, Doris Schmitt-Landsiedel
2007 J jnl
A 90-nm CMOS Low-Power GSM/EDGE Multimedia-Enhanced Baseband Processor With 380-MHz ARM926 Core and Mixed-Signal Extensions.
IEEE J. Solid State Circuits
Thomas Lüftner, Jörg Berthold, Christian Pacha, Georg Georgakos, Guillaume Sauzon, Olaf Hömke, Jurij Beshenar, Peter Mahrla, Knut M. Just, Peter Hober, Stephan Henzler, Doris Schmitt-Landsiedel, Andre Yakovleff, Axel Klein, Richard J. Knight, Pramod Acharya, Andre Bonnardot, Steffen Buch, Matthias Sauer
2007 J jnl
In-Situ Delay Characterization and Local Supply Voltage Adjustment for Compensation of Local Parametric Variations.
IEEE J. Solid State Circuits
Matthias Eireiner, Stephan Henzler, Georg Georgakos, Jörg Berthold, Doris Schmitt-Landsiedel
2007 — conf
Layout options for stability tuning of SRAM cells in multi-gate-FET technologies.
ESSCIRC
Florian Bauer, Klaus von Arnim, Christian Pacha, Thomas Schulz, Michael Fulde, Axel Nackaerts, M. Jurczak, Wade Xiong, K. T. San, C. Rinn Cleavelin, Klaus Schruefer, Georg Georgakos, Doris Schmitt-Landsiedel
2007 C conf
Soft Error Rates in 65nm SRAMs--Analysis of new Phenomena.
IOLTS
Franz X. Ruckerbauer, Georg Georgakos
2006 — conf
A 90nm CMOS low-power GSM/EDGE multimedia-enhanced baseband processor with 380MHz ARM9 and mixed-signal extensions.
ISSCC
Thomas Lüftner, Jörg Berthold, Christian Pacha, Georg Georgakos, Guillaume Sauzon, Olaf Hömke, Jurij Beshenar, Peter Mahrla, Knut M. Just, Peter Hober, Stephan Henzler, Doris Schmitt-Landsiedel, Andre Yakovleff, Axel Klein, Richard J. Knight, Pramod Acharya, Hamid Mabrouki, Goulhamid Juhoor, Matthias Sauer
2006 J jnl
Dynamic state-retention flip-flop for fine-grained power gating with small design and power overhead.
IEEE J. Solid State Circuits
Stephan Henzler, Georg Georgakos, Matthias Eireiner, Thomas Nirschl, Christian Pacha, Jörg Berthold, Doris Schmitt-Landsiedel
2005 — conf
Dynamic state-retention flip flop for fine-grained sleep-transistor scheme.
ESSCIRC
Stephan Henzler, Thomas Nirschi, Christian Pacha, Peter Spindler, Philip Teichmann, Michael Fulde, Jürgen Fischer, Matthias Eireiner, Thomas Fischer, Georg Georgakos, Jörg Berthold, Doris Schmitt-Landsiedel
2004 — conf
Single Supply Voltage High-Speed Semi-dynamic Level-Converting Flip-Flop with Low Power and Area Consumption.
PATMOS
Stephan Henzler, Georg Georgakos, Jörg Berthold, Doris Schmitt-Landsiedel
2004 — conf
Two Level Compact Simulation Methodology for Timing Analysis of Power-Switched Circuits.
PATMOS
Stephan Henzler, Georg Georgakos, Jörg Berthold, Doris Schmitt-Landsiedel
2003 C conf
Design Aspects and Technological Scaling Limits of ZigZag Circuit Block Switch-Off Schemes.
VLSI-SOC
Stephan Henzler, Markus Koban, Doris Schmitt-Landsiedel, Jörg Berthold, Georg Georgakos
2003 — conf
Impact of Gate Leakage on Efficiency of Circuit Block Switch-Off Schemes.
VLSI-SoC (Selected Papers)
Stephan Henzler, Philip Teichmann, Markus Koban, Jörg Berthold, Georg Georgakos, Doris Schmitt-Landsiedel