Geoffrey Yeap

15 papers Journal 6Unranked 9
YearRankTypeTitle / Venue / Authors
2025 — conf
A 38.1Mb/mm
ISSCC
Tsung-Yung Jonathan Chang, Yen-Huei Chen, K. Venkateswara Reddy, Nikhil Puri, Teja Masina, Kuo-Cheng Lin, Po-Sheng Wang, Yangsyu Lin, Chih-Yu Lin, Yi-Hsin Nien, Hidehiro Fujiwara, Ku-Feng Lin, Ming-Hung Chang, Ching-Wei Wu, Robin Lee, Yih Wang, Hung-Jen Liao, Quincy Li, Ping-Wei Wang, Geoffrey Yeap
2023 — conf
A 4.24GHz 128X256 SRAM Operating Double Pump Read Write Same Cycle in 5nm Technology.
VLSI Technology and Circuits
Nick Zhang, Young Suk Kim, Peter Hsu, Samsoo Kim, Derek Tao, Hung-Jen Liao, Ping-Wei Wang, Geoffrey Yeap, Quincy Li, Tsung-Yung Jonathan Chang
2021 J jnl
A 5-nm 135-Mb SRAM in EUV and High-Mobility Channel FinFET Technology With Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-V
IEEE J. Solid State Circuits
Tsung-Yung Jonathan Chang, Yen-Huei Chen, Wei-Min Chan, Hank Cheng, Po-Sheng Wang, Yangsyu Lin, Hidehiro Fujiwara, Robin Lee, Hung-Jen Liao, Ping-Wei Wang, Geoffrey Yeap, Quincy Li
2020 — conf
15.1 A 5nm 135Mb SRAM in EUV and High-Mobility-Channel FinFET Technology with Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-VMIN Applications.
ISSCC
Jonathan Chang, Yen-Huei Chen, Gary Chan, Hank Cheng, Po-Sheng Wang, Yangsyu Lin, Hidehiro Fujiwara, Robin Lee, Hung-Jen Liao, Ping-Wei Wang, Geoffrey Yeap, Quincy Li
2016 — conf
-197dBc/Hz FOM 4.3-GHz VCO Using an addressable array of minimum-sized nmos cross-coupled transistor pairs in 65-nm CMOS.
VLSI Circuits
Amit Jha, Ali Ahmadi, Sandeep Kshattry, T. Cao, K. Liao, Geoffrey Yeap, Yiorgos Makris, Kenneth K. O
2016 J jnl
Single Bit-Line 7T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Performance and Energy in 14 nm FinFET Technology.
IEEE Trans. Circuits Syst. I Regul. Pap.
Younghwi Yang, Hanwool Jeong, Seung Chul Song, Joseph Wang, Geoffrey Yeap, Seong-Ook Jung
2016 — conf
Unified Technology Optimization Platform using Integrated Analysis (UTOPIA) for holistic technology, design and system co-optimization at <= 7nm nodes.
VLSI Circuits
Seung Chul Song, J. Xu, D. Yang, K. Rim, P. Feng, Jerry Bao, J. Zhu, Joseph Wang, G. Nallapati, Mustafa Badaroglu, Praneeth Narayanasetti, B. Bucki, Jeff Fischer, Geoffrey Yeap
2015 — conf
Holistic technology optimization and key enablers for 7nm mobile SoC.
VLSIC
Seung Chul Song, J. Xu, N. N. Mojumder, K. Rim, D. Yang, Jerry Bao, J. Zhu, Joseph Wang, Mustafa Badaroglu, V. Machkaoutsan, Praneeth Narayanasetti, B. Bucki, Jeff Fischer, Geoffrey Yeap
2015 J jnl
SRAM Design for 22-nm ETSOI Technology: Selective Cell Current Boosting and Asymmetric Back-Gate Write-Assist Circuit.
IEEE Trans. Circuits Syst. I Regul. Pap.
Younghwi Yang, Juhyun Park, Seung Chul Song, Joseph Wang, Geoffrey Yeap, Seong-Ook Jung
2015 J jnl
Single-Ended 9T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Read Performance in 22-nm FinFET Technology.
IEEE Trans. Very Large Scale Integr. Syst.
Younghwi Yang, Juhyun Park, Seung Chul Song, Joseph Wang, Geoffrey Yeap, Seong-Ook Jung
2015 — conf
Transistor-interconnect mobile system-on-chip co-design method for holistic battery energy minimization.
VLSIC
N. N. Mojumder, Seung Chul Song, K. Rim, J. Xu, Joseph Wang, J. Zhu, Milena Vratonjic, K. Lin, Martin Saint-Laurent, Paul Bassett, Geoffrey Yeap
2014 J jnl
Improved device variability in scaled MOSFETs with deeply retrograde channel profile.
Microelectron. Reliab.
Jason Woo, Po-Yen Chien, Frank Yang, Seung Chul Song, P. R. Chidi Chidambaram, Joseph Wang, Geoffrey Yeap
2014 — conf
Technology-design-manufacturing co-optimization for advanced mobile SoCs.
CICC
Geoffrey Yeap
2011 J jnl
FinFET based SRAM bitcell design for 32 nm node and below.
Microelectron. J.
Seung Chul Song, M. Abu-Rahma, Geoffrey Yeap
2010 — conf
BSIM4-based lateral diode model for LNA co-designed with ESD protection circuit.
ISQED
Ming-Ta Yang, Yang Du, Charles Teng, Tony Chang, Eugene Worley, Ken Liao, You-Wen Yau, Geoffrey Yeap