Geng Zhang

11 papers Journal 8Unranked 3
YearRankTypeTitle / Venue / Authors
2026 J jnl
A 61.4 Gb/s/mm Wireline Transceiver Using a 7 bit-Over-8 Lane Symmetric Correlated Coding for High-Density Interconnects.
IEEE Trans. Circuits Syst. I Regul. Pap.
Mingche Lai, Geng Zhang, Fangxu Lv, Liquan Xiao, Xuqiang Zheng, Heng Huang, Kewei Xin, Liangyong Yuan, Ruixiao Kuai, Bolin Ren, Ruotian Yin, Guohe Zhang, Chao Fan
2025 J jnl
A Novel High-Speed Adaptive Duobinary Digital Detector Based on the Feed-Forward Equalizer and the Maximum Likelihood Sequence Detector for Wireline Transceivers.
IEEE Trans. Very Large Scale Integr. Syst.
Chaolong Xu, Fangxu Lv, Mingche Lai, Xingyun Qi, Qiang Wang, Zhang Luo, Shijie Li, Geng Zhang
2024 J jnl
A 56-Gb/s,0.708 pJ/bit single-ended simultaneous bidirectional transceiver with hybrid errors cancellation techniques for die-to-die interface.
Microelectron. J.
Bolin Ren, Fangxu Lv, Mingche Lai, Liquan Xiao, Geng Zhang, Xuqiang Zheng, Zhang Luo, Jiaqing Xu
2024 J jnl
A fully digital timing background calibration algorithm based on first-order auto-correlation for time-interleaved ADCs.
Microelectron. J.
Meng Li, Fangxu Lv, Mingche Lai, Xuqiang Zheng, Heng Huang, Xingyun Qi, Geng Zhang
2024 J jnl
A low jitter and low reference spur 5GHz PLL with quadrature charge-sampling PD in 28nm CMOS process.
IEICE Electron. Express
Wenchen Wang, Fangxu Lv, Zhengbin Pang, Heng Huang, Zhang Luo, Xingyun Qi, Jiaqing Xu, Geng Zhang, Kewei Xin, Chengzhuo Zhao
2024 J jnl
Frequency Domain Modeling and Performance Analysis of Injection-Locked LC Oscillator.
IEEE Trans. Circuits Syst. II Express Briefs
Kewei Xin, Mingche Lai, Fangxu Lv, Xuqiang Zheng, Kaile Guo, Zhengbin Pang, Chaolong Xu, Geng Zhang, Wenchen Wang, Meng Li
2023 — conf
A Low BER Cooperative-adaptive-equalizer for Serial Receiver in HPC Networks.
HPCC/DSS/SmartCity/DependSys
Mingche Lai, Fangxu Lv, Geng Zhang, Chaolong Xu
2023 — conf
Low-Jitter Retimer Circuits for High-Performance Computer Optical Communications.
ICCEIC
Qing Liu, Heming Wang, Fangxu Lv, Geng Zhang, Dongbin Lv
2022 J jnl
A 33.33 Gb/s/wire pin-efficient 1.06 pJ/bit wireline transceiver based on CNRZ-5 for Chiplet in 28 nm CMOS.
Microelectron. J.
Mingche Lai, Geng Zhang, Fangxu Lv, Xuqiang Zheng, Heming Wang, Dongbin Lv, Chaolong Xu, Xingyun Qi
2022 J jnl
A CNRZ-7 Based Wireline Transceiver With High-Bandwidth-Density, Low-Power for D2D Communication.
IEEE Access
Geng Zhang, Mingche Lai, Fangxu Lyu, Xuqiang Zheng, Heming Wang, Dongbin Lv, Chaolong Xu, Xingyun Qi, Qing Liu
2021 — conf
A 5-156.25Gb/s high pin efficiency Receiver Based on CNRZ-5 for USR High-Speed Interface.
ASICON
Geng Zhang, Fangxu Lv, Zhengbin Pang, Heming Wang, Dongbin Lv, Tao Liu, Jinwang Zhang