Geert Van der Plas

115 papers A* 5A 7C 2Misc 1Journal 43Unranked 56

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	Iterative Layout-Aware Power, Thermal, and IR-Drop Co-Optimization: Ensuring Convergency in 3D-ICs. IEEE J. Emerg. Sel. Topics Circuits Syst. Mohamed Naeim, Dwaipayan Biswas, Yun Dai, Odysseas Zografos, Herman Oprins, Geert Van der Plas, CT Kao, Pinhong Chen, Dragomir Milojevic
2024	—	`conf`	Thermal Analysis of 3D Stacking and BEOL Technologies with Functional Partitioning of Many-Core RISC-V SoC. ISVLSI Mohamed Naeim, Herman Oprins, Sudipta Das, Geert Van der Plas, Yun Dai, Pinhong Chen, CT Kao, Dwaipayan Biswas, Dragomir Milojevic
2024	—	`conf`	Toward 0 V ESD Protection in 2.5D/3D Advanced Bonding Technology. VLSI Technology and Circuits S.-H. Lin, Marko Simicic, N. Pantano, S.-H. Chen, Geert Van der Plas, Eric Beyne, Piet Wambacq
2023	—	`conf`	Design Enablement of 3-Dies Stacked 3D-ICs Using Fine-Pitch Hybrid-Bonding and TSVs. 3DIC Mohamed Naeim, Hanqi Yang, Pinhong Chen, Rong Bao, Antoine Dekeyser, Giuliano Sisto, Moritz Brunion, Rongmei Chen, Geert Van der Plas, Eric Beyne, Dragomir Milojevic
2023	J	`jnl`	Impact of gate-level clustering on automated system partitioning of 3D-ICs. CoRR Quentin Delhaye, Eric Beyne, Joël Goossens, Geert Van der Plas, Dragomir Milojevic
2023	J	`jnl`	Impact of gate-level clustering on automated system partitioning of 3D-ICs. Microelectron. J. Quentin Delhaye, Eric Beyne, Joël Goossens, Geert Van der Plas, Dragomir Milojevic
2023	A	`conf`	NimbleAI: Towards Neuromorphic Sensing-Processing 3D-integrated Chips. DATE Xabier Iturbe, Nassim Abderrahmane, Jaume Abella, Sergi Alcaide, Eric Beyne, Henri-Pierre Charles, Christelle Charpin-Nicolle, Lars Chittka, Angélica Dávila, Arne Erdmann, Carles Estrada, Ander Fernández, Anna Fontanelli, José Flich, Gianluca Furano, Alejandro Hernán Gloriani, Erik Isusquiza, Radu Grosu, Carles Hernández, Daniele Ielmini, David Jackson, Maha Kooli, Nicola Lepri, Bernabé Linares-Barranco, Jean-Loup Lachese, Eric Laurent, Menno Lindwer, Frank Linsenmaier, Mikel Luján, Karel Masarík, Nele Mentens, Orlando Moreira, Chinmay Nawghane, Luca Peres, Jean-Philippe Noel, Arash Pourtaherian, Christoph Posch, Peter Priller, Zdenek Prikryl, Felix Resch, Oliver Rhodes, Todor P. Stefanov, Moritz Storring, Michele Taliercio, Rafael Tornero, Marcel D. van de Burgwal, Geert Van der Plas, Elisa Vianello, Pavel Zaykov
2023	—	`conf`	Towards Chip-Package-System Co-optimization of Thermally-limited System-On-Chips (SOCs). IRPS Subrat Mishra, Sankatali Venkateswarlu, Bjorn Vermeersch, Moritz Brunion, Melina Lofrano, Dawit Burusie Abdi, Herman Oprins, Dwaipayan Biswas, Odysseas Zografos, Gaspard Hiblot, Geert Van der Plas, Pieter Weckx, Geert Hellings, James Myers, Francky Catthoor, Julien Ryckaert
2022	—	`conf`	(Why do we need) Wireless Heterogeneous Integration (anyway?). VLSI Technology and Circuits Michaël Peeters, S. Sinha, Xiao Sun, Claude Desset, Giuseppe Gramegna, John Slabbekoorn, Pieter Bex, Nelson Pinho, Tomas Webers, Dimitrios Velenis, Andy Miller, Nadine Collaert, Geert Van der Plas, Eric Beyne, Martijn Huynen, R. Broucke
2022	J	`jnl`	84%-Efficiency Fully Integrated Voltage Regulator for Computing Systems Enabled by 2.5-D High-Density MIM Capacitor. IEEE Trans. Very Large Scale Integr. Syst. Hesheng Lin, Dimitrios Velenis, Philip Nolmans, Xiao Sun, Francky Catthoor, Rudy Lauwereins, Geert Van der Plas, Eric Beyne
2022	—	`conf`	Backside PDN and 2.5D MIMCAP to Double Boost 2D and 3D ICs IR-Drop beyond 2nm Node. VLSI Technology and Circuits Rongmei Chen, Giuliano Sisto, Michele Stucchi, Anne Jourdain, Kenichi Miyaguchi, Pieter Schuddinck, P. Woeltgens, H. Lin, Naveen Kakarla, Anabela Veloso, Dragomir Milojevic, Odysseas Zografos, Pieter Weckx, Geert Hellings, Geert Van der Plas, Julien Ryckaert, Eric Beyne
2022	J	`jnl`	Efficient Backside Power Delivery for High-Performance Computing Systems. IEEE Trans. Very Large Scale Integr. Syst. Hesheng Lin, Geert Van der Plas, Xiao Sun, Dimitrios Velenis, Francky Catthoor, Rudy Lauwereins, Eric Beyne
2022	—	`conf`	Enabling Active Backside Technology for ESD and LU Reliability in DTCO/STCO. VLSI Technology and Circuits Kateryna Serbulova, S.-H. Chen, Geert Hellings, Anabela Veloso, Anne Jourdain, Dimitri Linten, Jo De Boeck, Guido Groeseneken, Julien Ryckaert, Geert Van der Plas, Eric Beyne, Eugenio Dentoni Litta, Naoto Horiguchi
2022	—	`conf`	Opportunities of Chip Power Integrity and Performance Improvement through Wafer Backside (BS) Connection: Invited Paper. SLIP Rongmei Chen, Giuliano Sisto, Odysseas Zografos, Dragomir Milojevic, Pieter Weckx, Geert Van der Plas, Eric Beyne
2022	—	`conf`	Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails. VLSI Technology and Circuits Anabela Veloso, Anne Jourdain, D. Radisic, Rongmei Chen, G. Arutchelvan, B. O'Sullivan, Hiroaki Arimura, Michele Stucchi, An De Keersgieter, M. Hosseini, T. Hopf, K. D'Have, S. Wang, E. Dupuy, G. Mannaert, Kevin Vandersmissen, S. Iacovo, P. Marien, S. Choudhury, Filip Schleicher, F. Sebaai, Yusuke Oniki, X. Zhou, A. Gupta, Tom Schram, B. Briggs, C. Lorant, E. Rosseel, Andriy Hikavyy, Roger Loo, J. Geypen, D. Batuk, G. T. Martinez, J. P. Soulie, Katia Devriendt, B. T. Chan, S. Demuynck, Gaspard Hiblot, Geert Van der Plas, Julien Ryckaert, Gerald Beyer, E. Dentoni Litta, Eric Beyne, Naoto Horiguchi
2021	—	`conf`	Design And Sign-off Methodologies For Wafer-To-Wafer Bonded 3D-ICs At Advanced Nodes (invited). SLIP Giuliano Sisto, Rongmei Chen, Richard Chou, Geert Van der Plas, Eric Beyne, Rod Metcalfe, Dragomir Milojevic
2021	—	`conf`	Design and Technology Solutions for 3D Integrated High Performance Systems. VLSI Circuits Geert Van der Plas, Eric Beyne
2019	—	`conf`	Comparative Analysis of the Degradation Mechanisms in Logic and I/O FinFET Devices Induced by Plasma Damage. IRPS Gaspard Hiblot, Yefan Liu, Geert Hellings, Geert Van der Plas
2019	—	`conf`	Design Enablement of Fine Pitch Face-to-Face 3D System Integration using Die-by-Die Place & Route. 3DIC Giuliano Sisto, Peter Debacker, Rongmei Chen, Geert Van der Plas, Richard Chou, Eric Beyne, Dragomir Milojevic
2019	—	`conf`	Process Complexity and Cost Considerations of Multi-Layer Die Stacks. 3DIC Dimitrios Velenis, Joeri De Vos, Soon-Wook Kim, Jaber Derakhshandeh, Pieter Bex, Giovanni Capuz, Samuel Suhard, Kenneth June Rebibis, Stefaan Van Huylenbroeck, Erik Jan Marinissen, Alain Phommahaxay, Andy Miller, Gerald Beyer, Geert Van der Plas, Eric Beyne
2018	J	`jnl`	A study on substrate noise coupling among TSVs in 3D chip stack. IEICE Electron. Express Yuuki Araga, Makoto Nagata, Joeri De Vos, Geert Van der Plas, Eric Beyne
2018	—	`conf`	TSV process-induced MOS reliability degradation. IRPS Yunlong Li, Michele Stucchi, Stefaan Van Huylenbroeck, Geert Van der Plas, Gerald Beyer, Eric Beyne, Kristof Croes
2016	—	`conf`	High-density and low-leakage novel embedded 3D MIM capacitor on Si interposer. 3DIC C. Roda Neve, Mikael Detalle, Philip Nolmans, Yunlong Li, Joeri De Vos, Geert Van der Plas, Gerald Beyer, Eric Beyne
2015	—	`conf`	Active-lite interposer for 2.5 & 3D integration. VLSIC Geert Hellings, Mirko Scholz, Mikael Detalle, Dimitrios Velenis, Muriel de Potter de ten Broeck, C. Roda Neve, Y. Li, Stefaan Van Huylenbroeck, Shih-Hung Chen, Erik Jan Marinissen, Antonio La Manna, Geert Van der Plas, Dimitri Linten, Eric Beyne, Aaron Thean
2015	—	`conf`	Processing active devices on Si interposer and impact on cost. 3DIC Dimitrios Velenis, Mikael Detalle, Geert Hellings, Mirko Scholz, Erik Jan Marinissen, Geert Van der Plas, Antonio La Manna, Andy Miller, Dimitri Linten, Eric Beyne
2015	—	`conf`	Thermal experimental and modeling analysis of high power 3D packages. ICICDT Herman Oprins, Vladimir Cherman, Geert Van der Plas, F. L. T. Maggioni, Joeri De Vos, Eric Beyne
2015	—	`conf`	Through silicon via to FinFET noise coupling in 3-D integrated circuits. ICICDT A. Rouhi Najaf Abadi, W. Guo, X. Sun, K. Ben Ali, Jean-Pierre Raskin, Martin Rack, C. Roda Neve, M. Choi, V. Moroz, Geert Van der Plas, Ingrid De Wolf, Eric Beyne, Philippe P. Absil
2014	—	`conf`	Analysis of 3D interconnect performance: Effect of the Si substrate resistivity. 3DIC X. Sun, Geert Van der Plas, Mikael Detalle, Eric Beyne
2014	J	`jnl`	Chip-Package Interaction in 3D stacked IC packages using Finite Element Modelling. Microelectron. Reliab. Bart Vandevelde, Andrej Ivankovic, B. Debecker, Melina Lofrano, Kris Vanstreels, Wei Guo, Vladimir Cherman, Marcel Gonzalez, Geert Van der Plas, Ingrid De Wolf, Eric Beyne, Zsolt Tokei
2014	—	`conf`	Comparative study of 3D stacked IC and 3D interposer integration: Processing and assembly challenges. 3DIC Joeri De Vos, Vladimir Cherman, Mikael Detalle, Teng Wang, Abdellah Salahouelhadj, Robert Daily, Geert Van der Plas, Eric Beyne
2013	—	`conf`	Design issues in heterogeneous 3D/2.5D integration. ASP-DAC Dragomir Milojevic, Pol Marchal, Erik Jan Marinissen, Geert Van der Plas, Diederik Verkest, Eric Beyne
2013	—	`conf`	Session 15 overview: Data converter techniques. ISSCC Michael H. Perrott, Geert Van der Plas
2012	—	`conf`	3D chip package interaction thermo-mechanical challenges: Proximity effects of Through Silicon vias and μ-bumps. ICICDT Wei Guo, Geert Van der Plas, Andrej Ivankovic, Geert Eneman, Vladimir Cherman, Bart De Wachter, Abdelkarim Mercha, Mario Gonzalez, Yann Civale, Augusto Redolfi, Thibault Buisson, A. Jourdan, Bart Vandevelde, Kenneth J. Rebibis, Ingrid De Wolf, Antonio La Manna, Gerald Beyer, Eric Beyne, Bart Swinnen
2012	J	`jnl`	A 6-Bit 50-MS/s Threshold Configuring SAR ADC in 90-nm Digital CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. Pierluigi Nuzzo, Claudio Nani, Costantino Armiento, Alberto L. Sangiovanni-Vincentelli, Jan Craninckx, Geert Van der Plas
2012	J	`jnl`	RF-to-Baseband Digitization in 40 nm CMOS With RF Bandpass ΔΣ Modulator and Polyphase Decimation Filter. IEEE J. Solid State Circuits Ewout Martens, André Bourdoux, Aïssa Couvreur, Robert Fasthuber, Peter Van Wesemael, Geert Van der Plas, Jan Craninckx, Julien Ryckaert
2011	A*	`conf`	3D heterogeneous system integration: application driver for 3D technology development. DAC Eric Beyne, Pol Marchal, Geert Van der Plas
2011	A	`conf`	An analytical compact model for estimation of stress in multiple Through-Silicon Via configurations. DATE Geert Eneman, J. Cho, V. Moroz, Dragomir Milojevic, M. Choi, Kristin De Meyer, Abdelkarim Mercha, Eric Beyne, Thomas Hoffmann, Geert Van der Plas
2011	—	`conf`	Analysis of microbump induced stress effects in 3D stacked IC technologies. 3DIC Andrej Ivankovic, Geert Van der Plas, V. Moroz, M. Choi, Vladimir Cherman, Abdelkarim Mercha, Paul Marchal, Marcel Gonzalez, Geert Eneman, Wenqi Zhang, Thibault Buisson, Mikael Detalle, Antonio La Manna, Diederik Verkest, Gerald Beyer, Eric Beyne, Bart Vandevelde, Ingrid De Wolf, Dirk Vandepitte
2011	—	`conf`	DRAM-on-logic Stack - Calibrated thermal and mechanical models integrated into PathFinding flow. CICC Dragomir Milojevic, Herman Oprins, Julien Ryckaert, Paul Marchal, Geert Van der Plas
2011	J	`jnl`	Design Issues and Considerations for Low-Cost 3-D TSV IC Technology. IEEE J. Solid State Circuits Geert Van der Plas, Paresh Limaye, Igor Loi, Abdelkarim Mercha, Herman Oprins, Cristina Torregiani, Steven Thijs, Dimitri Linten, Michele Stucchi, Guruprasad Katti, Dimitrios Velenis, Vladimir Cherman, Bart Vandevelde, Veerle Simons, Ingrid De Wolf, Riet Labie, Dan Perry, Stephane Bronckers, Nikolaos Minas, Miro Cupac, Wouter Ruythooren, Jan Van Olmen, Alain Phommahaxay, Muriel de Potter de ten Broeck, Ann Opdebeeck, Michal Rakowski, Bart De Wachter, Morin Dehan, Marc Nelis, Rahul Agarwal, Antonio Pullini, Federico Angiolini, Luca Benini, Wim Dehaene, Youssef Travaly, Eric Beyne, Paul Marchal
2011	J	`jnl`	Fine grain thermal modeling and experimental validation of 3D-ICs. Microelectron. J. Herman Oprins, Adi Srinivasan, Miroslav Cupák, Vladimir Cherman, Cristina Torregiani, Michele Stucchi, Geert Van der Plas, Paul Marchal, Bart Vandevelde, E. Cheng
2011	—	`conf`	In-tier diagnosis of power domains in 3D TSV ICs. 3DIC Yuuki Araga, Makoto Nagata, Geert Van der Plas, Jaemin Kim, Nikolaos Minas, Pol Marchal, Youssef Travaly, Michael Libois, Antonio La Manna, Wenqi Zhang, Eric Beyne
2011	—	`ch.`	Low-Power ADCs for Bio-Medical Applications. Bio-Medical CMOS ICs Jan Craninckx, Geert Van der Plas
2010	C	`conf`	3D integration: Circuit design, test, and reliability challenges. IOLTS Nikolaos Minas, Ingrid De Wolf, Erik Jan Marinissen, Michele Stucchi, Herman Oprins, Abdelkarim Mercha, Geert Van der Plas, Dimitrios Velenis, Pol Marchal
2010	—	`conf`	A 100kHz-10MHz BW, 78-to-52dB DR, 4.6-to-11mW flexible SC ΣΔ modulator in 1.2-V 90-nm CMOS. ESSCIRC Alonso Morgado, Rocío del Río, José M. de la Rosa, Lynn Bos, Julien Ryckaert, Geert Van der Plas
2010	J	`jnl`	A 2.6 mW 6 bit 2.2 GS/s Fully Dynamic Pipeline ADC in 40 nm Digital CMOS. IEEE J. Solid State Circuits Bob Verbruggen, Jan Craninckx, Maarten Kuijk, Piet Wambacq, Geert Van der Plas
2010	—	`conf`	A 2.6mW 6b 2.2GS/s 4-times interleaved fully dynamic pipelined ADC in 40nm digital CMOS. ISSCC Bob Verbruggen, Jan Craninckx, Maarten Kuijk, Piet Wambacq, Geert Van der Plas
2010	J	`jnl`	A Single-Bit 500 kHz-10 MHz Multimode Power-Performance Scalable 83-to-67 dB DR CTΔΣ for SDR in 90 nm Digital CMOS. IEEE J. Solid State Circuits Pieter Crombez, Geert Van der Plas, Michiel Steyaert, Jan Craninckx
2010	—	`conf`	Design issues and considerations for low-cost 3D TSV IC technology. ISSCC Geert Van der Plas, Paresh Limaye, Abdelkarim Mercha, Herman Oprins, Cristina Torregiani, Steven Thijs, Dimitri Linten, Michele Stucchi, Guruprasad Katti, Dimitrios Velenis, Domae Shinichi, Vladimir Cherman, Bart Vandevelde, Veerle Simons, Ingrid De Wolf, Riet Labie, Dan Perry, Stephane Bronckers, Nikolaos Minas, Miro Cupac, Wouter Ruythooren, Jan Van Olmen, Alain Phommahaxay, Muriel de Potter de ten Broeck, Ann Opdebeeck, Michal Rakowski, Bart De Wachter, Morin Dehan, Marc Nelis, Rahul Agarwal, Wim Dehaene, Youssef Travaly, Pol Marchal, Eric Beyne
2010	J	`jnl`	Multirate Cascaded Discrete-Time Low-Pass ΔΣ Modulator for GSM/Bluetooth/UMTS. IEEE J. Solid State Circuits Lynn Bos, Gerd Vandersteen, Pieter Rombouts, Arnd Geis, Alonso Morgado, Yves Rolain, Geert Van der Plas, Julien Ryckaert
2010	J	`jnl`	Substrate Noise Coupling Mechanisms in Lightly Doped CMOS Transistors. IEEE Trans. Instrum. Meas. Stephane Bronckers, Geert Van der Plas, Gerd Vandersteen, Yves Rolain
2010	—	`conf`	Verifying electrical/thermal/thermo-mechanical behavior of a 3D stack - Challenges and solutions. CICC Geert Van der Plas, Steven Thijs, Dimitri Linten, Guruprasad Katti, Paresh Limaye, Abdelkarim Mercha, Michele Stucchi, Herman Oprins, Bart Vandevelde, Nikolaos Minas, Miro Cupac, Morin Dehan, Marc Nelis, Rahul Agarwal, Wim Dehaene, Youssef Travaly, Eric Beyne, Paul Marchal
2009	J	`jnl`	A 2.2 mW 1.75 GS/s 5 Bit Folding Flash ADC in 90 nm Digital CMOS. IEEE J. Solid State Circuits Bob Verbruggen, Jan Craninckx, Maarten Kuijk, Piet Wambacq, Geert Van der Plas
2009	J	`jnl`	A 2.4 GHz Low-Power Sixth-Order RF Bandpass ΔΣ Converter in CMOS. IEEE J. Solid State Circuits Julien Ryckaert, Jonathan Borremans, Bob Verbruggen, Lynn Bos, Costantino Armiento, Jan Craninckx, Geert Van der Plas
2009	J	`jnl`	A Low-Power Reduced Kick-Back Comparator with Improved Calibration for High-Speed Flash ADCs. IEICE Trans. Electron. Guy Torfs, Zhisheng Li, Johan Bauwelinck, Xin Yin, Jan Vandewege, Geert Van der Plas
2009	J	`jnl`	A Methodology to Predict the Impact of Substrate Noise in Analog/RF Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Stephane Bronckers, Karen Scheir, Geert Van der Plas, Gerd Vandersteen, Yves Rolain
2009	—	`conf`	A multirate 3.4-to-6.8mW 85-to-66dB DR GSM/bluetooth/UMTS cascade DT ΔΣM in 90nm digital CMOS. ISSCC Lynn Bos, Gerd Vandersteen, Julien Ryckaert, Pieter Rombouts, Yves Rolain, Geert Van der Plas
2009	—	`conf`	A single bit 6.8mW 10MHz power-optimized continuous-time ΔΣ with 67dB DR in 90nm CMOS. ESSCIRC Pieter Crombez, Geert Van der Plas, Michiel Steyaert, Jan Craninckx
2009	J	`jnl`	Architectural Exploration and Design of Time-Interleaved SAR Arrays for Low-Power and High Speed A/D Converters. IEICE Trans. Electron. Sergio Saponara, Pierluigi Nuzzo, Claudio Nani, Geert Van der Plas, Luca Fanucci
2009	—	`conf`	Automated Pathfinding tool chain for 3D-stacked integrated circuits: Practical case study. 3DIC Dragomir Milojevic, Trevor E. Carlson, Kris Croes, Riko Radojcic, Diana F. Ragett, Dirk Seynhaeve, Federico Angiolini, Geert Van der Plas, Paul Marchal
2009	—	`conf`	Evaluation of energy-recovering interconnects for low-power 3D stacked ICs. 3DIC Panagiotis Asimakopoulos, Geert Van der Plas, Alexandre Yakovlev, Paul Marchal
2009	J	`jnl`	Experimental Analysis of the Coupling Mechanisms Between a 4 GHz PPA and a 5-7 GHz LC -VCO. IEEE Trans. Instrum. Meas. Stephane Bronckers, Gerd Vandersteen, Ludwig De Locht, Michael Libois, Geert Van der Plas, Yves Rolain
2008	J	`jnl`	A 150 MS/s 133 µW 7 bit ADC in 90 nm Digital CMOS. IEEE J. Solid State Circuits Geert Van der Plas, Bob Verbruggen
2008	—	`conf`	A 150MS/s 133μW 7b ADC in 90nm digital CMOS Using a Comparator-Based Asynchronous Binary-Search sub-ADC. ISSCC Geert Van der Plas, Bob Verbruggen
2008	—	`conf`	A 2.2mW 5b 1.75GS/s Folding Flash ADC in 90nm Digital CMOS. ISSCC Bob Verbruggen, Jan Craninckx, Maarten Kuijk, Piet Wambacq, Geert Van der Plas
2008	—	`conf`	Advanced Planar Bulk and Multigate CMOS Technology: Analog-Circuit Benchmarking up to mm-Wave Frequencies. ISSCC Piet Wambacq, Abdelkarim Mercha, Karen Scheir, Bob Verbruggen, Jonathan Borremans, Vincent De Heyn, Steven Thijs, Dimitri Linten, Geert Van der Plas, Bertrand Parvais, Morin Dehan, Stefaan Decoutere, Charlotte Soens, Nadine Collaert, Malgorzata Jurczak
2008	—	`conf`	An 820μW 9b 40MS/s Noise-Tolerant Dynamic-SAR ADC in 90nm Digital CMOS. ISSCC Vito Giannini, Pierluigi Nuzzo, Vincenzo Chironi, Andrea Baschirotto, Geert Van der Plas, Jan Craninckx
2008	A	`conf`	Mixed-Signal Design Space Exploration of Time-Interleaved A/D Converters for Ultra-Wide Band Applications. DATE Pierluigi Nuzzo, Claudio Nani, Sergio Saponara, Luca Fanucci, Geert Van der Plas
2008	J	`jnl`	Noise Analysis of Regenerative Comparators for Reconfigurable ADC Architectures. IEEE Trans. Circuits Syst. I Regul. Pap. Pierluigi Nuzzo, Fernando De Bernardinis, Pierangelo Terreni, Geert Van der Plas
2007	J	`jnl`	A 0.65-to-1.4 nJ/Burst 3-to-10 GHz UWB All-Digital TX in 90 nm CMOS for IEEE 802.15.4a. IEEE J. Solid State Circuits Julien Ryckaert, Geert Van der Plas, Vincent De Heyn, Claude Desset, Bart van Poucke, Jan Craninckx
2007	—	`conf`	A 0.65-to-1.4nJ/burst 3-to-10GHz UWB Digital TX in 90nm CMOS for IEEE 802.15.4a. ISSCC Julien Ryckaert, Geert Van der Plas, Vincent De Heyn, Claude Desset, Geert Vanwijnsberghe, Bart van Poucke, Jan Craninckx
2007	—	`conf`	A 65fJ/Conversion-Step 0-to-50MS/s 0-to-0.7mW 9b Charge-Sharing SAR ADC in 90nm Digital CMOS. ISSCC Jan Craninckx, Geert Van der Plas
2007	J	`jnl`	A CMOS Ultra-Wideband Receiver for Low Data-Rate Communication. IEEE J. Solid State Circuits Julien Ryckaert, Marian Verhelst, Mustafa Badaroglu, Stefano D'Amico, Vincent De Heyn, Claude Desset, Pierluigi Nuzzo, Bart van Poucke, Piet Wambacq, Andrea Baschirotto, Wim Dehaene, Geert Van der Plas
2007	—	`conf`	A fast start-up 3GHz-10GHz digitally controlled oscillator for UWB impulse radio in 90nm CMOS. ESSCIRC Vincent De Heyn, Geert Van der Plas, Julien Ryckaert, Jan Craninckx
2007	—	`conf`	A switchable low-area 2.4-and-5 GHz dual-band LNA in digital CMOS. ESSCIRC Jonathan Borremans, Piet Wambacq, Geert Van der Plas, Yves Rolain, Maarten Kuijk
2007	A	`conf`	Interactive presentation: Simulation methodology and experimental verification for the analysis of substrate noise on LC-VCO's. DATE Stephane Bronckers, Charlotte Soens, Geert Van der Plas, Gerd Vandersteen, Yves Rolain
2007	C	`conf`	Scalable Gate-Level Models for Power and Timing Analysis. ISCAS Mustafa Badaroglu, Geert Van der Plas, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
2007	J	`jnl`	Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance CoRR Charlotte Soens, Geert Van der Plas, Piet Wambacq, Stéphane Donnay
2007	J	`jnl`	The Potential of FinFETs for Analog and RF Circuit Applications. IEEE Trans. Circuits Syst. I Regul. Pap. Piet Wambacq, Bob Verbruggen, Karen Scheir, Jonathan Borremans, Morin Dehan, Dimitri Linten, Vincent De Heyn, Geert Van der Plas, Abdelkarim Mercha, Bertrand Parvais, Cedric Gustin, Vaidyanathan Subramanian, Nadine Collaert, Malgorzata Jurczak, Stefaan Decoutere
2006	—	`conf`	A 0.16pJ/Conversion-Step 2.5mW 1.25GS/s 4b ADC in a 90nm Digital CMOS Process. ISSCC Geert Van der Plas, Stefaan Decoutere, Stéphane Donnay
2006	A*	`conf`	A 10.6mW/0.8pJ power-scalable 1GS/s 4b ADC in 0.18mum CMOS with 5.8GHz ERBW. DAC Pierluigi Nuzzo, Geert Van der Plas, Fernando De Bernardinis, Liesbet Van der Perre, Bert Gyselinckx, Pierangelo Terreni
2006	—	`conf`	A 16mA UWB 3-to-5GHz 20Mpulses/s Quadrature Analog Correlation Receiver in 0.18µm CMOS. ISSCC Julien Ryckaert, Mustafa Badaroglu, Vincent De Heyn, Geert Van der Plas, Pierluigi Nuzzo, Andrea Baschirotto, Stefano D'Amico, Claude Desset, Hans Suys, Michael Libois, Bart van Poucke, Piet Wambacq, Bert Gyselinckx
2006	J	`jnl`	Analog-Digital Partitioning for Low-Power UWB Impulse Radios under CMOS Scaling. EURASIP J. Wirel. Commun. Netw. Mustafa Badaroglu, Claude Desset, Julien Ryckaert, Vincent De Heyn, Geert Van der Plas, Piet Wambacq, Bart van Poucke
2006	J	`jnl`	Clock-skew-optimization methodology for substrate-noise reduction with supply-current folding. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mustafa Badaroglu, Kris Tiri, Geert Van der Plas, Piet Wambacq, Ingrid Verbauwhede, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
2006	J	`jnl`	Evolution of substrate noise generation mechanisms with CMOS technology scaling. IEEE Trans. Circuits Syst. I Regul. Pap. Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo J. De Man
2006	J	`jnl`	Modeling of Substrate Noise Generation, Isolation, and Impact for an LC-VCO and a Digital Modem on a Lightly-Doped Substrate. IEEE J. Solid State Circuits Charlotte Soens, Geert Van der Plas, Mustafa Badaroglu, Piet Wambacq, Stéphane Donnay, Yves Rolain, Maarten Kuijk
2006	J	`jnl`	SWAN: high-level simulation methodology for digital substrate noise generation. IEEE Trans. Very Large Scale Integr. Syst. Mustafa Badaroglu, Geert Van der Plas, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
2005	J	`jnl`	Digital ground bounce reduction by supply current shaping and clock frequency Modulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
2005	J	`jnl`	Performance degradation of LC-tank VCOs by impact of digital switching noise in lightly doped substrates. IEEE J. Solid State Circuits Charlotte Soens, Geert Van der Plas, Piet Wambacq, Stéphane Donnay, Maarten Kuijk
2005	A	`conf`	Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance. DATE Charlotte Soens, Geert Van der Plas, Piet Wambacq, Stéphane Donnay
2005	—	`conf`	Substrate noise immune design of an LC-tank VCO using sensitivity functions. CICC Charlotte Soens, Geert Van der Plas, Piet Wambacq, Stéphane Donnay
2005	J	`jnl`	Ultra-wide-band transmitter for low-power wireless body area networks: design and evaluation. IEEE Trans. Circuits Syst. I Regul. Pap. Julien Ryckaert, Claude Desset, Andrew Fort, Mustafa Badaroglu, Vincent De Heyn, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Bart van Poucke, Bert Gyselinckx
2004	—	`conf`	A 14-bit 130-MHz CMOS current-steering DAC with adjustable INL. ESSCIRC Tao Chen, Peter Geens, Geert Van der Plas, Wim Dehaene, Georges G. E. Gielen
2004	J	`jnl`	A gradient-error and edge-effect tolerant switching scheme for a high-accuracy DAC. IEEE Trans. Circuits Syst. I Regul. Pap. Jurgen Deveugele, Geert Van der Plas, Michiel Steyaert, Georges G. E. Gielen, Willy M. C. Sansen
2004	A	`conf`	Digital Ground Bounce Reduction by Phase Modulation of the Clock. DATE Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
2004	J	`jnl`	Digital circuit capacitance and switching analysis for ground bounce in ICs with a high-ohmic substrate. IEEE J. Solid State Circuits Mustafa Badaroglu, Geert Van der Plas, Piet Wambacq, Lakshmanan Balasubramanian, Kris Tiri, Ingrid Verbauwhede, Stéphane Donnay, Georges G. E. Gielen, Hugo J. De Man
2004	A*	`conf`	High-level simulation of substrate noise in high-ohmic substrates with interconnect and supply effects. DAC Geert Van der Plas, Mustafa Badaroglu, Gerd Vandersteen, Petr Dobrovolný, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
2004	—	`conf`	Impact of technology scaling on substrate noise generation mechanisms [mixed signal ICs]. CICC Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
2004	—	`conf`	Performance degradation of an LC-tank VCO by impact of digital switching noise. ESSCIRC Charlotte Soens, Geert Van der Plas, Piet Wambacq, Stéphane Donnay
2003	—	`conf`	Digital circuit capacitance and switching analysis for ground bounce in ICs with a high-ohmic substrate. ESSCIRC Mustafa Badaroglu, Lakshmanan Balasubramanian, Kris Tiri, Vincent Gravot, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
2002	J	`jnl`	A layout synthesis methodology for array-type analog blocks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Geert Van der Plas, Jan Vandenbussche, Georges G. E. Gielen, Willy M. C. Sansen
2002	J	`jnl`	CYCLONE: automated design and layout of RF LC-oscillators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Carl De Ranter, Geert Van der Plas, Michiel Steyaert, Georges G. E. Gielen, Willy M. C. Sansen
2001	A	`conf`	A Layout-Aware Synthesis Methodology for RF Circuits. ICCAD Peter J. Vancorenland, Geert Van der Plas, Michiel Steyaert, Georges G. E. Gielen, Willy M. C. Sansen
2001	J	`jnl`	AMGIE-A synthesis environment for CMOS analog integrated circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Geert Van der Plas, Geert Debyser, Francky Leyn, Koen Lampaert, Jan Vandenbussche, Georges G. E. Gielen, Willy M. C. Sansen, Petar Veselinovic, Domine Leenaerts
2000	A*	`conf`	CYCLONE: automated design and layout of RF LC-oscillators. DAC Carl De Ranter, Bram De Muer, Geert Van der Plas, Peter J. Vancorenland, Michiel Steyaert, Georges G. E. Gielen, Willy M. C. Sansen
2000	A*	`conf`	Systematic design of a 14-bit 150-MS/s CMOS current-steering D/A converter. DAC Geert Van der Plas, Jan Vandenbussche, Walter Daems, Antal van den Bosch, Georges G. E. Gielen, Willy M. C. Sansen
1999	J	`jnl`	A 14-bit intrinsic accuracy Q IEEE J. Solid State Circuits Geert Van der Plas, Jan Vandenbussche, Willy Sansen, Michel S. J. Steyaert, Georges G. E. Gielen
1999	—	`conf`	Statistical behavioral modeling for A/D-converters. ICECS Geert Van der Plas, Jan Vandenbussche, Wim Verhaegen, Georges G. E. Gielen, Willy Sansen
1998	—	`conf`	A 12 bit 200 MHz low glitch CMOS D/A converter. CICC Anne Van den Bosch, Marc Borremans, Jan Vandenbussche, Geert Van der Plas, Augusto Manuel Marques, José Bastos, Michiel Steyaert, Georges G. E. Gielen, Willy Sansen
1998	—	`conf`	Behavioral model for D/A converters as VSI virtual components. CICC Jan Vandenbussche, Geert Van der Plas, Georges G. E. Gielen, Michiel Steyaert, Willy Sansen
1998	—	`conf`	Mondriaan: a tool for automated layout synthesis of array-type analog blocks. CICC Geert Van der Plas, Jan Vandenbussche, Georges G. E. Gielen, Willy Sansen
1997	Misc	`conf`	Automated test pattern generation for analog integrated circuits. VTS Wim Verhaegen, Geert Van der Plas, Georges G. E. Gielen
1996	—	`conf`	ADMIRE: advanced mixed signal design environment. ICECS Philippe Reynaert, Ludwig G. A. Callewaert, Georges G. E. Gielen, Geert Debyser, Koen Lampaert, Francky Leyn, Geert Van der Plas, Willy Sansen, Birger Schneider, René Bloch, Dave Orton, Steve Boardman, Jeremy Stent, Jean-François Agaësse, Jörg-Olliver Fischer-Binder, Jukka Riihiaho, Kari Tukkiniemi
1995	J	`jnl`	An analogue module generator for mixed analogue/digital asic design. Int. J. Circuit Theory Appl. Georges G. E. Gielen, Geert Debyser, Koen Lampaert, Francky Leyn, Koen Swings, Geert Van der Plas, Willy Sansen, Domine Leenaerts, Petar Veselinovic, W. van Bokhoven
1994	J	`jnl`	A CMOS 18 THzΩ 248 Mb/s transimpedance amplifier and 155 Mb/s LED-driver for low cost optical fiber links. IEEE J. Solid State Circuits Mark Ingels, Geert Van der Plas, Jan Crols, Michiel Steyaert