Geert Hellings

48 papers A* 1A 1Journal 9Unranked 37

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	A 1.8-V GPIO With Design-Technology-Reliability Co-Optimization in Sub-3-nm GAA-NS Technology. IEEE J. Solid State Circuits Wen-Chieh Chen, Shih-Hung Chen, Man-Ching Huang, Shu-Wei Chang, Geert Hellings, Guido Groeseneken
2025	—	`conf`	Design Technology Co-Optimization of 3D SRAM Macro in Nanosheet Technology for High-Bandwidth Applications. IMW Anurag Swarnkar, Dawit Burusie Abdi, Bhawana Kumari, Priya Venugopal, Nicolas Pantano, Geert Hellings, Jaydeep P. Kulkarni, Dwaipayan Biswas, Julien Ryckaert, Fernando García-Redondo
2025	A	`conf`	Half-Height Double-Row CFET Standard Cells for Area Optimized Placement in A7 CMOS Node. ICCAD Halil Kükner, Ji-Yung Lin, Sheng Yang, Lynn Verschueren, Jürgen Bömmels, Anita Farokhnejad, Maarten Van De Put, Odysseas Zografos, Naoto Horiguchi, Geert Hellings, Marie Garcia Bardon, Julien Ryckaert
2025	J	`jnl`	SOT-MRAM Bitcell Scaling with BEOL Read Selectors: A DTCO Study. CoRR Yang Xiang, Fernando García-Redondo, Arvind Sharma, Van Dai Nguyen, Andrea Fantini, Philippe Matagne, Siddharth Rao, Subhali Subhechha, Lynn Verschueren, Mohammed Aftab Baig, Marie Garcia Bardon, Geert Hellings
2024	—	`conf`	Backside Power Delivery in High Density and High Performance Context: IR-Drop and Block-Level Power-Performance-Area Benefits. VLSI Technology and Circuits Yun Zhou, S. C. Song, Halil Kükner, Giuliano Sisto, Sheng Yang, Anita Farokhnejad, Mohamed Naeim, Moritz Brunion, Ji-Yung Lin, Odysseas Zografos, Pieter Weckx, Shashank Ekbote, Nick Stevens-Yu, David Greenlaw, Steve Molloy, Geert Hellings, Julien Ryckaert
2024	J	`jnl`	Future Design Direction for SRAM Data Array: Hierarchical Subarray With Active Interconnect. IEEE Trans. Circuits Syst. I Regul. Pap. Hsiao-Hsuan Liu, Carlo Gilardi, Shairfe Muhammad Salahuddin, Zhenlin Pei, Pieter Schuddinck, Yang Xiang, Pieter Weckx, Geert Hellings, Marie Garcia Bardon, Julien Ryckaert, Chenyun Pan, Subhasish Mitra, Francky Catthoor
2024	A*	`conf`	GNN-assisted Back-side Clock Routing Methodology for Advance Technologies. DAC Nesara Eranna Bethur, Pruek Vanna-Iampikul, Odysseas Zografos, Lingjun Zhu, Giuliano Sisto, Dragomir Milojevic, Alberto García Ortiz, Geert Hellings, Julien Ryckaert, Francky Catthoor, Sung Kyu Lim
2024	—	`conf`	Thermal Considerations for Block-Level PPA Assessment in Angstrom Era: A Comparison Study of Nanosheet FETs (A10) & Complementary FETs (A5). VLSI Technology and Circuits S. Mishra, Bjorn Vermeersch, Sankatali Venkateswarlu, Halil Kukner, Gioele Mirabelli, Fabian M. Bufler, Moritz Brunion, Dawit Burusie Abdi, Herman Oprins, Dwaipayan Biswas, Odysseas Zografos, Francky Catthoor, Pieter Weckx, Geert Hellings, James Myers, Julien Ryckaert
2024	—	`conf`	Thermal Performance Evaluation of Multi-Core SOCs Using Power-Thermal Co-Simulation. IRPS Subrat Mishra, Bjorn Vermeersch, Sankatali Venkateswarlu, Halil Kukner, A. Sharma, G. Mirabeli, Fabian M. Bufler, Moritz Brunion, Dawit Burusie Abdi, Herman Oprins, Dwaipayan Biswas, Odysseas Zografos, Francky Catthoor, Pieter Weckx, Geert Hellings, James Myers, Julien Ryckaert
2023	J	`jnl`	3D SRAM Macro Design in 3D Nanofabric Process Technology. IEEE Trans. Circuits Syst. I Regul. Pap. Dawit Burusie Abdi, Shairfe Muhammad Salahuddin, Jürgen Bömmels, Edouard Giacomin, Pieter Weckx, Julien Ryckaert, Geert Hellings, Francky Catthoor
2023	—	`conf`	Block-level Evaluation and Optimization of Backside PDN for High-Performance Computing at the A14 node. VLSI Technology and Circuits Giuliano Sisto, R. Preston, Rongmei Chen, Gioele Mirabelli, Anita Farokhnejad, Yun Zhou, Ivan Ciofi, Anne Jourdain, A. Veloso, Michele Stucchi, Odysseas Zografos, Pieter Weckx, Geert Hellings, Julien Ryckaert
2023	—	`conf`	Investigating Nanowire, Nanosheet and Forksheet FET Hot-Carrier Reliability via TCAD Simulations: Invited Paper. IRPS Michiel Vandemaele, Ben Kaczer, Erik Bury, Jacopo Franco, Adrian Chasin, Alexander Makarov, Hans Mertens, Geert Hellings, Guido Groeseneken
2023	—	`conf`	PPA and Scaling Potential of Backside Power Options in N2 and A14 Nanosheet Technology. VLSI Technology and Circuits S. Yang, Pieter Schuddinck, Marie Garcia Bardon, Yang Xiang, Anabela Veloso, B. T. Chan, Gioele Mirabelli, Gaspard Hiblot, Geert Hellings, Julien Ryckaert
2023	—	`conf`	Towards Chip-Package-System Co-optimization of Thermally-limited System-On-Chips (SOCs). IRPS Subrat Mishra, Sankatali Venkateswarlu, Bjorn Vermeersch, Moritz Brunion, Melina Lofrano, Dawit Burusie Abdi, Herman Oprins, Dwaipayan Biswas, Odysseas Zografos, Gaspard Hiblot, Geert Van der Plas, Pieter Weckx, Geert Hellings, James Myers, Francky Catthoor, Julien Ryckaert
2023	—	`conf`	Upcoming Challenges of ESD Reliability in DTCO with BS-PDN Routing via BPRs. VLSI Technology and Circuits Wen-Chieh Chen, S.-H. Chen, Anabela Veloso, Kateryna Serbulova, Geert Hellings, Guido Groeseneken
2022	—	`conf`	Backside PDN and 2.5D MIMCAP to Double Boost 2D and 3D ICs IR-Drop beyond 2nm Node. VLSI Technology and Circuits Rongmei Chen, Giuliano Sisto, Michele Stucchi, Anne Jourdain, Kenichi Miyaguchi, Pieter Schuddinck, P. Woeltgens, H. Lin, Naveen Kakarla, Anabela Veloso, Dragomir Milojevic, Odysseas Zografos, Pieter Weckx, Geert Hellings, Geert Van der Plas, Julien Ryckaert, Eric Beyne
2022	—	`conf`	Co-integration Process Compatible Input/Output (I/O) Device Options for GAA Nanosheet Technology. ESSDERC Gautam Gaddemane, Krishna K. Bhuwalka, Philippe Matagne, Gerhard Rzepa, Maarten L. Van De Put, Sybren Santermans, Oskar Baumgartner, Hao Wu, Geert Hellings
2022	—	`conf`	Enabling Active Backside Technology for ESD and LU Reliability in DTCO/STCO. VLSI Technology and Circuits Kateryna Serbulova, S.-H. Chen, Geert Hellings, Anabela Veloso, Anne Jourdain, Dimitri Linten, Jo De Boeck, Guido Groeseneken, Julien Ryckaert, Geert Van der Plas, Eric Beyne, Eugenio Dentoni Litta, Naoto Horiguchi
2022	J	`jnl`	Evaluation of Nanosheet and Forksheet Width Modulation for Digital IC Design in the Sub-3-nm Era. IEEE Trans. Very Large Scale Integr. Syst. Giuliano Sisto, Odysseas Zografos, Bilal Chehab, Naveen Kakarla, Yang Xiang, Dragomir Milojevic, Pieter Weckx, Geert Hellings, Julien Ryckaert
2022	—	`conf`	On Superior Hot Carrier Robustness of Dynamically-Doped Field-Effect-Transistors. IRPS Stanislav Tyaginov, Aryan Afzalian, Alexander Makarov, Alexander Grill, Michiel Vandemaele, Maksim Cherenev, Mikhail I. Vexler, Geert Hellings, Ben Kaczer
2022	—	`conf`	PPAC of sheet-based CFET configurations for 4 track design with 16nm metal pitch. VLSI Technology and Circuits Pieter Schuddinck, Fabian M. Bufler, Yang Xiang, Anita Farokhnejad, Gioele Mirabelli, Anne Vandooren, Bilal Chehab, A. Gupta, César Roda Neve, Geert Hellings, Julien Ryckaert
2022	—	`conf`	Self-Heating in iN8-iN2 CMOS Logic Cells: Thermal Impact of Architecture (FinFET, Nanosheet, Forksheet and CFET) and Scaling Boosters. VLSI Technology and Circuits Bjorn Vermeersch, Erik Bury, Yang Xiang, Pieter Schuddinck, Krishna K. Bhuwalka, Geert Hellings, Julien Ryckaert
2022	—	`conf`	Simulation Comparison of Hot-Carrier Degradation in Nanowire, Nanosheet and Forksheet FETs. IRPS Michiel Vandemaele, Ben Kaczer, Stanislav Tyaginov, Erik Bury, Adrian Vaisman Chasin, Jacopo Franco, Alexander Makarov, Hans Mertens, Geert Hellings, Guido Groeseneken
2021	—	`conf`	Performance Trade-Off Scenarios for GAA Nanosheet FETs Considering Inner-spacers and Epi-induced Stress: Understanding & Mitigating Process Risks. ESSCIRC Amita Rawat, Krishna K. Bhuwalka, Philippe Matagne, Bjorn Vermeersch, Hao Wu, Geert Hellings, Julien Ryckaert, Changze Liu
2021	—	`conf`	Performance Trade-Off Scenarios for GAA Nanosheet FETs Considering Inner-spacers and Epi-induced Stress: Understanding & Mitigating Process Risks. ESSDERC Amita Rawat, Krishna K. Bhuwalka, Philippe Matagne, Bjorn Vermeersch, Hao Wu, Geert Hellings, Julien Ryckaert, Changze Liu
2021	—	`conf`	Reliability and Variability-Aware DTCO Flow: Demonstration of Projections to N3 FinFET and Nanosheet Technologies. IRPS Gerhard Rzepa, Markus Karner, Oskar Baumgartner, Georg Strof, Franz Schanovsky, Ferdinand Mitterbauer, Christian Kernstock, Hui-Wen Karner, Pieter Weckx, Geert Hellings, Dieter Claes, Zhicheng Wu, Yang Xiang, Thomas Chiarella, Bertrand Parvais, Jérôme Mitard, Jacopo Franco, Ben Kaczer, Dimitri Linten, Zlatan Stanojevic
2020	—	`conf`	A Compact Physics Analytical Model for Hot-Carrier Degradation. IRPS Stanislav Tyaginov, Alexander Grill, Michiel Vandemaele, Tibor Grasser, Geert Hellings, Alexander Makarov, Markus Jech, Dimitri Linten, Ben Kaczer
2019	—	`conf`	CDM-Time Domain Turn-on Transient of ESD Diodes in Bulk FinFET and GAA NW Technologies. IRPS Shih-Hung Chen, Dimitri Linten, Geert Hellings, Marko Simicic, Ben Kaczer, Thomas Chiarella, Hans Mertens, Jérôme Mitard, Anda Mocuta, N. Horiguchi
2019	—	`conf`	Comparative Analysis of the Degradation Mechanisms in Logic and I/O FinFET Devices Induced by Plasma Damage. IRPS Gaspard Hiblot, Yefan Liu, Geert Hellings, Geert Van der Plas
2019	—	`conf`	Concise Analytical Expression for Wunsch-Bell 1-D Pulsed Heating and Applications in ESD Using TLP. IRPS Geert Hellings, Philippe Roussel, Nian Wang, Roman Boschke, Shih-Hung Chen, Marko Simicic, Mirko Scholz, Soeren Stoedel, Kris Myny, Dimitri Linten, Paul Hellings, Nowab Reza M. D. Ashif
2019	—	`conf`	Modeling the Effect of Random Dopants on Hot-Carrier Degradation in FinFETs. IRPS Alexander Makarov, Ben Kaczer, Philippe Roussel, Adrian Vaisman Chasin, Alexander Grill, Michiel Vandemaele, Geert Hellings, Al-Moatasem El-Sayed, Tibor Grasser, Dimitri Linten, Stanislav Tyaginov
2019	—	`conf`	Stochastic Modeling of Hot-Carrier Degradation in nFinFETs Considering the Impact of Random Traps and Random Dopants. ESSDERC Alexander Makarov, Dimitri Linten, Stanislav Tyaginov, Ben Kaczer, Philippe Roussel, Adrian Vaisman Chasin, Michiel Vandemaele, Geert Hellings, Al-Moatasem El-Sayed, Markus Jech, Tibor Grasser
2018	J	`jnl`	Comphy - A compact-physics framework for unified modeling of BTI. Microelectron. Reliab. Gerhard Rzepa, Jacopo Franco, Barry J. O'Sullivan, A. Subirats, Marko Simicic, Geert Hellings, Pieter Weckx, Markus Jech, Theresia Knobloch, Michael Waltl, Philippe Roussel, Dimitri Linten, Ben Kaczer, Tibor Grasser
2018	—	`conf`	ESD diodes with Si/SiGe superlattice I/O finFET architecture in a vertically stacked horizontal nanowire technology. ESSDERC Marko Simicic, Geert Hellings, Shih-Hung Chen, Naoto Horiguchi, Dimitri Linten
2018	J	`jnl`	Scalability comparison between raised- and embedded-SiGe source/drain structures for Si Microelectron. Reliab. Shimpei Yamaguchi, Liesbeth Witters, Jérôme Mitard, Geert Eneman, Geert Hellings, Andriy Hikavyy, Roger Loo, Naoto Horiguchi
2018	—	`conf`	Scaling CMOS beyond Si FinFET: an analog/RF perspective. ESSDERC Bertrand Parvais, Geert Hellings, Marko Simicic, Pieter Weckx, Jérôme Mitard, Doyoung Jang, V. Deshpande, B. van Liempc, Anabela Veloso, A. Vandooren, Niamh Waldron, Piet Wambacq, Nadine Collaert, Diederik Verkest
2017	—	`conf`	ESD characterisation of a-IGZO TFTs on Si and foil substrates. ESSDERC Nian Wang, Shih-Hung Chen, Geert Hellings, Kris Myny, Soeren Steudel, Mirko Scholz, Roman Boschke, Dimitri Linten, Guido Groeseneken
2017	—	`conf`	Tunable ESD clamp for high-voltage power I/O pins of a battery charge circuit in mobile applications. ESSDERC Mirko Scholz, Geert Hellings, Shih-Hung Chen, Dimitri Linten
2016	J	`jnl`	Impact of on- and off-chip protection on the transient-induced latch-up sensitivity of CMOS IC. Microelectron. Reliab. Mirko Scholz, Shih-Hung Chen, Geert Hellings, Dimitri Linten
2015	—	`conf`	Active-lite interposer for 2.5 & 3D integration. VLSIC Geert Hellings, Mirko Scholz, Mikael Detalle, Dimitrios Velenis, Muriel de Potter de ten Broeck, C. Roda Neve, Y. Li, Stefaan Van Huylenbroeck, Shih-Hung Chen, Erik Jan Marinissen, Antonio La Manna, Geert Van der Plas, Dimitri Linten, Eric Beyne, Aaron Thean
2015	—	`conf`	ESD characterization of planar InGaAs devices. IRPS Zhigang Ji, Dimitri Linten, Roman Boschke, Geert Hellings, S. H. Chen, AliReza Alian, D. Zhou, Yves Mols, Tsvetan Ivanov, Jacopo Franco, Ben Kaczer, X. Zhang, R. Gao, Jianfu Zhang, Weidong Zhang, Nadine Collaert, Guido Groeseneken
2015	—	`conf`	ESD protection diodes in optical interposer technology. ICICDT Roman Boschke, Guido Groeseneken, Mirko Scholz, Shih-Hung Chen, Geert Hellings, Peter Verheyen, Dimitri Linten
2015	—	`conf`	Impact of fin shape variability on device performance towards 10nm node. ICICDT Kazuyuki Tomida, Keizo Hiraga, Morin Dehan, Geert Hellings, Doyoung Jang, Kenichi Miyaguchi, Thomas Chiarella, Minsoo Kim, Anda Mocuta, Naoto Horiguchi, Abdelkarim Mercha, Diederik Verkest, Aaron Thean
2015	—	`conf`	Impact of local interconnects on ESD design. ICICDT Mirko Scholz, Shih-Hung Chen, Geert Hellings, Dimitri Linten, Roman Boschke
2015	—	`conf`	Processing active devices on Si interposer and impact on cost. 3DIC Dimitrios Velenis, Mikael Detalle, Geert Hellings, Mirko Scholz, Erik Jan Marinissen, Geert Van der Plas, Antonio La Manna, Andy Miller, Dimitri Linten, Eric Beyne
2013	—	`conf`	Quasi-3D method: Time-efficient TCAD and mixed-mode simulations on finFET technologies. CICC Geert Hellings, Shih-Hung Chen, Dimitri Linten, Mirko Scholz, Guido Groeseneken
2012	—	`conf`	Superior reliability and reduced Time-Dependent variability in high-mobility SiGe channel pMOSFETs for VLSI logic applications. ICICDT Jacopo Franco, Ben Kaczer, Jérôme Mitard, Maria Toledano-Luque, Felice Crupi, Geert Eneman, Ph. J. Rousse, Tibor Grasser, M. Cho, Thomas Kauerauf, Liesbeth Witters, Geert Hellings, L.-Å. Ragnarsson, Naoto Horiguchi, Marc M. Heyns, Guido Groeseneken
2010	J	`jnl`	Impact of interface state trap density on the performance characteristics of different III-V MOSFET architectures. Microelectron. Reliab. Brahim Benbakhti, J. S. Ayubi-Moak, Karol Kalna, D. Lin, Geert Hellings, Guy Brammertz, Kristin De Meyer, Iain Thayne, Asen Asenov