Gauthaman Murali

24 papers A* 1A 6C 1Journal 10Unranked 5
YearRankTypeTitle / Venue / Authors
2025 J jnl
3DNN-Xplorer: A Machine Learning Framework for Design Space Exploration of Heterogeneous 3-D DNN Accelerators.
IEEE Trans. Very Large Scale Integr. Syst.
Gauthaman Murali, Min Gyu Park, Sung Kyu Lim
2025 — conf
A 68 TOPS/W, 256MB SRAM Sparse GEMM Accelerator Tiled Across 16, 4nm Near Memory Compute (NMC) Chiplets Disaggregated 2.5D System.
CICC
Srivatsa Rangachar Srinivasa, Prerna Budhkar, Gauthaman Murali, Vui Seng Chua, Paolo A. Aseron, Vinayak Honkote, Ravi R. Iyer, Nilesh Jain, Dileep John Kurian, Anuradha Srinivasan, Tanay Karnik
2025 — conf
A High-Performance Passive Base System for Distributed AI/Media Acceleration.
CICC
Ragh Kuttappa, Jainaveen Sundaram, Srivatsa Rangachar Srinivasa, Paolo A. Aseron, Gauthaman Murali, Vinayak Honkote, Prerna Budhkar, Dileep Kurian, Ronald Kalim, Thomas P. Thomas, Anuradha Srinivasan, Tanay Karnik
2025 A conf
Invited Paper: System and Technology Co-Optimization Framework for a Disaggregated System with Passive Die 2.5D Integration.
ICCAD
Gauthaman Murali, Mudit Bhargava, Shairfe Salahuddin, Zhichao Chen, Archana Pandey, Srivatsa Rangachar Srinivasa, Prerna Budhkar, Ragh Kuttappa, Vinayak Honkote, Prashanth Sakthi, Myung-Hee Na, Tanay Karnik
2025 — conf
System-Level Validation Across Multiple Platforms to build a Robust 2.5D Multi Foundry Chiplet Solution.
ACM Great Lakes Symposium on VLSI
Srivatsa Rangachar Srinivasa, Dileep Kurian, Paolo A. Aseron, Prerna Budhkar, Vinayak Honkote, Dan Lake, Jaykant Timbadiya, Satish Yada, Suresh Kadavakollu, James Greensky, Gauthaman Murali, Anuradha Srinivasan, Ragh Kuttappa, Tanay Karnik
2024 — —
Design Methodology And Electronic Design Automation Techniques For Heterogeneous 3D Machine Learning Accelerators.
Gauthaman Murali
2024 A conf
Hetero-3D: Maximizing Performance and Power Delivery Benefits of Heterogeneous 3D ICs.
ISLPED
Lingjun Zhu, Jiawei Hu, Gauthaman Murali, Sung Kyu Lim
2023 A conf
3DNN-Xplorer: A Machine Learning Framework for Design Space Exploration of Heterogeneous 3D DNN Accelerators.
ICCAD
Gauthaman Murali, Aditya Iyer, Navneeth Ravichandran, Sung Kyu Lim
2023 J jnl
A PPA Study of Reinforced Placement Parameter Autotuning: Pseudo-3D vs. True-3D Placers.
ACM Trans. Design Autom. Electr. Syst.
Gauthaman Murali, Anthony Agnesina, Sung Kyu Lim
2023 J jnl
On Continuing DNN Accelerator Architecture Scaling Using Tightly Coupled Compute-on-Memory 3-D ICs.
IEEE Trans. Very Large Scale Integr. Syst.
Gauthaman Murali, Aditya Iyer, Lingjun Zhu, Jianming Tong, Francisco Muñoz-Martínez, Srivatsa Rangachar Srinivasa, Tanay Karnik, Tushar Krishna, Sung Kyu Lim
2022 J jnl
A Machine Learning-Powered Tier Partitioning Methodology for Monolithic 3-D ICs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yi-Chen Lu, Sai Pentapati, Lingjun Zhu, Gauthaman Murali, Kambiz Samadi, Sung Kyu Lim
2022 — conf
ART-3D: Analytical 3D Placement with Reinforced Parameter Tuning for Monolithic 3D ICs.
ISPD
Gauthaman Murali, Sandra Maria Shaji, Anthony Agnesina, Guojie Luo, Sung Kyu Lim
2022 J jnl
Design Automation and Test Solutions for Monolithic 3D ICs.
ACM J. Emerg. Technol. Comput. Syst.
Lingjun Zhu, Arjun Chaudhuri, Sanmitra Banerjee, Gauthaman Murali, Pruek Vanna-Iampikul, Krishnendu Chakrabarty, Sung Kyu Lim
2021 J jnl
Clock Delivery Network Design and Analysis for Interposer-Based 2.5-D Heterogeneous Systems.
IEEE Trans. Very Large Scale Integr. Syst.
Gauthaman Murali, Heechun Park, Eric Qin, Hakki Mert Torun, Majid Ahadi Dolatsara, Madhavan Swaminathan, Tushar Krishna, Sung Kyu Lim
2021 A conf
Heterogeneous 3D ICs: Current Status and Future Directions for Physical Design Technologies.
DATE
Gauthaman Murali, Sung Kyu Lim
2021 J jnl
Heterogeneous Mixed-Signal Monolithic 3-D In-Memory Computing Using Resistive RAM.
IEEE Trans. Very Large Scale Integr. Syst.
Gauthaman Murali, Xiaoyu Sun, Shimeng Yu, Sung Kyu Lim
2021 A conf
ParaMitE: Mitigating Parasitic CNFETs in the Presence of Unetched CNTs.
ICCAD
Sanmitra Banerjee, Arjun Chaudhuri, Jinwoo Kim, Gauthaman Murali, Mark Nelson, Sung Kyu Lim, Krishnendu Chakrabarty
2020 J jnl
Advances in Design and Test of Monolithic 3-D ICs.
IEEE Des. Test
Arjun Chaudhuri, Sanmitra Banerjee, Heechun Park, Jinwoo Kim, Gauthaman Murali, Edward Lee, Daehyun Kim, Sung Kyu Lim, Saibal Mukhopadhyay, Krishnendu Chakrabarty
2020 J jnl
Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse.
IEEE Trans. Very Large Scale Integr. Syst.
Jinwoo Kim, Gauthaman Murali, Heechun Park, Eric Qin, Hyoukjun Kwon, Venkata Chaitanya Krishna Chekuri, Nael Mizanur Rahman, Nihar Dasari, Arvind Singh, Minah Lee, Hakki Mert Torun, Kallol Roy, Madhavan Swaminathan, Saibal Mukhopadhyay, Tushar Krishna, Sung Kyu Lim
2020 J jnl
Breaking Barriers: Maximizing Array Utilization for Compute In-Memory Fabrics.
CoRR
Brian Crafton, Samuel Spetalnick, Gauthaman Murali, Tushar Krishna, Sung Kyu Lim, Arijit Raychowdhury
2020 C conf
Breaking Barriers: Maximizing Array Utilization for Compute in-Memory Fabrics.
VLSI-SOC
Brian Crafton, Samuel Spetalnick, Gauthaman Murali, Tushar Krishna, Sung Kyu Lim, Arijit Raychowdhury
2020 A conf
RTL-to-GDS Design Tools for Monolithic 3D ICs.
ICCAD
Jinwoo Kim, Gauthaman Murali, Pruek Vanna-Iampikul, Edward Lee, Daehyun Kim, Arjun Chaudhuri, Sanmitra Banerjee, Krishnendu Chakrabarty, Saibal Mukhopadhyay, Sung Kyu Lim
2020 — conf
Statistical Array Allocation and Partitioning for Compute In-Memory Fabrics.
VLSI-SoC (Selected Papers)
Brian Crafton, Samuel Spetalnick, Gauthaman Murali, Tushar Krishna, Sung Kyu Lim, Arijit Raychowdhury
2019 A* conf
Architecture, Chip, and Package Co-design Flow for 2.5D IC Design Enabling Heterogeneous IP Reuse.
DAC
Jinwoo Kim, Gauthaman Murali, Heechun Park, Eric Qin, Hyoukjun Kwon, Venkata Chaitanya Krishna Chekuri, Nihar Dasari, Arvind Singh, Minah Lee, Hakki Mert Torun, Kallol Roy, Madhavan Swaminathan, Saibal Mukhopadhyay, Tushar Krishna, Sung Kyu Lim