Gary S. Tyson - RankMe

76 papers A* 18A 7B 11C 5Misc 4Journal 20Unranked 11

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	Sally A. McKee. IEEE Micro Gary S. Tyson
2023	—	`conf`	Data Assimilation with Ocean Models: A Case Study of Reduced Precision and Machine Learning in the Gulf of Mexico. Euro-Par Workshops Daniel Voss, Gary S. Tyson, Olmo Zavala-Romero, Alexandra Bozec, Ashwanth Srinivasan
2020	A	`conf`	Experience of Administering Our First S-STEM Program to Broaden Participation in Computer Science. SIGCSE An-I Andy Wang, David B. Whalley, Zhenghao Zhang, Gary S. Tyson
2019	B	`conf`	Amniote: A User Space Interface to the Android Runtime. ENASE Zachary Yannes, Gary S. Tyson
2016	B	`conf`	Agave: A benchmark suite for exploring the complexities of the Android software stack. ISPASS Martin K. Brown, Zachary Yannes, Michael Lustig, Mazdak Sanati, Sally A. McKee, Gary S. Tyson, Steven K. Reinhardt
2016	C	`conf`	Interactive Augmented Reality for Dance. ICCC Taylor Brockhoeft, Jennifer Petuch, James Bach, Emil Djerekarov, Margareta Ackerman, Gary S. Tyson
2015	Misc	`conf`	Scheduling instruction effects for a statically pipelined processor. CASES B. Davis, Ryan Baird, Peter Gavin, Magnus Själander, Ian Finlayson, F. Rasapour, G. Cook, Gang-Ryung Uh, David B. Whalley, Gary S. Tyson
2015	C	`conf`	Serious 3D gaming research for the vision impaired. HealthCom Justin B. Marshall, Gary S. Tyson, Juan Llanos, Roberto Miguel Sanchez, Francisca B. Marshall
2014	A	`conf`	A journey toward obtaining our first NSF S-STEM (scholarship) grant. SIGCSE An-I Andy Wang, Gary S. Tyson, David B. Whalley, Robert van Engelen, Zhenghao Zhang
2013	B	`conf`	Improving processor efficiency by statically pipelining instructions. LCTES Ian Finlayson, Brandon Davis, Peter Gavin, Gang-Ryung Uh, David B. Whalley, Magnus Själander, Gary S. Tyson
2012	J	`jnl`	An Overview of Static Pipelining. IEEE Comput. Archit. Lett. Ian Finlayson, Gang-Ryung Uh, David B. Whalley, Gary S. Tyson
2012	J	`jnl`	Program Differentiation. J. Circuits Syst. Comput. Daniel Chang, Stephen Hines, Paul E. West, Gary S. Tyson, David B. Whalley
2011	—	`conf`	ContextProvider: Context awareness for medical monitoring applications. EMBC Michael Mitchell, Christopher R. Meyers, An-I Andy Wang, Gary S. Tyson
2011	—	`conf`	Improving Low Power Processor Efficiency with Static Pipelining. Interaction between Compilers and Computer Architectures Ian Finlayson, Gang-Ryung Uh, David B. Whalley, Gary S. Tyson
2010	—	`conf`	A computational exploration of gene regulation by nucleosome position. BCB Justin A. Fincher, Gary S. Tyson, Jonathan H. Dennis
2010	—	`conf`	Effect of sequences on the shape of protein energy landscapes. BCB Yue Li, Gary S. Tyson, Jinfeng Zhang
2009	—	`conf`	Core monitors: monitoring performance in multicore processors. Conf. Computing Frontiers Paul E. West, Yuval Peress, Gary S. Tyson, Sally A. McKee
2009	J	`jnl`	Data Cache Techniques to Save Power and Deliver High Performance in Embedded Systems. Trans. High Perform. Embed. Archit. Compil. Major Bhadauria, Sally A. McKee, Karan Singh, Gary S. Tyson
2009	B	`conf`	Guaranteeing instruction fetch behavior with a lookahead instruction fetch engine (LIFE). LCTES Stephen Roderick Hines, Yuval Peress, Peter Gavin, David B. Whalley, Gary S. Tyson
2009	J	`jnl`	Practical exhaustive optimization phase order exploration and evaluation. ACM Trans. Archit. Code Optim. Prasad A. Kulkarni, David B. Whalley, Gary S. Tyson, Jack W. Davidson
2008	J	`jnl`	Archer: A Community Distributed Computing Infrastructure for Computer Architecture Research and Education CoRR Renato J. O. Figueiredo, P. Oscar Boykin, José A. B. Fortes, Tao Li, Jie-Kwon Peir, David Wolinsky, Lizy Kurian John, David R. Kaeli, David J. Lilja, Sally A. McKee, Gokhan Memik, Alain Roy, Gary S. Tyson
2008	C	`conf`	Archer: A Community Distributed Computing Infrastructure for Computer Architecture Research and Education. CollaborateCom Renato J. O. Figueiredo, P. Oscar Boykin, José A. B. Fortes, Tao Li, Jie-Kwon Peir, David Wolinsky, Lizy K. John, David R. Kaeli, David J. Lilja, Sally A. McKee, Gokhan Memik, Alain Roy, Gary S. Tyson
2008	A	`conf`	Enhancing the effectiveness of utilizing an instruction register file. IPDPS David B. Whalley, Gary S. Tyson
2007	B	`conf`	Addressing instruction fetch bottlenecks by using an instruction register file. LCTES Stephen Roderick Hines, Gary S. Tyson, David B. Whalley
2007	A	`conf`	Evaluating Heuristic Optimization Phase Order Search Algorithms. CGO Prasad A. Kulkarni, David B. Whalley, Gary S. Tyson
2007	Misc	`conf`	Facilitating compiler optimizations through the dynamic mapping of alternate register structures. CASES Christopher Zimmer, Stephen Roderick Hines, Prasad A. Kulkarni, Gary S. Tyson, David B. Whalley
2007	A*	`conf`	Guaranteeing Hits to Improve the Efficiency of a Small Instruction Cache. MICRO Stephen Hines, David B. Whalley, Gary S. Tyson
2007	—	`conf`	Leveraging High Performance Data Cache Techniques to Save Power in Embedded Systems. HiPEAC Major Bhadauria, Sally A. McKee, Karan Singh, Gary S. Tyson
2007	J	`jnl`	Specializing Cache Structures for High Performance and Energy Conservation in Embedded Systems. Trans. High Perform. Embed. Archit. Compil. Michael J. Geiger, Sally A. McKee, Gary S. Tyson
2006	Misc	`conf`	Adapting compilation techniques to enhance the packing of instructions into registers. CASES Stephen Hines, David B. Whalley, Gary S. Tyson
2006	A	`conf`	Exhaustive Optimization Phase Order Space Exploration. CGO Prasad A. Kulkarni, David B. Whalley, Gary S. Tyson, Jack W. Davidson
2006	J	`jnl`	High-quality ISA synthesis for low-power cache designs in embedded microprocessors. IBM J. Res. Dev. Allen C. Cheng, Gary S. Tyson
2006	B	`conf`	In search of near-optimal optimization phase orderings. LCTES Prasad A. Kulkarni, David B. Whalley, Gary S. Tyson, Jack W. Davidson
2006	B	`conf`	Reducing the cost of conditional transfers of control by using comparison specifications. LCTES William C. Kreahling, Stephen Hines, David B. Whalley, Gary S. Tyson
2005	J	`jnl`	An Energy Efficient Instruction Set Synthesis Framework for Low Power Embedded System Designs. IEEE Trans. Computers Allen C. Cheng, Gary S. Tyson
2005	—	`conf`	Beyond Basic Region Caching: Specializing Cache Structures for High Performance and Energy Conservation. HiPEAC Michael J. Geiger, Sally A. McKee, Gary S. Tyson
2005	—	`conf`	Drowsy region-based caches: minimizing both dynamic and static power dissipation. Conf. Computing Frontiers Michael J. Geiger, Sally A. McKee, Gary S. Tyson
2005	A*	`conf`	Improving Program Efficiency by Packing Instructions into Registers. ISCA Stephen Hines, Joshua Green, Gary S. Tyson, David B. Whalley
2005	B	`conf`	PowerFITS: Reduce Dynamic and Static I-Cache Power Using Application Specific Instruction Set Synthesis. ISPASS Allen C. Cheng, Gary S. Tyson, Trevor N. Mudge
2005	A*	`conf`	Reducing Instruction Fetch Cost by Packing Instructions into RegisterWindows. MICRO Stephen Hines, Gary S. Tyson, David B. Whalley
2004	J	`jnl`	A Prefetch Taxonomy. IEEE Trans. Computers Viji Srinivasan, Edward S. Davidson, Gary S. Tyson
2004	A*	`conf`	FITS: framework-based instruction-set tuning synthesis for embedded application specific processors. DAC Allen C. Cheng, Gary S. Tyson, Trevor N. Mudge
2001	C	`conf`	Allocation by Conflict: A Simple Effective Multilateral Cache Management Scheme. ICCD Edward S. Tam, Stevan A. Vlaovic, Gary S. Tyson, Edward S. Davidson
2001	A*	`conf`	Branch History Guided Instruction Prefetching. HPCA Viji Srinivasan, Edward S. Davidson, Gary S. Tyson, Mark J. Charney, Thomas R. Puzak
2001	J	`jnl`	Evaluating the Use of Register Queues in Software Pipelined Loops. IEEE Trans. Computers Gary S. Tyson, Mikhail Smelyanskiy, Edward S. Davidson
2001	J	`jnl`	Improving Bandwidth Utilization using Eager Writeback. J. Instr. Level Parallelism Hsien-Hsin S. Lee, Gary S. Tyson, Matthew K. Farrens
2001	A*	`conf`	Stack Value File: Custom Microarchitecture for the Stack. HPCA Hsien-Hsin S. Lee, Mikhail Smelyanskiy, Chris J. Newburn, Gary S. Tyson
2000	A*	`conf`	Eager writeback - a technique for improving bandwidth utilization. MICRO Hsien-Hsin S. Lee, Gary S. Tyson, Matthew K. Farrens
2000	A*	`conf`	Improving BTB performance in the presence of DLLs. MICRO Stevan A. Vlaovic, Edward S. Davidson, Gary S. Tyson
2000	B	`conf`	Instruction overhead and data locality effects in superscalar processors. ISPASS Murali Annavaram, Gary S. Tyson, Edward S. Davidson
2000	B	`conf`	Quantifying instruction-level parallelism limits on an EPIC architecture. ISPASS Hsien-Hsin S. Lee, Youfeng Wu, Gary S. Tyson
2000	Misc	`conf`	Region-based caching: an energy-delay efficient memory architecture for embedded processors. CASES Hsien-Hsin S. Lee, Gary S. Tyson
2000	—	`conf`	Register Queues: A New Hardware/Software Approach to Efficient Software Pipelining. IEEE PACT Mikhail Smelyanskiy, Gary S. Tyson, Edward S. Davidson
1999	J	`jnl`	A high level simulator integrated with the Mirv compiler. SIGARCH Comput. Archit. News Krisztián Flautner, Gary S. Tyson, Trevor N. Mudge
1999	J	`jnl`	Active Management of Data Caches by Exploiting Reuse Information. IEEE Trans. Computers Edward S. Tam, Jude A. Rivers, Vijayalakshmi Srinivasan, Gary S. Tyson, Edward S. Davidson
1999	A	`conf`	Classifying load and store instructions for memory renaming. International Conference on Supercomputing Glenn Reinman, Brad Calder, Dean M. Tullsen, Gary S. Tyson, Todd M. Austin
1999	J	`jnl`	Memory Renaming: Fast, Early and Accurate Processing of Memory Communication. Int. J. Parallel Program. Gary S. Tyson, Todd M. Austin
1999	J	`jnl`	Performance Limits of Trace Caches. J. Instr. Level Parallelism Matt Postiff, Gary S. Tyson, Trevor N. Mudge
1999	J	`jnl`	The limits of instruction level parallelism in SPEC95 applications. SIGARCH Comput. Archit. News Matthew A. Postiff, David A. Greene, Gary S. Tyson, Trevor N. Mudge
1998	A*	`conf`	Analyzing the Working Set Characteristics of Branch Execution. MICRO Sangwook P. Kim, Gary S. Tyson
1998	—	`conf`	Computer architecture instruction at the University of Michigan. WCAE@ISCA Gary S. Tyson, Steven K. Reinhardt, Trevor N. Mudge
1998	C	`conf`	Evaluating the performance of active cache management schemes. ICCD Edward S. Tam, Jude A. Rivers, Vijayalakshmi Srinivasan, Gary S. Tyson, Edward S. Davidson
1998	A	`conf`	Utilizing Reuse Information in Data Cache Management. International Conference on Supercomputing Jude A. Rivers, Edward S. Tam, Gary S. Tyson, Edward S. Davidson, Matthew K. Farrens
1998	B	`conf`	mlcache: A Flexible Multi-Lateral Cache Simulator. MASCOTS Edward S. Tam, Jude A. Rivers, Gary S. Tyson, Edward S. Davidson
1997	A*	`conf`	Improving the Accuracy and Performance of Memory Communication Through Renaming. MICRO Gary S. Tyson, Todd M. Austin
1997	J	`jnl`	Managing data caches using selective cache line replacement. Int. J. Parallel Program. Gary S. Tyson, Matthew K. Farrens, John Matthews, Andrew R. Pleszkun
1997	A*	`conf`	On High-Bandwidth Data Cache Design for Multi-Issue Processors. MICRO Jude A. Rivers, Gary S. Tyson, Edward S. Davidson, Todd M. Austin
1996	J	`jnl`	Evaluating the Effects of Predicated Execution on Branch Prediction. Int. J. Parallel Program. Gary S. Tyson, Matthew K. Farrens
1995	A*	`conf`	A modified approach to data cache management. MICRO Gary S. Tyson, Matthew K. Farrens, John Matthews, Andrew R. Pleszkun
1994	A*	`conf`	A Study of Single-Chip Processor/Cache Organizations for Large Numbers of Transistors. ISCA Matthew K. Farrens, Gary S. Tyson, Andrew R. Pleszkun
1994	J	`jnl`	Code scheduling for multiple instruction stream architectures. Int. J. Parallel Program. Gary S. Tyson, Matthew K. Farrens
1994	A*	`conf`	The effects of predicated execution on branch prediction. MICRO Gary S. Tyson
1993	A*	`conf`	Techniques for extracting instruction level parallelism on MIMD architectures. MICRO Gary S. Tyson, Matthew K. Farrens
1992	A*	`conf`	A partitioned translation lookaside buffer approach to reducing address bandwith. ISCA Matthew K. Farrens, Arvin Park, Rob Fanfelle, Pius Ng, Gary S. Tyson
1992	A*	`conf`	MISC: a Multiple Instruction Stream Computer. MICRO Gary S. Tyson, Matthew K. Farrens, Andrew R. Pleszkun
1992	A*	`conf`	Modifying VM hardware to reduce address pin requirements. MICRO Matthew K. Farrens, Arvin Park, Gary S. Tyson