Gary Lauterbach

11 papers A* 2Misc 1Journal 5Unranked 3
YearRankTypeTitle / Venue / Authors
2021 J jnl
The Path to Successful Wafer-Scale Integration: The Cerebras Story.
IEEE Micro
Gary Lauterbach
2013 A* conf
A novel system architecture for web scale applications using lightweight CPUs and virtualized I/O.
HPCA
Kshitij Sudan, Saisanthosh Balakrishnan, Sean Lie, Min Xu, Dhiraj Mallick, Gary Lauterbach, Rajeev Balasubramonian
2011 — conf
SeaMicro SM10000-64 server: Building datacenter servers using cell phone chips.
Hot Chips Symposium
Ashutosh Dhodapkar, Gary Lauterbach, Sean Lie, Dhiraj Mallick, Jim Bauman, Sundar Kanthadai, Toru Kuzuhara, Gene Shen, Min Xu, Chris Zhang
2005 — conf
Challenges in Building a Flat-Bandwidth Memory Hierarchy for a Large-Scale Computer with Proximity Communication.
Hot Interconnects
Robert J. Drost, Craig Forrest, Bruce Guenin, Ron Ho, Ashok V. Krishnamoorthy, Danny Cohen, John E. Cunningham, Bernard Tourancheau, Arthur Zingher, Alex Chow, Gary Lauterbach, Ivan E. Sutherland
2003 Misc conf
Robust Highly-Connected Direct Interconnection Network Topologies.
PDPTA
Ilya Sharapov, Gary Lauterbach, Stephen P. Crago
2000 J jnl
A third-generation SPARC V9 64-b microprocessor.
IEEE J. Solid State Circuits
Raymond A. Heald, Kathirgamar Aingaran, Chaim Amir, Michael Ang, Michael Boland, Pankaj Dixit, Gary Gouldsberry, Dale Greenley, Joel Grinberg, Jason M. Hart, Tim Horel, Wen-Jay Hsu, James M. Kaku, Chin Kim, Song Kim, Fabian Klass, Hang Kwan, Gary Lauterbach, Roger Lo, Hugh McIntyre, Anup Mehta, David Murata, Sophie Nguyen, Yet-Ping Pai, Subeer Patel, Ken Shin, Kenway Tam, Sai Vishwanthaiah, John Wu, Gin Yee, Eileen You
1999 J jnl
UltraSPARC-III: designing third-generation 64-bit performance.
IEEE Micro
Tim Horel, Gary Lauterbach
1999 J jnl
Vying for the Lead in High-Performance Processors (Interview).
Computer
Gary Lauterbach
1998 J jnl
64-KByte sum-addressed-memory cache with 1.6-ns cycle and 2.6-ns latency.
IEEE J. Solid State Circuits
Raymond A. Heald, Ken Shin, Vinita Reddy, I-Feng Kao, Masood Khan, William L. Lynch, Gary Lauterbach, Joe Petolino
1998 A* conf
Low Load Latency Through Sum-Addressed Memory (SAM).
ISCA
William L. Lynch, Gary Lauterbach, Joseph I. Chamdani
1994 — conf
Accelerating Architectural Simulation by Parallel Execution of Trace Samples.
HICSS (1)
Gary Lauterbach