Ganesh Lakshminarayana

47 papers A* 9A 10Misc 4Journal 21Unranked 3

Year	Rank	Type	Title / Venue / Authors
2006	J	`jnl`	The LOTTERYBUS on-chip communication architecture. IEEE Trans. Very Large Scale Integr. Syst. Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana
2005	J	`jnl`	Input space-adaptive optimization for embedded-software synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Weidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha
2005	J	`jnl`	Memory binding for performance optimization of control-flow intensive behavioral descriptions. IEEE Trans. Very Large Scale Integr. Syst. Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha
2004	J	`jnl`	Common-case computation: a high-level energy and performance optimization technique. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ganesh Lakshminarayana, Anand Raghunathan, Kamal S. Khouri, Niraj K. Jha, Sujit Dey
2004	J	`jnl`	Design of high-performance system-on-chips using communication architecture tuners. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana, Sujit Dey
2004	J	`jnl`	Input space adaptive design: a high-level methodology for optimizing energy and performance. IEEE Trans. Very Large Scale Integr. Syst. Weidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha
2003	J	`jnl`	Analysis of power dissipation in embedded systems using real-time operating systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Robert P. Dick, Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha
2002	J	`jnl`	High-level energy macromodeling of embedded software. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tat Kee Tan, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha
2002	J	`jnl`	High-level test compaction techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
2002	—	`conf`	Input Space Adaptive Embedded Software Synthesis. ASP-DAC/VLSI Design Weidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha
2002	—	`conf`	Optimizing public-key encryption for wireless clients. ICC Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Ganesh Lakshminarayana
2001	Misc	`conf`	Accurate Power Macro-modeling Techniques for Complex RTL Circuits. VLSI Design Nachiketh R. Potlapally, Michael S. Hsiao, Anand Raghunathan, Ganesh Lakshminarayana, Srimat T. Chakradhar
2001	A*	`conf`	High-level Software Energy Macro-modeling. DAC Tat Kee Tan, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha
2001	A*	`conf`	Input Space Adaptive Design: A High-level Methodology for Energy and Performance Optimization. DAC Weidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha
2001	A*	`conf`	LOTTERYBUS: A New High-Performance Communication Architecture for System-on-Chip Designs. DAC Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana
2001	J	`jnl`	TAO: regular expression-based register-transfer level testability analysis and optimization. IEEE Trans. Very Large Scale Integr. Syst. Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
2001	J	`jnl`	Testing of core-based systems-on-a-chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
2001	A	`conf`	Transient Power Management Through High Level Synthesis. ICCAD Vijay Raghunathan, Srivaths Ravi, Anand Raghunathan, Ganesh Lakshminarayana
2000	A	`conf`	: Reducing test application time in high-level test generation. ITC Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
2000	J	`jnl`	Behavioral Synthesis of Fault Secure Controller/Datapaths Based on Aliasing Probability Analysis. IEEE Trans. Computers Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha
2000	A*	`conf`	Communication architecture tuners: a methodology for the design of high-performance communication architectures for systems-on-chips. DAC Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana, Sujit Dey
2000	Misc	`conf`	High-Level Synthesis with Variable-Latency Components. VLSI Design Vijay Raghunathan, Srivaths Ravi, Ganesh Lakshminarayana
2000	J	`jnl`	Incorporating speculative execution into scheduling ofcontrol-flow-intensive designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha
2000	J	`jnl`	Integrating variable-latency components into high-level synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Vijay Raghunathan, Srivaths Ravi, Ganesh Lakshminarayana
2000	A*	`conf`	Power analysis of embedded operating systems. DAC Robert P. Dick, Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha
2000	J	`jnl`	TAO-BIST: A framework for testability analysis and optimization forbuilt-in self-test of RTL circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
1999	A	`conf`	A framework for testing core-based systems-on-a-chip. ICCAD Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
1999	J	`jnl`	COSYN: Hardware-software co-synthesis of heterogeneous distributed embedded systems. IEEE Trans. Very Large Scale Integr. Syst. Bharat P. Dave, Ganesh Lakshminarayana, Niraj K. Jha
1999	A*	`conf`	Common-Case Computation: A High-Level Technique for Power and Performance Optimization. DAC Ganesh Lakshminarayana, Anand Raghunathan, Kamal S. Khouri, Niraj K. Jha, Sujit Dey
1999	J	`jnl`	FACT: a framework for applying throughput and power optimizing transformations to control-flow-intensive behavioral descriptions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ganesh Lakshminarayana, Niraj K. Jha
1999	J	`jnl`	High-level synthesis of low-power control-flow intensive circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha
1999	J	`jnl`	High-level synthesis of power-optimized and area-optimized circuits from hierarchical data-flow intensive behaviors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ganesh Lakshminarayana, Niraj K. Jha
1999	A	`conf`	Memory binding for performance optimization of control-flow intensive behaviors. ICCAD Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha
1999	J	`jnl`	Power management in high-level synthesis. IEEE Trans. Very Large Scale Integr. Syst. Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha, Sujit Dey
1999	Misc	`conf`	TAO-BIST: A Framework for Testability Analysis and Optimizationb of RTL Circuits for BIST. VTS Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
1999	J	`jnl`	Wavesched: a novel scheduling technique for control-flow intensive designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ganesh Lakshminarayana, Kamal S. Khouri, Niraj K. Jha
1998	Misc	`conf`	A Power Management Methodology for High-Level Synthesis. VLSI Design Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha, Sujit Dey
1998	A	`conf`	Fast high-level power estimation for control-flow intensive design. ISLPED Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha
1998	A	`conf`	IMPACT: A High-Level Synthesis System for Low Power Control-Flow Intensive Circuits. DATE Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha
1998	A*	`conf`	Incorporating Speculative Execution into Scheduling of Control-Flow Intensive Behavioral Descriptions. DAC Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha
1998	A	`conf`	Removal of memory access bottlenecks for scheduling control-flow intensive behavioral descriptions. ICCAD Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
1998	A*	`conf`	Synthesis of Power-Optimized and Area-Optimized Circuits from Hierarchical Behavioral Descriptions. DAC Ganesh Lakshminarayana, Niraj K. Jha
1998	A	`conf`	TAO: regular expression based high-level testability analysis and optimization. ITC Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
1998	A	`conf`	Transforming control-flow intensive designs to facilitate power management. ICCAD Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha, Sujit Dey
1997	A*	`conf`	COSYN: Hardware-Software Co-Synthesis of Embedded Systems. DAC Bharat P. Dave, Ganesh Lakshminarayana, Niraj K. Jha
1997	A	`conf`	Wavesched: a novel scheduling technique for control-flow intensive behavioral descriptions. ICCAD Ganesh Lakshminarayana, Kamal S. Khouri, Niraj K. Jha
1996	—	`conf`	Behavioral Synthesis of Fault Secure Controller?Datapaths using Aliasing Probability Analysis. FTCS Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha