Ganesh Balamurugan

40 papers A 1C 1Journal 15Unranked 22
YearRankTypeTitle / Venue / Authors
2026 J jnl
A 56-Gb/s Hybrid Silicon Photonic and 5-nm CMOS 3-D-Integrated Transceiver for Optical Compute I/O.
IEEE J. Solid State Circuits
Ganesh Balamurugan, Parmanand Mishra, Subal Sahni, Ankur Aggarwal, Simon Forey, Andrew Gimlett, Prateek Goyal, Han Hao, Santosh Hariwan, Masum Hossain, Sejun Jeon, Narayan Kaniyur, David Lazovsky, Wonho Lee, Bengt Littmann, Raj Nagulapalli, Kevin Park, John Rollinson, Matteo Staffaroni, Prakash Thakur, Saurabh Vats, Preet Virk, Dehua Xiao, Hemesh Yasotharan, Raman Yazdani, Waleed Younis, Shifeng Yu, Phil Winterbottom
2024 J jnl
8-λ × 50 Gbps/λ Heterogeneously Integrated Si-Ph DWDM Transmitter.
IEEE J. Solid State Circuits
Cooper S. Levy, Zhe Xuan, Jahnavi Sharma, Duanni Huang, Ranjeet Kumar, Chaoxuan Ma, Guan-Lin Su, Songtao Liu, Jinyong Kim, Xinru Wu, Tolga Acikalin, Haisheng Rong, Ganesh Balamurugan, James E. Jaussi
2023 — conf
A 256 Gbps Heterogeneously Integrated Silicon Photonic Microring-based DWDM Receiver Suitable for In-Package Optical I/O.
VLSI Technology and Circuits
Zhe Xuan, Ganesh Balamurugan, Duanni Huang, Ranjeet Kumar, Jahnavi Sharma, Cooper Levy, Jinyong Kim, Chaoxuan Ma, Guan-Lin Su, Songtao Liu, Xinru Wu, Tolga Acikalin, Haisheng Rong, James E. Jaussi
2023 — conf
A 3D-integrated 8λ × 32 Gbps λ Silicon Photonic Microring-based DWDM Transmitter.
CICC
Cooper Levy, Zhe Xuan, Duanni Huang, Ranjeet Kumar, Jahnavi Sharma, Taehwan Kim, Chaoxuan Ma, Guan-Lin Su, Songtao Liu, Jinyong Kim, Xinru Wu, Ganesh Balamurugan, Haisheng Rong, James E. Jaussi
2023 — conf
integrated dual-polarization silicon photonic transceiver with automated polarization control.
OFC
Xinru Wu, Duanni Huang, Taehwan Kim, Ranjeet Kumar, Guan-Lin Su, Chaoxuan Ma, Songtao Liu, Ganesh Balamurugan, Haisheng Rong
2022 J jnl
A 100-Gb/s PAM-4 Optical Receiver With 2-Tap FFE and 2-Tap Direct-Feedback DFE in 28-nm CMOS.
IEEE J. Solid State Circuits
Hao Li, Chun-Ming Hsu, Jahnavi Sharma, James E. Jaussi, Ganesh Balamurugan
2022 — conf
A 106 Gb/s 2.5 Vppd Linear Microring Modulator Driver with Integrated Photocurrent Sensor in 28nm CMOS.
OFC
Hao Li, Meer Nazmus Sakib, Duanni Huang, Ranjeet Kumar, Haisheng Rong, Ganesh Balamurugan, James E. Jaussi
2022 J jnl
A 128 Gb/s, 11.2 mW Single-Ended PAM4 Linear TIA With 2.7 μA
IEEE J. Solid State Circuits
Saeid Daneshgar, Hao Li, Taehwan Kim, Ganesh Balamurugan
2022 J jnl
Silicon Photonic Microring-Based 4 × 112 Gb/s WDM Transmitter With Photocurrent-Based Thermal Control in 28-nm CMOS.
IEEE J. Solid State Circuits
Jahnavi Sharma, Zhe Xuan, Hao Li, Taehwan Kim, Ranjeet Kumar, Meer N. Sakib, Chun-Ming Hsu, Chaoxuan Ma, Haisheng Rong, Ganesh Balamurugan, James E. Jaussi
2021 — conf
11.6 A 100Gb/s-8.3dBm-Sensitivity PAM-4 Optical Receiver with Integrated TIA, FFE and Direct-Feedback DFE in 28nm CMOS.
ISSCC
Hao Li, Jahnavi Sharma, Chun-Ming Hsu, Ganesh Balamurugan, James E. Jaussi
2021 J jnl
A 3-D-Integrated Silicon Photonic Microring-Based 112-Gb/s PAM-4 Transmitter With Nonlinear Equalization and Thermal Control.
IEEE J. Solid State Circuits
Hao Li, Ganesh Balamurugan, Taehwan Kim, Meer Sakib, Ranjeet Kumar, Haisheng Rong, James E. Jaussi, Bryan Casper
2021 — conf
A 4×50 Gb/s All-Silicon Ring-based WDM Transceiver with CMOS IC.
ECOC
Hao Li, Zhe Xuan, Ranjeet Kumar, Meer Sakib, Jahnavi Sharma, Chun-Ming Hsu, Chaoxuan Ma, Haisheng Rong, Ganesh Balamurugan, James E. Jaussi
2021 — conf
Silicon Photonic Micro-Ring Modulator-based 4 x 112 Gb/s O-band WDM Transmitter with Ring Photocurrent-based Thermal Control in 28nm CMOS.
VLSI Circuits
Jahnavi Sharma, Hao Li, Zhe Xuan, Ranjeet Kumar, Chun-Ming Hsu, Meer Sakib, Peicheng Liao, Haisheng Rong, James E. Jaussi, Ganesh Balamurugan
2020 — conf
12.1 A 3D-Integrated Microring-Based 112Gb/s PAM-4 Silicon-Photonic Transmitter with Integrated Nonlinear Equalization and Thermal Control.
ISSCC
Hao Li, Ganesh Balamurugan, Meer Sakib, Ranjeet Kumar, Hasitha Jayatilleka, Haisheng Rong, James E. Jaussi, Bryan Casper
2019 — conf
56G/112G Link Foundations Standards, Link Budgets & Models.
CICC
Ganesh Balamurugan, Ajay Balankutty, Chun-Ming Hsu
2019 — conf
A 112 Gb/s PAM4 Transmitter with Silicon Photonics Microring Modulator and CMOS Driver.
OFC
Hao Li, Ganesh Balamurugan, Meer Sakib, Jie Sun, Jeffery Driscoll, Ranjeet Kumar, Hasitha Jayatilleka, Haisheng Rong, James E. Jaussi, Bryan Casper
2018 — conf
A 112 Gb/s PAM4 Linear TIA with 0.96 pJ/bit Energy Efficiency in 28 nm CMOS.
ESSCIRC
Hao Li, Ganesh Balamurugan, James E. Jaussi, Bryan Casper
2015 — conf
A 0.5-to-0.75V, 3-to-8 Gbps/lane, 385-to-790 fJ/b, bi-directional, quad-lane forwarded-clock transceiver in 22nm CMOS.
VLSIC
Rajesh Inti, Sudip Shekhar, Ganesh Balamurugan, James E. Jaussi, Clark Roberts, Tzu-Chien Hsueh, Bryan Casper
2014 — conf
26.2 A 205mW 32Gb/s 3-Tap FFE/6-tap DFE bidirectional serial link in 22nm CMOS.
ISSCC
James E. Jaussi, Ganesh Balamurugan, Sami Hyvonen, Tzu-Chien Hsueh, Tawfiq Musah, Gökçe Keskin, Sudip Shekhar, Joseph T. Kennedy, Shreyas Sen, Rajesh Inti, Mozhgan Mansuri, Michael Leddige, Bryce Horine, Clark Roberts, Randy Mooney, Bryan Casper
2014 — conf
26.4 A 25.6Gb/s differential and DDR4/GDDR5 dual-mode transmitter with digital clock calibration in 22nm CMOS.
ISSCC
Tzu-Chien Hsueh, Ganesh Balamurugan, James E. Jaussi, Sami Hyvonen, Joseph T. Kennedy, Gökçe Keskin, Tawfiq Musah, Sudip Shekhar, Rajesh Inti, Shreyas Sen, Mozhgan Mansuri, Clark Roberts, Bryan Casper
2014 J jnl
A 4-32 Gb/s Bidirectional Link With 3-Tap FFE/6-Tap DFE and Collaborative CDR in 22 nm CMOS.
IEEE J. Solid State Circuits
Tawfiq Musah, James E. Jaussi, Ganesh Balamurugan, Sami Hyvonen, Tzu-Chien Hsueh, Gokce Keskin, Sudip Shekhar, Joseph T. Kennedy, Shreyas Sen, Rajesh Inti, Mozhgan Mansuri, Michael Leddige, Bryce Horine, Clark Roberts, Randy Mooney, Bryan Casper
2013 J jnl
A Scalable 0.128-1 Tb/s, 0.8-2.6 pJ/bit, 64-Lane Parallel I/O in 32-nm CMOS.
IEEE J. Solid State Circuits
Mozhgan Mansuri, James E. Jaussi, Joseph T. Kennedy, Tzu-Chien Hsueh, Sudip Shekhar, Ganesh Balamurugan, Frank O'Mahony, Clark Roberts, Randy Mooney, Bryan Casper
2013 — conf
A scalable 0.128-to-1Tb/s 0.8-to-2.6pJ/b 64-lane parallel I/O in 32nm CMOS.
ISSCC
Mozhgan Mansuri, James E. Jaussi, Joseph T. Kennedy, Tzu-Chien Hsueh, Sudip Shekhar, Ganesh Balamurugan, Frank O'Mahony, Clark Roberts, Randy Mooney, Bryan Casper
2010 J jnl
A 47 , ˟, 10 Gb/s 1.4 mW/Gb/s Parallel Interface in 45 nm CMOS.
IEEE J. Solid State Circuits
Frank O'Mahony, James E. Jaussi, Joseph T. Kennedy, Ganesh Balamurugan, Mozhgan Mansuri, Clark Roberts, Sudip Shekhar, Randy Mooney, Bryan Casper
2010 — conf
A 47×10Gb/s 1.4mW/(Gb/s) parallel interface in 45nm CMOS.
ISSCC
Frank O'Mahony, Joseph T. Kennedy, James E. Jaussi, Ganesh Balamurugan, Mozhgan Mansuri, Clark Roberts, Sudip Shekhar, Randy Mooney, Bryan Casper
2010 — conf
A 5-to-25Gb/s 1.6-to-3.8mW/(Gb/s) reconfigurable transceiver in 45nm CMOS.
ISSCC
Ganesh Balamurugan, Frank O'Mahony, Mozhgan Mansuri, James E. Jaussi, Joseph T. Kennedy, Bryan Casper
2009 J jnl
Strong Injection Locking in Low- Q LC Oscillators: Modeling and Application in a Forwarded-Clock I/O Receiver.
IEEE Trans. Circuits Syst. I Regul. Pap.
Sudip Shekhar, Ganesh Balamurugan, David J. Allstot, Mozhgan Mansuri, James E. Jaussi, Randy Mooney, Joseph T. Kennedy, Bryan Casper, Frank O'Mahony
2008 — conf
A 27Gb/s Forwarded-Clock I/O Receiver Using an Injection-Locked LC-DCO in 45nm CMOS.
ISSCC
Frank O'Mahony, Sudip Shekhar, Mozhgan Mansuri, Ganesh Balamurugan, James E. Jaussi, Joseph T. Kennedy, Bryan Casper, David J. Allstot, Randy Mooney
2008 J jnl
A Scalable 5-15 Gbps, 14-75 mW Low-Power I/O Transceiver in 65 nm CMOS.
IEEE J. Solid State Circuits
Ganesh Balamurugan, Joseph T. Kennedy, Gaurab Banerjee, James E. Jaussi, Mozhgan Mansuri, Frank O'Mahony, Bryan Casper, Randy Mooney
2008 J jnl
Joint Equalization and Coding for On-Chip Bus Communication.
IEEE Trans. Very Large Scale Integr. Syst.
Srinivasa R. Sridhara, Ganesh Balamurugan, Naresh R. Shanbhag
2008 — conf
Strong injection locking of low-Q LC oscillators.
CICC
Mozhgan Mansuri, Frank O'Mahony, Ganesh Balamurugan, James E. Jaussi, Joseph T. Kennedy, Sudip Shekhar, Randy Mooney, Bryan Casper
2007 — conf
Future Microprocessor Interfaces: Analysis, Design and Optimization.
CICC
Bryan Casper, Ganesh Balamurugan, James E. Jaussi, Joseph T. Kennedy, Mozhgan Mansuri
2005 J jnl
8-Gb/s source-synchronous I/O link with adaptive receiver equalization, offset cancellation, and clock de-skew.
IEEE J. Solid State Circuits
James E. Jaussi, Ganesh Balamurugan, David R. Johnson, Bryan Casper, Aaron Martin, Joseph T. Kennedy, Naresh R. Shanbhag, Randy Mooney
2005 — conf
Joint Equalization and Coding for On-Chip Bus Communication.
ISQED
Srinivasa R. Sridhara, Naresh R. Shanbhag, Ganesh Balamurugan
2004 — —
Noise-Tolerant Digital System Design
Ganesh Balamurugan
2003 C conf
Modeling and Mitigation of Jitter in Multi-Gbps Source-Synchronous I/O Links.
ICCD
Ganesh Balamurugan, Naresh R. Shanbhag
2002 J jnl
A 130-nm 6-GHz 256 × 32 bit leakage-tolerant register file.
IEEE J. Solid State Circuits
Ram K. Krishnamurthy, Atila Alvandpour, Ganesh Balamurugan, Naresh R. Shanbhag, Krishnamurthy Soumyanath, Shekhar Y. Borkar
2001 J jnl
The twin-transistor noise-tolerant dynamic circuit technique.
IEEE J. Solid State Circuits
Ganesh Balamurugan, Naresh R. Shanbhag
2000 — conf
A noise-tolerant dynamic circuit design technique.
CICC
Ganesh Balamurugan, Naresh R. Shanbhag
1999 A conf
Energy-efficient dynamic circuit design in the presence of crosstalk noise.
ISLPED
Ganesh Balamurugan, Naresh R. Shanbhag