Ganapathy Parthasarathy

22 papers A* 2A 6C 1Misc 2Journal 3Unranked 8

Year	Rank	Type	Title / Venue / Authors
2024	J	`jnl`	HDL-GPT: High-Quality HDL is All You Need. CoRR Bhuvnesh Kumar, Saurav Nanda, Ganapathy Parthasarathy, Pawan Patil, Austin Tsai, Parivesh Choudhary
2023	—	`conf`	Optimizing Constrained Random Verification with ML and Bayesian Estimation. MLCAD Bhuvnesh Kumar, Ganapathy Parthasarathy, Saurav Nanda, Sridhar Rajakumar
2022	C	`conf`	Optimizing ML Classification Models for Constrained EDA Resource Budgets. ICCD Ganapathy Parthasarathy, Bhuvnesh Kumar, Saurav Nanda, Parivesh Choudhary, Sridhar Rajakumar
2022	—	`conf`	RTL Regression Test Selection using Machine Learning. ASP-DAC Ganapathy Parthasarathy, Aabid Rushdi, Parivesh Choudhary, Saurav Nanda, Malan Evans, Hansika Gunasekara, Sridhar Rajakumar
2019	—	`conf`	Resource Aware Scheduling for EDA Regression Jobs. Euro-Par Workshops Saurav Nanda, Ganapathy Parthasarathy, Parivesh Choudhary, Arun Venkatachar
2017	—	`conf`	Test Knowledge Data Base. VLSI-DAT Arun Venkatachar, S. Rajakumar, M. Chapman, Sajeewan Basuru, Ganapathy Parthasarathy, C.-C. Lin, A. Hegde, T. Li
2005	A	`conf`	An Efficient Sequential SAT Solver With Improved Search Strategies. DATE Feng Lu, Madhu K. Iyer, Ganapathy Parthasarathy, Li-C. Wang, Kwang-Ting Cheng, Kuang-Chien Chen
2005	A	`conf`	Efficient Conflict-Based Learning in an RTL Circuit Constraint Solver. DATE Madhu K. Iyer, Ganapathy Parthasarathy, Kwang-Ting Cheng
2005	A	`conf`	RTL SAT simplification by Boolean and interval arithmetic reasoning. ICCAD Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Forrest Brewer
2005	A*	`conf`	Structural search for RTL with predicate learning. DAC Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Forrest Brewer
2004	A*	`conf`	An efficient finite-domain constraint solver for circuits. DAC Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Li-C. Wang
2004	—	`conf`	Efficient reachability checking using sequential SAT. ASP-DAC Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Li-C. Wang
2004	J	`jnl`	Safety Property Verification Using Sequential SAT and Bounded Model Checking. IEEE Des. Test Comput. Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Li-C. Wang
2003	—	`conf`	A comparison of BDDs, BMC, and sequential SAT for model checking. HLDVT Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Li-C. Wang
2003	A	`conf`	SATORI - A Fast Sequential SAT Engine for Circuits. ICCAD Madhu K. Iyer, Ganapathy Parthasarathy, Kwang-Ting Cheng
2002	A	`conf`	Combining ATPG and Symbolic Simulation for Efficient Validation of Embedded Array Systems. ITC Ganapathy Parthasarathy, Madhu K. Iyer, Tao Feng, Li-C. Wang, Kwang-Ting Cheng, Magdy S. Abadir
2002	J	`jnl`	Efficient circuit clustering for area and power reduction in FPGAs. ACM Trans. Design Autom. Electr. Syst. Amit Singh, Ganapathy Parthasarathy, Malgorzata Marek-Sadowska
2001	—	`conf`	An analysis of ATPG and SAT algorithms for formal verification. HLDVT Ganapathy Parthasarathy, Chung-Yang Huang, Kwang-Ting Cheng
2001	A	`conf`	Interconnect Resource-Aware Placement for Hierarchical FPGAs. ICCAD Amit Singh, Ganapathy Parthasarathy, Malgorzata Marek-Sadowska
2001	—	`conf`	Interconnect complexity-aware FPGA placement using Rent's rule. SLIP Ganapathy Parthasarathy, Malgorzata Marek-Sadowska, Arindam Mukherjee, Amit Singh
1999	Misc	`conf`	Digital Circuit Design for Minimum Transient Energy and a Linear Programming Method. VLSI Design Vishwani D. Agrawal, Michael L. Bushnell, Ganapathy Parthasarathy, Rajesh Ramadoss
1998	Misc	`conf`	Towards Simultaneous Delay-Fault Built-In Self-Test and Partial-Scan Insertion. VTS Ganapathy Parthasarathy, Michael L. Bushnell