Gain Kim

45 papers A 2C 6Journal 21Unranked 16
YearRankTypeTitle / Venue / Authors
2026 J jnl
A 112-Gb/s Discrete Multitone Wireline Receiver Datapath With Time-Interleaved Time-Based ADC in 5-nm FinFET.
IEEE J. Solid State Circuits
Jaewon Lee, Pier Andrea Francese, Matthias Braendli, Thomas Morf, Marcel A. Kossel, Seoyoung Jang, Yujin Choi, DongGeon Kim, Taekwang Jang, Gain Kim
2025 — conf
7.5 A 353mW 112Gb/s Discrete Multitone Wireline Receiver Datapath with Time-Based ADC in 5nm FinFET.
ISSCC
Jaewon Lee, Pier Andrea Francese, Matthias Brändli, Thomas Morf, Marcel A. Kossel, Seoyoung Jang, Gain Kim
2025 J jnl
A 2-Lane DAC-/ADC-Based 2 × 2 MIMO PAM-4 MMSE-DFE Wireline Transceiver With FEXT Cancellation on RFSoC Platform.
IEEE Trans. Very Large Scale Integr. Syst.
Jaewon Lee, Seoyoung Jang, Yujin Choi, DongGeon Kim, Matthias Braendli, Thomas Morf, Marcel A. Kossel, Pier Andrea Francese, Gain Kim
2025 J jnl
A Fast Design Optimization of On-Chip Equalizing Links Using Particle Swarm Optimization.
IEEE Trans. Very Large Scale Integr. Syst.
Hyoseok Song, Kwangmin Kim, Gain Kim, Byungsub Kim
2025 A conf
A Spectral-Efficient Low-Power NRZ/PAM-4 Dual-Mode Wireline Transmitter for Multidrop Interfaces.
ISLPED
DongGeon Kim, Kiarash Gharibdoust, Armin Tajalli, Kyungtae Lee, Gain Kim
2025 — conf
A Time-Domain Analysis, Modeling and Optimization of Analog Amplitude-Modulated Multi-Tone Serial Data Transceivers.
ICEIC
DongGeon Kim, Seongjin Kim, Gain Kim
2025 J jnl
An 86.71875-GHz RF Transceiver for 57.8125-Gb/s Plastic Waveguide Links With a CDR-Assisted Carrier Synchronization Technique in 28-nm CMOS.
IEEE J. Solid State Circuits
Hanho Choi, Ha-Il Song, Hyosup Won, Jun Young Yoo, Woohyun Kwon, Huxian Jin, Konan Kwon, Cheongmin Lee, Gain Kim, Jake Eu, Sean Park, Hyeon-Min Bae
2025 J jnl
An On-Chip Low-Cost Averaging Digital Sampling Scope for 80-GS/s Measurement of Wireline Pulse Responses.
IEEE Trans. Very Large Scale Integr. Syst.
Won Joon Choi, Myungguk Lee, Junung Choi, Jaeik Cho, Gain Kim, Byungsub Kim
2025 J jnl
BEE-SLAM: A 65-nm 17.96-TOPS/W Location-Sharing-Based Multi-Agent Neuromorphic SLAM Accelerator for Swarm Robotics.
IEEE J. Solid State Circuits
Jaehyun Lee, Dong-gu Choi, Gain Kim, Minyoung Song, Jong-Hyeok Yoon
2024 J jnl
A 2-Lane Discrete Multitone Wireline Receiver Datapath With Far-End Crosstalk Cancellation on RFSoC Platform.
IEEE Trans. Circuits Syst. II Express Briefs
Jaewon Lee, Seoyoung Jang, Matthias Braendli, Thomas Morf, Marcel A. Kossel, Pier Andrea Francese, Gain Kim
2024 J jnl
A 26-Gb/s Framed-Pulsewidth Modulation Transceiver for Extended Reach Optical Links.
IEEE J. Solid State Circuits
Woohyun Kwon, Hyosup Won, Taeho Kim, Sejun Jeon, Soon-Won Kwon, Ha-Il Song, Hanho Choi, Bongjin Kim, Huxian Jin, Jun-Gi Jo, Woosang Han, Tai-Young Kim, Gain Kim, Jake Eu, Jinho Park, Hyeon-Min Bae
2024 C conf
A 4×4 MIMO Discrete Multitone Wireline Transceiver With Far-End Crosstalk Cancellation For ADC-Based High-Speed Serial Links.
ISCAS
Jaewon Lee, Seoyoung Jang, Yujin Choi, DongGeon Kim, Matthias Braendli, Marcel A. Kossel, Andrea Ruffino, Thomas Morf, Pier Andrea Francese, Gain Kim
2024 — conf
A 97dB-PSRR 178.4dB-FOMDR Calibration-Free VCO-ΔΣ ADC Using a PVT-Insensitive Frequency-Locked Differential Regulation Scheme for Multi-Channel ExG Acquisition.
VLSI Technology and Circuits
Sehwan Lee, Taeryoung Seol, Geunha Kim, Minyoung Song, Gain Kim, Jong-Hyeok Yoon, Arup K. George, Junghyup Lee
2024 J jnl
A DAC/ADC-Based Wireline Transceiver Datapath Functional Verification on RFSoC Platform.
IEEE Trans. Circuits Syst. II Express Briefs
Jaewon Lee, Seoyoung Jang, Yujin Choi, DongGeon Kim, Serdar A. Yonar, Matthias Braendli, Andrea Ruffino, Thomas Morf, Marcel A. Kossel, Pier Andrea Francese, Gain Kim
2024 J jnl
A Discrete Multitone Wireline Transceiver Datapath With On-Chip Sign-Sign LMS Adaptation and Loading Profile Optimization on RFSoC.
IEEE Trans. Circuits Syst. II Express Briefs
Jaewon Lee, Seoyoung Jang, DongGeon Kim, Yujin Choi, Jong-Hyeok Yoon, Matthias Braendli, Thomas Morf, Marcel A. Kossel, Pier Andrea Francese, Gain Kim
2024 — conf
A Discrete Multitone Wireline Transceiver Using Optimal Loading Over Reflective Channel For ADC-Based High-Speed Serial Links.
ISOCC
Jaewon Lee, Seoyoung Jang, DongGeon Kim, Yujin Choi, Sungyu Song, Gain Kim
2024 — conf
A Discrete Multitone Wireline Transceiver With Clipping Ratio Optimization For ADC-Based High-Speed Serial Links.
ISOCC
Seoyoung Jang, Jaewon Lee, Yujin Choi, DongGeon Kim, Gain Kim
2024 J jnl
A Loop-Break Decision Feedback Equalizer for DAC/ADC-DSP-Based Wireline Transceivers.
IEEE Trans. Circuits Syst. I Regul. Pap.
DongGeon Kim, Yujin Choi, Jaewon Lee, Seoyoung Jang, Sungyu Song, Matthias Braendli, Thomas Morf, Marcel A. Kossel, Pier Andrea Francese, Gain Kim
2024 — conf
A Study on the Effects of Power Loading Profile in Discrete Multitone Wireline Serial-Data Transceiver with Fixed-Point DSP-SerDes Simulator.
ICEIC
Seoyoung Jang, Jaewon Lee, Gain Kim
2024 — conf
Area Optimization of the Feed-Forward Equalizer for ADC-Based High-Speed Wireline Receiver Using Channel Characteristics.
ICEIC
Yujin Choi, Seoyoung Jang, Gain Kim
2024 — conf
BEE-SLAM: A 65nm 17.96 TOPS/W 97.55%-Sparse-Activity Hybrid Mixed-Signal/Digital Multi-Agent Neuromorphic SLAM Accelerator for Swarm Robotics.
CICC
Jaehyun Lee, Dong-gu Choi, Minyoung Song, Gain Kim, Jong-Hyeok Yoon
2024 J jnl
Compact Single-Ended Transceivers Demonstrating Flexible Generation of 1/N-Rate Receiver Front-Ends for Short-Reach Links.
IEEE Trans. Circuits Syst. I Regul. Pap.
Myungguk Lee, Jaeik Cho, Junung Choi, Won Joon Choi, Jiyun Lee, Iksu Jang, Changjae Moon, Gain Kim, Byungsub Kim
2024 C conf
DMT 3L4W: A 3-Lane 4-Wire Signaling With Discrete Multitone Modulation for High-Speed Wireline Chip-to-Chip Interconnects.
ISCAS
Seoyoung Jang, Jaewon Lee, Yujin Choi, DongGeon Kim, Gain Kim
2023 — conf
A 1V-Supply $1.85\mathrm{V}_{\text{PP}}$ -Input-Range 1kHz-BW 181.9dB-FOMDR179.4dB-FOMSNDR 2
ISSCC
Geunha Kim, Sehwan Lee, Taeryoung Seol, Seungyeob Baik, YeonJae Shin, Gain Kim, Jong-Hyeok Yoon, Arup K. George, Junghyup Lee
2023 — conf
An 86.71875GHz RF transceiver for 57.8125Gb/s waveguide links with a CDR-assisted carrier synchronization loop in 28nm.
ESSCIRC
Hanho Choi, Ha-Il Song, Hyosup Won, Jun Young Yoo, Woohyun Kwon, Huxian Jin, Konan Kwon, Cheong Min Lee, Gain Kim, Jake Eu, Sean Park, Hyeon-Min Bae
2023 — conf
Does Charge Balancing Ensure the Safety of the Electrical Stimulation and Is It Power Efficientƒ.
EMBC
Reza Ranjandish, Gain Kim
2023 J jnl
Far-End Crosstalk Cancellation With MIMO OFDM for >200 Gb/s ADC-Based Serial Links.
IEEE Trans. Circuits Syst. II Express Briefs
Gain Kim
2022 — conf
Bin-Specific Quantization in Spectral-Domain Convolutional Neural Network Accelerators.
AICAS
Jinho Park, Jaewon Lee, Gain Kim, Hyeon-Min Bae
2022 J jnl
Design Space Exploration of Single-Lane OFDM-Based Serial Links for High-Speed Wireline Communications.
IEEE Open J. Circuits Syst.
Gain Kim
2021 C conf
Link Bit-Error-Rate Requirement Analysis for Deep Neural Network Accelerators.
ISCAS
Jaewon Lee, Gain Kim, Jinho Park, Hyeon-Min Bae
2020 J jnl
A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET.
IEEE J. Solid State Circuits
Gain Kim, Marcel A. Kossel, Alessandro Cevrero, Ilter Özkaya, Andreas Burg, Thomas Toifl, Yusuf Leblebici, Lukas Kull, Danny Luu, Matthias Braendli, Christian Menolfi, Pier Andrea Francese, Hazar Yueksel, Cosimo Aprile, Thomas Morf
2019 — conf
A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET.
ISSCC
Gain Kim, Lukas Kull, Danny Luu, Matthias Braendli, Christian Menolfi, Pier Andrea Francese, Hazar Yueksel, Cosimo Aprile, Thomas Morf, Marcel A. Kossel, Alessandro Cevrero, Ilter Özkaya, Andreas Burg, Thomas Toifl, Yusuf Leblebici
2019 — conf
A 4.8pJ/b 56Gb/s ADC-Based PAM-4 Wireline Receiver Data-Path with Cyclic Prefix in 14nm FinFET.
A-SSCC
Gain Kim, Lukas Kull, Danny Luu, Matthias Braendli, Christian Menolfi, Pier Andrea Francese, Hazar Yueksel, Cosimo Aprile, Thomas Morf, Marcel A. Kossel, Alessandro Cevrero, Ilter Özkaya, Hyeon-Min Bae, Andreas Burg, Thomas Toifl, Yusuf Leblebici
2019 — conf
Design Considerations and Performance Trade-Offs for 56Gb/s Discrete Multi-Tone Electrical Link.
MWSCAS
Gain Kim, Woohyun Kwon, Thomas Toifl, Yusuf Leblebici, Hyeon-Min Bae
2018 J jnl
Direct Reconstruction of Saturated Samples in Band-Limited OFDM Signals.
CoRR
Kyong Hwan Jin, Gain Kim, Yusuf Leblebici, Jong Chul Ye, Michael Unser
2018 C conf
Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver.
ISCAS
Gain Kim, Lukas Kull, Danny Luu, Matthias Braendli, Christian Menolfi, Pier Andrea Francese, Cosimo Aprile, Thomas Morf, Marcel A. Kossel, Alessandro Cevrero, Ilter Özkaya, Thomas Toifl, Yusuf Leblebici
2017 J jnl
A Time-Division Multiplexing Signaling Scheme for Inter-Symbol/Channel Interference Reduction in Low-Power Multi-Drop Memory Links.
IEEE Trans. Circuits Syst. II Express Briefs
Gain Kim, Chen Cao, Kiarash Gharibdoust, Armin Tajalli, Yusuf Leblebici
2017 J jnl
Design and Modeling of Serial Data Transceiver Architecture by Employing Multi-Tone Single-Sideband Signaling Scheme.
IEEE Trans. Circuits Syst. I Regul. Pap.
Gain Kim, Thierry Barailler, Chen Cao, Kiarash Gharibdoust, Yusuf Leblebici
2016 J jnl
A Digital Spectrum Shaping Signaling Serial-Data Transceiver With Crosstalk and ISI Reduction Property in Multidrop Interfaces.
IEEE Trans. Circuits Syst. II Express Briefs
Gain Kim, Kiarash Gharibdoust, Armin Tajalli, Yusuf Leblebici
2016 J jnl
A Study on the Programming Structures for RRAM-Based FPGA Architectures.
IEEE Trans. Circuits Syst. I Regul. Pap.
Xifan Tang, Gain Kim, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
2016 C conf
A fully-digital spectrum shaping signaling for serial-data transceiver with crosstalk and ISI reduction property in multi-drop memory interfaces.
ISCAS
Kiarash Gharibdoust, Gain Kim, Armin Tajalli, Yusuf Leblebici
2016 — conf
Architectural modeling of a multi-tone/single-sideband serial link transceiver for lossy wireline data links.
APCCAS
Gain Kim, Yusuf Leblebici
2015 J jnl
A Novel FPGA Architecture Based on Ultrafine Grain Reconfigurable Logic Cells.
IEEE Trans. Very Large Scale Integr. Syst.
Pierre-Emmanuel Gaillardon, Xifan Tang, Gain Kim, Giovanni De Micheli
2015 C conf
Design optimization of polyphase digital down converters for extremely high frequency wireless communications.
VLSI-SoC
Gain Kim, Raffaele Capoccia, Yusuf Leblebici
2015 A conf
Towards More Efficient Logic Blocks By Exploiting Biconditional Expansion (Abstract Only).
FPGA
Pierre-Emmanuel Gaillardon, Gain Kim, Xifan Tang, Luca Gaetano Amarù, Giovanni De Micheli