Gaetano Palumbo

298 papers C 41Journal 131Unranked 126
YearRankTypeTitle / Venue / Authors
2026 J jnl
Pseudo-Dynamic AOI and OAI Standard-Cell-Based Comparators.
IEEE Trans. Circuits Syst. I Regul. Pap.
Antonio Manno, Giuseppe Scotti, Gaetano Palumbo
2025 — conf
A Fully-Synthesizable And-Or-Invert-Based Pseudo-Dynamic Voltage Comparator.
ICECS
Antonio Manno, Giuseppe Scotti, Gaetano Palumbo
2025 — conf
A Novel Ultra-Low-Voltage Pseudo-Dynamic Voltage Comparator Based On OAI Standard-Cells.
PRIME
Antonio Manno, Giuseppe Scotti, Gaetano Palumbo
2025 — conf
A Triple Latched Ultra-Low-Voltage Rail-to-Rail ICMR Standard-Cell Based Comparator.
PRIME
Antonio Manno, Giuseppe Scotti, Gaetano Palumbo
2025 — conf
An Area-Efficient Design Strategy for Dickson Charge Pumps on Flexible Substrate.
ICECS
Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo
2025 — conf
Detailed Modeling of a PFM Buck-Boost Converter suitable for Low Power Applications.
PRIME
Carla Caruso, Elio Consoli, Gaetano Palumbo, Giuseppe Patti
2025 — conf
Double Differential Amplifier by means of a MOS CCII for Active Electrodes.
PRIME
Carla Caruso, Alfio Dario Grasso, Federico Nicolas Guerrero, Gaetano Palumbo
2025 C conf
The charge pump as a signal amplifier: enabling small-signal gain boosting.
ISCAS
Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo
2024 J jnl
Rail to Rail ICMR and High Performance ULV Standard-Cell-Based Comparator for Biomedical and IoT Applications.
IEEE Access
Riccardo Della Sala, Francesco Centurelli, Giuseppe Scotti, Gaetano Palumbo
2024 — conf
The Self-Oscillating Dickson Charge Pump.
DCIS
Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo
2023 — conf
An Energy-Efficient Design Strategy for Dickson Charge Pumps with Linear Distributed Capacitance.
NEWCAS
Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo
2023 C conf
Fully On-Chip Charge Pump-based Boost Converter in 65-nm CMOS for Single Solar Cell Powered IC.
ISCAS
Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo
2023 — conf
GBW Optimization in Two-Stage OTAs Operating in Weak Inversion.
DCIS
Javier Beloso-Legarra, Antonio Lopez-Martin, Carlos Aristoteles De la Cruz, Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi
2023 — conf
Triple Clock Boosted Voltage Multiplier: A Design Strategy to Heavily Reduce Rise Time.
NEWCAS
Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo
2023 J jnl
Very-Low-Voltage Charge Pump Topologies for IoT Applications.
IEEE Trans. Circuits Syst. I Regul. Pap.
Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo
2022 J jnl
A Bulk Current Regulation Technique for Dual-Branch Cross-Coupled Charge Pumps.
IEEE Trans. Circuits Syst. II Express Briefs
Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo
2022 J jnl
A Charge Loss Aware Advanced Model of Dickson Voltage Multipliers.
IEEE Access
Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo, Toru Tanzawa
2022 J jnl
A Methodology to Derive a Symbolic Transfer Function for Multistage Amplifiers.
IEEE Access
Hamed Aminzadeh, Alfio Dario Grasso, Gaetano Palumbo
2022 J jnl
A Novel Clock Gating Approach for the Design of Low-Power Linear Feedback Shift Registers.
IEEE Access
Gianluca Giustolisi, Rosario Mita, Gaetano Palumbo, Giuseppe Scotti
2022 J jnl
Analysis and Comparison in the Energy-Delay Space of Nanometer CMOS One-Bit Full-Adders.
IEEE Access
Gianluca Giustolisi, Gaetano Palumbo
2022 J jnl
Double-Differential Amplifier for sEMG Measurement by Means of a Current-Mode Approach.
IEEE Access
Federico Nicolas Guerrero, Enrique Mario Spinelli, Alfio Dario Grasso, Gaetano Palumbo
2022 J jnl
Single miller capacitor frequency compensation techniques: Theoretical comparison and critical review.
Int. J. Circuit Theory Appl.
Alfio Dario Grasso, Davide Marano, Gaetano Palumbo, Salvatore Pennisi
2022 J jnl
The Dickson Charge Pump as a Signal Amplifier.
IEEE Trans. Circuits Syst. I Regul. Pap.
Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo
2022 J jnl
Two-Stage OTA With All Subthreshold MOSFETs and Optimum GBW to DC-Current Ratio.
IEEE Trans. Circuits Syst. II Express Briefs
Javier Beloso-Legarra, Alfio Dario Grasso, Antonio J. López-Martín, Gaetano Palumbo, Salvatore Pennisi
2021 C conf
A Low-Voltage High-Performance Frequency Divider exploiting Folded MCML.
ISCAS
Francesco Centurelli, Giuseppe Scotti, Alessandro Trifiletti, Gaetano Palumbo
2021 J jnl
A Memory-Targeted Dynamic Reconfigurable Charge Pump to Achieve a Power Consumption Reduction in IoT Nodes.
IEEE Access
Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo
2021 J jnl
A Very-Low-Voltage Frequency Divider in Folded MOS Current Mode Logic With Complementary n- and p-type Flip-Flops.
IEEE Trans. Very Large Scale Integr. Syst.
Francesco Centurelli, Giuseppe Scotti, Gaetano Palumbo
2021 J jnl
Charge Pumps for Ultra-Low-Power Applications: Analysis, Design, and New Solutions.
IEEE Trans. Circuits Syst. II Express Briefs
Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo, Toru Tanzawa
2021 — conf
Comparison of the Wide-Frequency Range Dynamic Behavior of the Dickson and Cockcroft-Walton Voltage Multipliers.
MWSCAS
Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo
2021 J jnl
Design of CMOS three-stage amplifiers for near-to-minimum settling-time.
Microelectron. J.
Gianluca Giustolisi, Gaetano Palumbo
2021 J jnl
Design of Low-Voltage Power Efficient Frequency Dividers in Folded MOS Current Mode Logic.
IEEE Trans. Circuits Syst. I Regul. Pap.
Francesco Centurelli, Giuseppe Scotti, Alessandro Trifiletti, Gaetano Palumbo
2021 J jnl
Design of Three-Stage OTA Based on Settling-Time Requirements Including Large and Small Signal Behavior.
IEEE Trans. Circuits Syst. I Regul. Pap.
Gianluca Giustolisi, Gaetano Palumbo
2021 C conf
Design of Three-Stage OTAs from Settling-Time and Slew-Rate Constraints.
ISCAS
Gianluca Giustolisi, Gaetano Palumbo
2021 — conf
Dickson Charge Pump: Design Strategy for Optimum Efficiency.
NEWCAS
Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo
2020 J jnl
A High-Performance Charge Pump Topology for Very-Low-Voltage Applications.
IEEE Trans. Circuits Syst. II Express Briefs
Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo
2020 J jnl
A Multi-Folded MCML for Ultra-Low-Voltage High-Performance in Deeply Scaled CMOS.
IEEE Trans. Circuits Syst.
Gaetano Palumbo, Giuseppe Scotti
2020 J jnl
A Novel 0.5 V MCML D-Flip-Flop Topology Exploiting Forward Body Bias Threshold Lowering.
IEEE Trans. Circuits Syst. II Express Briefs
Giuseppe Scotti, Alessandro Trifiletti, Gaetano Palumbo
2020 J jnl
A Subthreshold Cross-Coupled Hybrid Charge Pump for 50-mV Cold-Start.
IEEE Access
Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo
2020 J jnl
A simple and effective design strategy to increase power conversion efficiency of linear charge pumps.
Int. J. Circuit Theory Appl.
Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo
2020 J jnl
Charge Pump Improvement for Energy Harvesting Applications by Node Pre-Charging.
IEEE Trans. Circuits Syst.
Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo
2020 J jnl
Current-mode body-biased switch to increase performance of linear charge pumps.
Int. J. Circuit Theory Appl.
Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo
2020 J jnl
Delay models and design guidelines for MCML gates with resistor or PMOS load.
Microelectron. J.
Francesco Centurelli, Giuseppe Scotti, Alessandro Trifiletti, Gaetano Palumbo
2020 J jnl
Linear distribution of capacitance in Dickson charge pumps to reduce rise time.
Int. J. Circuit Theory Appl.
Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo, Toru Tanzawa
2019 J jnl
Class-AB CMOS output stages suitable for low-voltage amplifiers in nanometer technologies.
Microelectron. J.
Gianluca Giustolisi, Gaetano Palumbo, Salvatore Pennisi
2019 J jnl
In-Depth Analysis of Pole-Zero Compensations in CMOS Operational Transconductance Amplifiers.
IEEE Trans. Circuits Syst. I Regul. Pap.
Gianluca Giustolisi, Gaetano Palumbo
2019 J jnl
Optimized Charge Pump With Clock Booster for Reduced Rise Time or Silicon Area.
IEEE Trans. Circuits Syst. II Express Briefs
Andrea Ballo, Alfio Dario Grasso, Gianluca Giustolisi, Gaetano Palumbo
2018 — conf
A Clock Boosted Charge Pump with Reduced Rise Time.
ICECS
Andrea Ballo, Gianluca Giustolisi, Alfio Dario Grasso, Gaetano Palumbo
2018 — conf
A Novel 0.6V MCML D-Latch Topology exploiting Dynamic Body Bias Threshold Lowering.
ICECS
Giuseppe Scotti, Alessandro Trifiletti, Gaetano Palumbo
2018 — conf
A Novel Very Low Voltage Topology to implement MCML XOR Gates.
PRIME
Davide Bellizia, Gaetano Palumbo, Giuseppe Scotti, Alessandro Trifiletti
2018 J jnl
Bessel-like compensation of three-stage operational transconductance amplifiers.
Int. J. Circuit Theory Appl.
Gianluca Giustolisi, Gaetano Palumbo
2018 — conf
Design of CMOS OTAs with Settling-Time Constraints.
ICECS
Gianluca Giustolisi, Gaetano Palumbo
2018 J jnl
Dual Push-Pull High-Speed Rail-to-Rail CMOS Buffer Amplifier for Flat-Panel Displays.
IEEE Trans. Circuits Syst. II Express Briefs
Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi
2018 J jnl
Guest Editorial Special Issue on Selected Papers from PRIME 2017 and SMACD 2017.
Integr.
Giulia Di Capua, Nuno Horta, Francisco V. Fernández, Günhan Dündar, Salvatore Pennisi, Gaetano Palumbo, Massimo Alioto, Gianluca Giustolisi
2018 J jnl
High-Performance Three-Stage Single-Miller CMOS OTA With No Upper Limit of C
IEEE Trans. Circuits Syst. II Express Briefs
Alfio Dario Grasso, Davide Marano, Gaetano Palumbo, Salvatore Pennisi
2018 C conf
Non-Inverting Class-AB CMOS Output Stage for Driving High-Capacitive Loads.
ISCAS
Gianluca Giustolisi, Gaetano Palumbo
2018 C conf
Settling-time oriented OTA design through the approximation of the ideal delay.
ISCAS
Gianluca Giustolisi, Gaetano Palumbo
2018 J jnl
Switched-Capacitor Power Management Integrated Circuit for Autonomous Internet of Things Node.
IEEE Trans. Circuits Syst. II Express Briefs
Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi
2018 — conf
Three-stage single-miller CMOS OTA driving 10 nF with 1.46-MHz GBW.
ICICDT
Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi, Davide Marano
2017 J jnl
Design of Low-Voltage High-Speed CML D-Latches in Nanometer CMOS Technologies.
IEEE Trans. Very Large Scale Integr. Syst.
Giuseppe Scotti, Davide Bellizia, Alessandro Trifiletti, Gaetano Palumbo
2017 J jnl
Robust design of CMOS amplifiers oriented to settling-time specification.
Int. J. Circuit Theory Appl.
Gianluca Giustolisi, Gaetano Palumbo
2017 J jnl
The noise performance of CMOS Miller operational transconductance amplifiers with embedded current-buffer frequency compensation.
Int. J. Circuit Theory Appl.
Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi, Willy Sansen
2016 — conf
A 0.003-mm
ICECS
Davide Marano, Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi
2016 J jnl
Optimized Active Single-Miller Capacitor Compensation With Inner Half-Feedforward Stage for Very High-Load Three-Stage OTAs.
IEEE Trans. Circuits Syst. I Regul. Pap.
Davide Marano, Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi
2016 C conf
Verilog-a modeling of Silicon Photo-Multipliers.
ISCAS
Gianluca Giustolisi, Gaetano Palumbo, Paolo Finocchiaro, Alfio Pappalardo
2015 — conf
195-nW 120-dB subthreshold CMOS OTA driving up to 200 pF and occupying only 4.4-10-3 mm2.
ICECS
Alfio Dario Grasso, Davide Marano, Gaetano Palumbo, Salvatore Pennisi
2015 — conf
A new enhanced PSPICE implementation of the equivalent circuit model of SiPM detectors.
NEWCAS
Davide Marano, Giovanni Bonanno, S. Garozzo, Giuseppe Romeo, Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi
2015 — conf
Comparative analysis of the robustness of master-slave flip-flops against variations.
ICECS
Massimo Alioto, Elio Consoli, Gaetano Palumbo
2015 J jnl
Design Methodology of Subthreshold Three-Stage CMOS OTAs Suitable for Ultra-Low-Power Low-Area and High Driving Capability.
IEEE Trans. Circuits Syst. I Regul. Pap.
Alfio Dario Grasso, Davide Marano, Gaetano Palumbo, Salvatore Pennisi
2015 J jnl
High-Performance Four-Stage CMOS OTA Suitable for Large Capacitive Loads.
IEEE Trans. Circuits Syst. I Regul. Pap.
Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi
2015 J jnl
Integrated Quenching-and-Reset Circuit for Single-Photon Avalanche Diodes.
IEEE Trans. Instrum. Meas.
Gianluca Giustolisi, Alfio Dario Grasso, Gaetano Palumbo
2015 — conf
PVT variations in differential flip-flops: A comparative analysis.
ECCTD
Massimo Alioto, Gaetano Palumbo, Elio Consoli
2015 — conf
Single-miller all-passive compensation network for three-stage OTAs.
ECCTD
Giuseppe Di Cataldo, Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi
2015 J jnl
Three-Stage Dynamic-Biased CMOS Amplifier With a Robust Optimization of the Settling Time.
IEEE Trans. Circuits Syst. I Regul. Pap.
Gianluca Giustolisi, Gaetano Palumbo
2015 — conf
Variability budgetin pulsed flip-flops.
NEWCAS
Massimo Alioto, Gaetano Palumbo, Elio Consoli
2015 J jnl
Variations in Nanometer CMOS Flip-Flops: Part I - Impact of Process Variations on Timing.
IEEE Trans. Circuits Syst. I Regul. Pap.
Massimo Alioto, Elio Consoli, Gaetano Palumbo
2015 J jnl
Variations in Nanometer CMOS Flip-Flops: Part II - Energy Variability and Impact of Other Sources of Variations.
IEEE Trans. Circuits Syst. I Regul. Pap.
Massimo Alioto, Elio Consoli, Gaetano Palumbo
2014 — conf
A new accurate analytical expression for the SiPM transient response to single photons.
ICECS
Davide Marano, Giovanni Bonanno, Massimiliano Belluso, Sergio Billotta, Alessandro Grillo, S. Garozzo, Giuseppe Romeo, Alfio Dario Grasso, Salvatore Pennisi, Gaetano Palumbo
2014 — conf
CMOS class-AB tunable voltage-feedback current operational amplifier.
ICECS
Fermin Esparza-Alfaro, Antonio J. López-Martín, Gaetano Palumbo, Salvatore Permisi
2014 — conf
High-performance frequency compensation topology for four-stage OTAs.
ICECS
Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi, Giuseppe Di Cataldo
2014 J jnl
Low-Power Class-AB CMOS Voltage Feedback Current Operational Amplifier With Tunable Gain and Bandwidth.
IEEE Trans. Circuits Syst. II Express Briefs
Fermin Esparza-Alfaro, Salvatore Pennisi, Gaetano Palumbo, Antonio J. López-Martín
2014 — conf
Monolithic quenching-and-reset circuit for single-photon avalanche diodes.
ICECS
Gianluca Giustolisi, Alfio Dario Grasso, Gaetano Palumbo
2014 J jnl
Novel Class of Energy-Efficient Very High-Speed Conditional Push-Pull Pulsed Latches.
IEEE Trans. Very Large Scale Integr. Syst.
Elio Consoli, Gaetano Palumbo, Jan M. Rabaey, Massimo Alioto
2014 J jnl
Self-Biased Dual-Path Push-Pull Output Buffer Amplifier for LCD Column Drivers.
IEEE Trans. Circuits Syst. I Regul. Pap.
Alfio Dario Grasso, Davide Marano, Fermin Esparza-Alfaro, Antonio J. López-Martín, Gaetano Palumbo, Salvatore Pennisi
2013 — conf
A simple extraction procedure for determining the electrical parameters in Silicon Photomultipliers.
ECCTD
Gianluca Giustolisi, Gaetano Palumbo, Paolo Finocchiaro, Alfio Pappalardo
2013 — conf
Optimized frequency compensation topology for low-power three-stage OTAs.
ECCTD
Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi
2012 J jnl
A Simple Circuit Approach to Reduce Delay Variations in Domino Logic Gates.
IEEE Trans. Circuits Syst. I Regul. Pap.
Gaetano Palumbo, Melita Pennisi, Massimo Alioto
2012 C conf
A simple keeper topology to reduce delay variations in nanometer domino logic.
ISCAS
Massimo Alioto, Gaetano Palumbo, Melita Pennisi
2012 J jnl
An Accurate Ultra-Compact I-V Model for Nanometer MOS Transistors With Applications on Digital Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap.
Elio Consoli, Gianluca Giustolisi, Gaetano Palumbo
2012 J jnl
Behavioral modeling of statistical phenomena of single-photon avalanche diodes.
Int. J. Circuit Theory Appl.
Gianluca Giustolisi, Rosario Mita, Gaetano Palumbo
2012 — conf
Conditional push-pull pulsed latches with 726fJ·ps energy-delay product in 65nm CMOS.
ISSCC
Elio Consoli, Massimo Alioto, Gaetano Palumbo, Jan M. Rabaey
2012 J jnl
From energy-delay metrics to constraints on the design of digital circuits.
Int. J. Circuit Theory Appl.
Massimo Alioto, Elio Consoli, Gaetano Palumbo
2012 C conf
Logic gates dynamic modeling by means of an ultra-compact MOS model.
ISCAS
Elio Consoli, Gianluca Giustolisi, Gaetano Palumbo
2012 J jnl
Reconsidering High-Speed Design Criteria for Transmission-Gate-Based Master-Slave Flip-Flops.
IEEE Trans. Very Large Scale Integr. Syst.
Elio Consoli, Gaetano Palumbo, Melita Pennisi
2012 J jnl
Robust Miller Compensation With Current Amplifiers Applied to LDO Voltage Regulators.
IEEE Trans. Circuits Syst. I Regul. Pap.
Gianluca Giustolisi, Gaetano Palumbo, Ester Spitale
2011 — conf
An ultra-compact MOS model in nanometer technologies.
ECCTD
Elio Consoli, Gianluca Giustolisi, Gaetano Palumbo
2011 J jnl
Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part I - Methodology and Design Strategies.
IEEE Trans. Very Large Scale Integr. Syst.
Massimo Alioto, Elio Consoli, Gaetano Palumbo
2011 J jnl
Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part II - Results and Figures of Merit.
IEEE Trans. Very Large Scale Integr. Syst.
Massimo Alioto, Elio Consoli, Gaetano Palumbo
2011 C conf
DET FF topologies: A detailed investigation in the energy-delay-area domain.
ISCAS
Massimo Alioto, Elio Consoli, Gaetano Palumbo
2011 — conf
Figures of merit for class AB input stages.
ECCTD
Gaetano Palumbo, Melita Pennisi, Ramón González Carvajal
2011 — conf
Inverter transfer curves and SRAM noise margin evaluation based on an ultra-compact MOS model.
ECCTD
Elio Consoli, Gianluca Giustolisi, Gaetano Palumbo
2011 J jnl
Optimized design of parallel carry-select adders.
Integr.
Massimo Alioto, Gaetano Palumbo, Massimo Poli
2011 C conf
Self-biased dual-path push-pull output buffer amplifier topology for LCD driver applications.
ISCAS
Davide Marano, Gaetano Palumbo, Salvatore Pennisi
2011 C conf
TG Master-Slave FFs: High-speed optimization.
ISCAS
Elio Consoli, Gaetano Palumbo, Melita Pennisi
2011 C conf
Verilog-A modeling of SPAD statistical phenomena.
ISCAS
Gianluca Giustolisi, Rosario Mita, Gaetano Palumbo
2010 C conf
A novel low-power high-speed rail-to-rail class-B buffer amplifier for LCD output drivers.
ISCAS
Davide Marano, Gaetano Palumbo, Salvatore Pennisi
2010 J jnl
Analytical comparison of reversed nested Miller frequency compensation techniques.
Int. J. Circuit Theory Appl.
Alfio Dario Grasso, Davide Marano, Gaetano Palumbo, Salvatore Pennisi
2010 C conf
Analytical figure of merit evaluation of RNMC networks for low-power three-stage OTAs.
ISCAS
Davide Marano, Gaetano Palumbo, Salvatore Pennisi
2010 C conf
Clock distribution in clock domains with Dual-Edge-Triggered Flip-Flops to improve energy-efficiency.
ISCAS
Massimo Alioto, Elio Consoli, Gaetano Palumbo
2010 J jnl
Flip-Flop Energy/Performance Versus Clock Slope and Impact on the Clock Network Design.
IEEE Trans. Circuits Syst. I Regul. Pap.
Massimo Alioto, Elio Consoli, Gaetano Palumbo
2010 J jnl
General Strategies to Design Nanometer Flip-Flops in the Energy-Delay Space.
IEEE Trans. Circuits Syst. I Regul. Pap.
Massimo Alioto, Elio Consoli, Gaetano Palumbo
2010 J jnl
Improved Low-Power High-Speed Buffer amplifier with slew-Rate Enhancement for LCD Applications.
J. Circuits Syst. Comput.
Davide Marano, Gaetano Palumbo, Salvatore Pennisi
2010 C conf
Low-power dual-active class-AB buffer amplifier with self-biasing network for LCD column drivers.
ISCAS
Davide Marano, Gaetano Palumbo, Salvatore Pennisi
2010 — conf
Physical Design Aware Comparison of Flip-Flops for High-Speed Energy-Efficient VLSI Circuits.
PATMOS
Massimo Alioto, Elio Consoli, Gaetano Palumbo
2010 J jnl
Simple and accurate modeling of the output transition time in nanometer CMOS gates.
Int. J. Circuit Theory Appl.
Massimo Alioto, Gaetano Palumbo, Massimo Poli
2010 J jnl
Step-response optimisation techniques for low-power, high-load, three-stage operational amplifiers driving large capacitive loads.
IET Circuits Devices Syst.
Davide Marano, Gaetano Palumbo, Salvatore Pennisi
2010 J jnl
Understanding the Effect of Process Variations on the Delay of Static and Domino Logic.
IEEE Trans. Very Large Scale Integr. Syst.
Massimo Alioto, Gaetano Palumbo, Melita Pennisi
2009 C conf
A New Advanced RNMC Technique with Dual-active Current and Voltage Buffers for Low-power High-load Three-stage Amplifiers.
ISCAS
Davide Marano, Gaetano Palumbo, Salvatore Pennisi
2009 — conf
A high-speed low-power output buffer amplifier for large-size LCD applications.
ICECS
Davide Marano, Gaetano Palumbo, Salvatore Pennisi
2009 — conf
An efficient RNM compensation topology with voltage buffer and nulling resistors for large-capacitive-load three-stage OTAs.
ICECS
Davide Marano, Gaetano Palumbo, Salvatore Pennisi
2009 J jnl
Analysis and Modeling of Energy Consumption in RLC Tree Circuits.
IEEE Trans. Very Large Scale Integr. Syst.
Massimo Alioto, Gaetano Palumbo, Massimo Poli
2009 — conf
Analysis of the impact of random process variations in CMOS tapered buffers.
ICECS
Massimo Alioto, Gaetano Palumbo, Melita Pennisi
2009 J jnl
Approach to analyse and design nearly sinusoidal oscillators.
IET Circuits Devices Syst.
Gaetano Palumbo, Melita Pennisi, Salvatore Pennisi
2009 — conf
Correct procedures to evaluate the effect of intradie variations on the delay variability of digital circuits.
ECCTD
Massimo Alioto, Elio Consoli, Gaetano Palumbo, Melita Pennisi
2009 — conf
Exploitation of the phasor approach for closed-form solution of the Van der Pol's oscillator and sinusoidal oscillators with high-order nonlinearity.
ICECS
Gaetano Palumbo, Melita Pennisi, Salvatore Pennisi
2009 — conf
Impact of clock slope on energy/delay of pulsed flip-flops and optimum clock domain design.
ECCTD
Massimo Alioto, Elio Consoli, Gaetano Palumbo
2009 J jnl
Improved Power-Efficient RNMC Technique with voltage Buffer and Nulling resistors for Low-Power High-Load Three-Stage amplifiers.
J. Circuits Syst. Comput.
Davide Marano, Gaetano Palumbo, Salvatore Pennisi
2009 C conf
Metrics and Design Considerations on the Energy-delay Tradeoff of Digital Circuits.
ISCAS
Massimo Alioto, Elio Consoli, Gaetano Palumbo
2009 — conf
Optimum clock slope for flip-flops within a clock domain: Analysis and a case study.
ICECS
Massimo Alioto, Elio Consoli, Gaetano Palumbo
2009 J jnl
Propagation delay of an RC-circuit with a ramp input: An analytical very accurate and simple model.
Int. J. Circuit Theory Appl.
Rosario Mita, Gaetano Palumbo
2009 C conf
Step-response Optimization Techniques for Low-power Three-stage Operational Amplifiers for Large Capacitive Load Applications.
ISCAS
Davide Marano, Gaetano Palumbo, Salvatore Pennisi
2008 J jnl
AMOLED pixel driver circuits based on poly-Si TFTs: A comparison.
Integr.
Gaetano Palumbo, Melita Pennisi
2008 J jnl
Accurate model for single-photon avalanche diodes.
IET Circuits Devices Syst.
Rosario Mita, Gaetano Palumbo, Pier Giorgio Fallica
2008 J jnl
An approach to model high-frequency distortion in negative-feedback amplifiers.
Int. J. Circuit Theory Appl.
Salvatore Omar Cannizzaro, Gaetano Palumbo, Salvatore Pennisi
2008 — conf
Analysis of the impact of process variations on static logic circuits versus fan-in.
ICECS
Massimo Alioto, Gaetano Palumbo, Melita Pennisi
2008 J jnl
Analytical comparison of frequency compensation techniques in three-stage amplifiers.
Int. J. Circuit Theory Appl.
Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi
2008 J jnl
Comparison of the Frequency Compensation Techniques for CMOS Two-Stage Miller OTAs.
IEEE Trans. Circuits Syst. II Express Briefs
Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi
2008 — conf
Design guidelines for high-speed Transmission-gate latches: Analysis and comparison.
ICECS
Gaetano Palumbo, Melita Pennisi
2008 — conf
Design guidelines for minimum harmonic distortion in a wien oscillator with automatic amplitude control system.
ICECS
Gaetano Palumbo, Melita Pennisi, Salvatore Pennisi
2008 J jnl
Design methodology of Miller frequency compensation with current buffer/amplifier.
IET Circuits Devices Syst.
Walter Aloisi, Gaetano Palumbo, Salvatore Pennisi
2008 — conf
Energy evaluation in RLC tree circuits with exponential input.
ICECS
Massimo Alioto, Gaetano Palumbo, Massimo Poli
2008 C conf
Explicit energy evaluation in RLC tree circuits with ramp inputs.
ISCAS
Massimo Alioto, Massimo Poli, Gaetano Palumbo
2008 J jnl
High-Speed and Compact Quenching Circuit for Single-Photon Avalanche Diodes.
IEEE Trans. Instrum. Meas.
Rosario Mita, Gaetano Palumbo
2008 C conf
Low-voltage LDO Compensation Strategy based on Current Amplifiers.
ISCAS
Gianluca Giustolisi, Gaetano Palumbo, Ester Spitale
2008 J jnl
Miller Theorem for Weakly Nonlinear Feedback Circuits and Application to CE Amplifier.
IEEE Trans. Circuits Syst. II Express Briefs
Gaetano Palumbo, Melita Pennisi, Salvatore Pennisi
2008 J jnl
Power-Aware Design of Nanometer MCML Tapered Buffers.
IEEE Trans. Circuits Syst. II Express Briefs
Massimo Alioto, Gaetano Palumbo
2008 C conf
Power-delay optimization in MCML tapered buffers.
ISCAS
Massimo Alioto, Gaetano Palumbo
2008 J jnl
Single Miller capacitor frequency compensation with nulling resistor for three-stage amplifiers.
Int. J. Circuit Theory Appl.
Salvatore Omar Cannizzaro, Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi
2008 — conf
Understanding the Effect of Intradie Random Process Variations in Nanometer Domino Logic.
PATMOS
Massimo Alioto, Gaetano Palumbo, Melita Pennisi
2008 J jnl
Wien-Type Oscillators: Evaluation and Optimization of Harmonic Distortion.
IEEE Trans. Circuits Syst. II Express Briefs
Gaetano Palumbo, Melita Pennisi, Salvatore Pennisi
2007 — conf
A generalization of Miller formulae for nonlinear feedback networks.
ECCTD
Giuseppe Di Cataldo, Gaetano Palumbo, Melita Pennisi, Salvatore Pennisi
2007 J jnl
Advances in Reversed Nested Miller Compensation.
IEEE Trans. Circuits Syst. I Regul. Pap.
Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi
2007 C conf
Delay Variability Due to Supply Variations in Transmission-Gate Full Adders.
ISCAS
Massimo Alioto, Gaetano Palumbo
2007 J jnl
Design Procedures for Three-Stage CMOS OTAs With Nested-Miller Compensation.
IEEE Trans. Circuits Syst. I Regul. Pap.
Salvatore Omar Cannizzaro, Alfio Dario Grasso, Rosario Mita, Gaetano Palumbo, Salvatore Pennisi
2007 C conf
Design of Fast Large Fan-In CMOS Multiplexers Accounting for Interconnects.
ISCAS
Massimo Alioto, Gaetano Palumbo
2007 — conf
Distortion analysis in the frequency domain of a Gm-C biquad.
ECCTD
Gaetano Palumbo, Melita Pennisi, Salvatore Pennisi
2007 — conf
Efficient and Accurate Models of Output Transition Time in CMOS Logic.
ICECS
Massimo Alioto, Massimo Poli, Gaetano Palumbo
2007 — conf
Energy consumption in RLC tree circuits.
ECCTD
Massimo Alioto, Gaetano Palumbo, Massimo Poli
2007 C conf
High-Speed/Low-Power Mixed Full Adder Chains: Analysis and Comparison versus Technology.
ISCAS
Massimo Alioto, Gaetano Palumbo
2007 — conf
Highly-accurate propagation delay analytical model of an RC-circuit with a ramp input.
ECCTD
Rosario Mita, Gaetano Palumbo
2007 J jnl
Improved Reversed Nested Miller Frequency Compensation Technique With Voltage Buffer and Resistor.
IEEE Trans. Circuits Syst. II Express Briefs
Alfio Dario Grasso, Davide Marano, Gaetano Palumbo, Salvatore Pennisi
2007 J jnl
Interconnect-Aware Design of Fast Large Fan-In CMOS Multiplexers.
IEEE Trans. Circuits Syst. II Express Briefs
Massimo Alioto, Gaetano Palumbo
2007 — conf
LDO compensation strategy based on current buffer/amplifiers.
ECCTD
Gianluca Giustolisi, Gaetano Palumbo, Ester Spitale
2007 C conf
Miller Compensation: Optimization with Current Buffer/Amplifier.
ISCAS
Walter Aloisi, Giuseppe Di Cataldo, Gaetano Palumbo, Salvatore Pennisi
2007 J jnl
Mixed Full Adder topologies for high-performance low-power arithmetic circuits.
Microelectron. J.
Massimo Alioto, Giuseppe Di Cataldo, Gaetano Palumbo
2007 J jnl
Propagation Delay of an
IEEE Trans. Circuits Syst. II Express Briefs
Rosario Mita, Gaetano Palumbo, Massimo Poli
2007 J jnl
Resistance of Feedback Amplifiers: A Novel Representation.
IEEE Trans. Circuits Syst. II Express Briefs
Arnaldo D'Amico, Christian Falconi, Gianluca Giustolisi, Gaetano Palumbo
2007 C conf
Rosenstark-like Representation of Feedback Amplifier Resistance.
ISCAS
Christian Falconi, Arnaldo D'Amico, Gianluca Giustolisi, Gaetano Palumbo
2007 — conf
Single Miller capacitor frequency compensation with nulling resistor for three-stage amplifiers.
ECCTD
Salvatore Omar Cannizzaro, Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi
2007 — conf
Very high-speed carry computation based on mixed dynamic/transmission-gate Full Adders.
ECCTD
Massimo Alioto, Gaetano Palumbo
2006 — conf
A Design Methodology for High-Speed Low-Power MCML Frequency Dividers.
ICECS
Massimo Alioto, Rosario Mita, Gaetano Palumbo
2006 J jnl
A fast driver circuit for single-photon sensors.
Microelectron. J.
Rosario Mita, Gaetano Palumbo, Pier Giorgio Fallica
2006 C conf
Active reversed nested Miller compensation for three-stage amplifiers.
ISCAS
Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi
2006 C conf
Analysis and evaluation of harmonic distortion in the tunnel diode oscillator.
ISCAS
Gaetano Palumbo, Melita Pennisi, Salvatore Pennisi
2006 — conf
Analysis of Harmonic Distortion in the Colpitts Oscillator.
ICECS
Gaetano Palumbo, Melita Pennisi, Salvatore Pennisi
2006 J jnl
Charge pump circuits with only capacitive loads: optimized design.
IEEE Trans. Circuits Syst. II Express Briefs
Gaetano Palumbo, Domenico Pappalardo
2006 C conf
Delay uncertainty due to supply variations in static and dynamic full adders.
ISCAS
Massimo Alioto, Gaetano Palumbo
2006 J jnl
Design of High-Speed Power-Efficient MOS Current-Mode Logic Frequency Dividers.
IEEE Trans. Circuits Syst. II Express Briefs
Massimo Alioto, Rosario Mita, Gaetano Palumbo
2006 J jnl
Design strategies of cascaded CML gates.
IEEE Trans. Circuits Syst. II Express Briefs
Massimo Alioto, Gaetano Palumbo
2006 J jnl
Distortion analysis of Miller-compensated three-stage amplifiers.
IEEE Trans. Circuits Syst. I Regul. Pap.
Salvatore Omar Cannizzaro, Gaetano Palumbo, Salvatore Pennisi
2006 J jnl
Effects of nonlinear feedback in the frequency domain.
IEEE Trans. Circuits Syst. I Regul. Pap.
Salvatore Omar Cannizzaro, Gaetano Palumbo, Salvatore Pennisi
2006 C conf
Efficient output transition time modeling in CMOS gates with ramp/exponential inputs.
ISCAS
Massimo Alioto, Gaetano Palumbo, Massimo Poli
2006 J jnl
Energy Consumption in RC Tree Circuits.
IEEE Trans. Very Large Scale Integr. Syst.
Massimo Alioto, Gaetano Palumbo, Massimo Poli
2006 J jnl
Impact of Supply Voltage Variations on Full Adder Delay: Analysis and Comparison.
IEEE Trans. Very Large Scale Integr. Syst.
Massimo Alioto, Gaetano Palumbo
2006 — conf
Modeling of Delay Variability Due to Supply Variations in Pass-Transistor and Static Full Adders.
ICECS
Massimo Alioto, Gaetano Palumbo
2006 — conf
Modeling of Feedback Analog Circuits with VHDL.
ICECS
Giuseppe Di Cataldo, Rosario Mita, Gaetano Palumbo, Melita Pennisi
2006 — conf
NMOS Low Drop-Out Regulator with Dynamic Biasing.
ICECS
Gianluca Giustolisi, Gaetano Palumbo, Christian Falconi, Arnaldo D'Amico
2006 C conf
Nanometer MCML gates: models and design considerations.
ISCAS
Massimo Alioto, Gaetano Palumbo
2006 — conf
RC-Chain: a Simple Model of Delay with a Ramp Input.
ICECS
Giuseppe Di Cataldo, Rosario Mita, Gaetano Palumbo, Massimo Poli
2006 J jnl
Three-Stage CMOS OTA for Large Capacitive Loads With Efficient Frequency Compensation Scheme.
IEEE Trans. Circuits Syst. II Express Briefs
Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi
2005 — conf
A comparison between amoled poly-TFT driver circuits.
ICECS
Gaetano Palumbo, Melita Pennisi
2005 — conf
A fast active quenching and recharging circuit for single-photon avalanche diodes.
ECCTD
Rosario Mita, Gaetano Palumbo, Giorgio Fallica
2005 J jnl
A high-performance very low-voltage current sense amplifier for nonvolatile memories.
IEEE J. Solid State Circuits
Antonino Conte, Gianbattista Lo Giudice, Gaetano Palumbo, Alfredo Signorello
2005 — conf
A novel model for single photon detectors.
ICECS
Rosario Mita, Andrea Oliveri, Gaetano Palumbo, Pier Giorgio Fallica
2005 — conf
Analysis and optimization of a low-voltage class-AB output stage.
ICECS
Walter Aloisi, Gianluca Giustolisi, Gaetano Palumbo
2005 — conf
Behavioral model of charge pumps with VHDL.
ICECS
Rosario Mita, Gaetano Palumbo, Melita Pennisi
2005 — conf
Comparison of methods for predicting distortion in class-AB stages.
ICECS
Gianluca Giustolisi, Gaetano Palumbo
2005 J jnl
Design and Comparison of Very Low-Voltage CMOS Output Stages.
IEEE Trans. Circuits Syst. I Regul. Pap.
Walter Aloisi, Gianluca Giustolisi, Gaetano Palumbo
2005 — conf
Design strategy to minimize rise time and silicon area of charge pump with only capacitive loads.
ICECS
Gaetano Palumbo, Domenico Pappalardo, Luigi Innacolo
2005 — conf
Design techniques for low-power cascaded CML gates.
ISCAS (5)
Massimo Alioto, Gaetano Palumbo
2005 — conf
Distortion analysis of three-stage amplifiers with reversed nested-Miller compensation.
ECCTD
Salvatore Omar Cannizzaro, Gaetano Palumbo, Salvatore Pennisi
2005 J jnl
Efficiency model of boost dc-dc PWM converters.
Int. J. Circuit Theory Appl.
Walter Aloisi, Gaetano Palumbo
2005 — conf
Energy Consumption in RC Tree Circuits with Exponential Inputs: An Analytical Model.
PATMOS
Massimo Alioto, Gaetano Palumbo, Massimo Poli
2005 — conf
Guidelines for designing class-AB output stages.
ECCTD
Walter Aloisi, Gianluca Giustolisi, Gaetano Palumbo
2005 J jnl
Low-voltage high-drive CMOS current feedback op-amp.
IEEE Trans. Circuits Syst. II Express Briefs
Rosario Mita, Gaetano Palumbo, Salvatore Pennisi
2005 J jnl
Modelling and design considerations on CML gates under high-current effects.
Int. J. Circuit Theory Appl.
Massimo Alioto, Gaetano Palumbo
2005 — conf
New analytical approach to evaluate harmonic distortion in nonlinear feedback amplifiers.
ECCTD
Salvatore Omar Cannizzaro, Gaetano Palumbo, Salvatore Pennisi
2005 J jnl
Nonidealities of Tow-Thomas biquads Using VOA- and CFOA-based Miller integrators.
IEEE Trans. Circuits Syst. II Express Briefs
Rosario Mita, Gaetano Palumbo, Salvatore Pennisi
2005 — conf
Optimized design of ECL gates with a power constraint.
ECCTD
Alfio Dario Grasso, Gaetano Palumbo
2005 — conf
Optimized design of source coupled logic gates in GaAs HEMT technology.
ISCAS (4)
Gaetano Palumbo, Pasquale Tommasino, Alessandro Trifiletti
2005 J jnl
Power-delay optimization of D-latch/MUX source coupled logic gates.
Int. J. Circuit Theory Appl.
Massimo Alioto, Gaetano Palumbo
2005 — conf
Statistical analysis of CMOS current reference.
ECCTD
Gianluca Giustolisi, Gaetano Palumbo, Maurizio Gaibotti, Michelangelo Pisasale
2005 — conf
VHDL-based modeling of a DC-DC boost converter.
ICECS
Rosario Mita, Gaetano Palumbo
2005 — conf
Well-defined design procedure for a three-stage CMOS OTA.
ISCAS (3)
Rosario Mita, Gaetano Palumbo, Salvatore Pennisi
2004 — conf
A 1.35-V sense amplifier for non volatile memories based on current mode approach.
ESSCIRC
Antonino Conte, Gianbattista Lo Giudice, Gaetano Palumbo, Alfredo Signorello
2004 — conf
A gate-level strategy to design Carry Select Adders.
ISCAS (2)
Massimo Alioto, Gaetano Palumbo, Massimo Poli
2004 J jnl
Effect of CFOA nonidealities in Miller integrator cells.
IEEE Trans. Circuits Syst. II Express Briefs
Rosario Mita, Gaetano Palumbo, Salvatore Pennisi
2004 J jnl
Evaluation of energy consumption in RC ladder circuits driven by a ramp input.
IEEE Trans. Very Large Scale Integr. Syst.
Massimo Alioto, Gaetano Palumbo, Massimo Poli
2004 J jnl
Exploiting the high-frequency performance of low-voltage low-power SC filters.
IEEE Trans. Circuits Syst. II Express Briefs
Walter Aloisi, Gianluca Giustolisi, Gaetano Palumbo
2004 — conf
Harmonic distortion in three-stage nested-Miller-compensated amplifiers.
ISCAS (1)
Gaetano Palumbo, Salvatore Pennisi
2004 — conf
Low-voltage linear voltage regulator suitable for memories.
ISCAS (1)
Walter Aloisi, Stello Matteo Billé, Gaetano Palumbo
2004 — conf
Sigma-Delta A/D fuzzy converter.
ISCAS (4)
Gianluca Giustolisi, Gaetano Palumbo
2003 J jnl
1.5-V CMOS CCII+ with high current-driving capability.
IEEE Trans. Circuits Syst. II Express Briefs
Rosario Mita, Gaetano Palumbo, Salvatore Pennisi
2003 — conf
A 1-V CMOS output stage with high linearity.
ISCAS (1)
Walter Aloisi, Gianluca Giustolisi, Gaetano Palumbo
2003 J jnl
A low-voltage low-power voltage reference based on subthreshold MOSFETs.
IEEE J. Solid State Circuits
Gianluca Giustolisi, Gaetano Palumbo, M. Criscione, F. Cutri
2003 — conf
A new method for evaluating harmonic distortion in push-pull output stages.
ISCAS (1)
Gianluca Giustolisi, Gaetano Palumbo
2003 — conf
A novel 1-V class-AB transconductor for improving speed performance in SC applications.
ISCAS (1)
Gianluca Giustolisi, Gaetano Palumbo
2003 J jnl
Analysis, modelling and optimization of a gain boosted telescopic amplifier.
Int. J. Circuit Theory Appl.
Walter Aloisi, Gianluca Giustolisi, Gaetano Palumbo
2003 J jnl
Design guidelines for reversed nested Miller compensation in three-stage amplifiers.
IEEE Trans. Circuits Syst. II Express Briefs
Rosario Mita, Gaetano Palumbo, Salvatore Pennisi
2003 — conf
Design of MUX, XOR and D-latch SCL gates.
ISCAS (5)
Massimo Alioto, Gaetano Palumbo
2003 — conf
Design of low-voltage low-power SC filters for high-frequency applications.
ISCAS (1)
Walter Aloisi, Gianluca Giustolisi, Gaetano Palumbo
2003 — conf
Performance comparison of Tow-Thomas biquad filters based on VOAs and CFOAs.
ISCAS (1)
Rosario Mita, Gaetano Palumbo, Salvatore Pennisi
2003 J jnl
Performance evaluation of the low-voltage CML D-latch topology.
Integr.
Massimo Alioto, Rosario Mita, Gaetano Palumbo
2002 — conf
A high-performance buffer for non-volatile memories.
ICECS
L. De Ambrogi, S. Nicosia, Giovanni Pagano, Gaetano Palumbo
2002 — conf
A novel pseudo random bit generator for cryptography applications.
ICECS
Rosario Mita, Gaetano Palumbo, Salvatore Pennisi, Massimo Poli
2002 — conf
An Approach to Energy Consumption Modeling in RC Ladder Circuits.
PATMOS
Massimo Alioto, Gaetano Palumbo, Massimo Poli
2002 — conf
Analysis and comparison of low-voltage CML D-latch.
ICECS
Massimo Alioto, Rosario Mita, Gaetano Palumbo
2002 J jnl
Analysis and comparison on full adder block in submicron technology.
IEEE Trans. Very Large Scale Integr. Syst.
Massimo Alioto, Gaetano Palumbo
2002 — conf
Analysis and optimization of gain-boosted telescopic amplifiers.
ISCAS (1)
Walter Aloisi, Gianluca Giustolisi, Gaetano Palumbo
2002 — conf
Analysis of power supply noise attenuation in a PTAT current source.
ISCAS (1)
Gianluca Giustolisi, Gaetano Palumbo
2002 — conf
Comparison between Miller integrator cells using VOAs and CFOAs.
ICECS
Rosario Mita, Gaetano Palumbo, Salvatore Pennisi
2002 J jnl
Current-mode A/D fuzzy converter.
IEEE Trans. Fuzzy Syst.
Gianluca Giustolisi, Gaetano Palumbo, Salvatore Pennisi
2002 — conf
Design guidelines for bipolar frequency dividers.
ICECS
Massimo Alioto, Giuseppe Di Cataldo, Gaetano Palumbo
2002 — conf
Evaluation on power reduction applying gated clock approaches.
ISCAS (4)
Gaetano Palumbo, Francesco Pappalardo, S. Sannella
2002 — conf
Hybrid nested Miller compensation with nulling resistors.
ICECS
Rosario Mita, Gaetano Palumbo, Salvatore Pennisi
2002 C conf
Low Power Strategy for a TFT Controller.
DSD
Giuseppe Notarangelo, Marco Gibilaro, Francesco Pappalardo, Agatino Pennisi, Gaetano Palumbo
2002 — conf
Modeling Propagation Delay of MUX, XOR, and D-Latch Source-Coupled Logic Gates.
PATMOS
Massimo Alioto, Gaetano Palumbo
2002 — conf
Modeling of Propagation Delay of a First Order Circuit with a Ramp Input.
PATMOS
Rosario Mita, Gaetano Palumbo
2002 J jnl
Modelling of source-coupled logic gates.
Int. J. Circuit Theory Appl.
Massimo Alioto, Gaetano Palumbo, Salvatore Pennisi
2002 — conf
Power-delay trade-offs in SCL gates.
ISCAS (3)
Massimo Alioto, Gaetano Palumbo
2002 — conf
Propagation delay model of current driven RC chain.
ICECS
Gaetano Palumbo, Massimo Poli
2002 — conf
Statistical analysis of the resolution in a current-mode ADC.
ICECS
Gianluca Giustolisi, Gaetano Palumbo, Salvatore Pennisi
2002 — conf
Voltage regulator based on an high-efficiency adaptive charge pump.
ICECS
Gaetano Palumbo, Domenico Pappalardo, Maurizio Gaibotti
2001 — conf
A fuzzy controller for step-up DC/DC converters.
ICECS
M. Criscione, Gianluca Giustolisi, A. Lionetto, M. Muscarà, Gaetano Palumbo
2001 J jnl
A high‐performance CMOS CCII.
Int. J. Circuit Theory Appl.
Gaetano Palumbo, Salvatore Pennisi
2001 J jnl
Analysis and optimization of a novel CMOS multiplier.
Int. J. Circuit Theory Appl.
Gianluca Giustolisi, Giuseppe Palmisano, Gaetano Palumbo
2001 — conf
Built-In Self Test for Low Cost Testing of a 60 MHz Synchronous Flash Memory.
IOLTW
Gaetano Palumbo, Giuseppe Introvaia, Vincenzo Mastrocola, Promod Kumar, Francesco Pipiton
2001 — conf
CML ring oscillators: oscillation frequency.
ISCAS (4)
Massimo Alioto, Giuseppe Di Cataldo, Gaetano Palumbo
2001 — conf
Delay estimation of SCL gates with output buffer.
ICECS
Massimo Alioto, Gaetano Palumbo, Salvatore Pennisi
2001 — conf
Detailed frequency analysis of power supply rejection in Brokaw bandgap.
ISCAS (1)
Gianluca Giustolisi, Gaetano Palumbo
2001 — conf
Feedback amplifiers: a simplified analysis of harmonic distortion in the frequency domain.
ICECS
Gaetano Palumbo, Salvatore Pennisi
2001 — conf
Modeling and minimization of power consumption in charge pump circuits.
ISCAS (4)
Gaetano Palumbo, Domenico Pappalardo, Maurizio Gaibotti
2001 — conf
Optimized design of high fan-in multiplexers using switches with driving capability.
ICECS
Massimo Alioto, Gaetano Palumbo
2001 J jnl
Power estimation in adiabatic circuits: a simple and accurate model.
IEEE Trans. Very Large Scale Integr. Syst.
Massimo Alioto, Gaetano Palumbo
2001 — conf
Reversed nested Miller compensation with current follower.
ISCAS (1)
Rosario Mita, Gaetano Palumbo, Salvatore Pennisi
2000 C conf
A fuzzy membership function circuit in SC technique.
ISCAS
Gianluca Giustolisi, Giuseppe Palmisano, Gaetano Palumbo
2000 J jnl
CMRR frequency response of CMOS operational transconductance amplifiers.
IEEE Trans. Instrum. Meas.
Gianluca Giustolisi, Giuseppe Palmisano, Gaetano Palumbo
2000 C conf
Evaluation of power consumption in adiabatic circuits.
ISCAS
Massimo Alioto, Gaetano Palumbo
2000 C conf
High-speed bipolar MUX modeling and design.
ISCAS
Massimo Alioto, Gaetano Palumbo
2000 — conf
Modeling of Power Consumption of Adiabatic Gates versus Fan in and Comparison with Conventional Gates.
PATMOS
Massimo Alioto, Gaetano Palumbo
1999 — conf
A class AB CMOS current mirror with low-voltage capability.
ICECS
Gaetano Palumbo, Salvatore Pennisi
1999 — conf
A general HDL-A model of a DC-DC switching regulator core.
ICECS
Gaetano Palumbo, Davide Torrisi, Riccardo Ursino
1999 J jnl
High-speed voltage buffers for the experimental characterization of CMOS transconductance operational amplifiers.
IEEE Trans. Instrum. Meas.
Giuseppe Di Cataldo, Giuseppe Palmisano, Gaetano Palumbo, Salvatore Pennisi
1999 J jnl
Highly accurate and simple models for CML and ECL gates.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Massimo Alioto, Gaetano Palumbo
1999 — conf
Performance parameters of current operational amplifiers.
ICECS
Giuseppe Palmisano, Gaetano Palumbo, Salvatore Pennisi
1998 — conf
A 1.5 V CMOS voltage multiplier.
ICECS
Gianluca Giustolisi, Giuseppe Palmisano, Gaetano Palumbo
1998 — conf
A Novel 1.5-V Cmos Mixer.
Great Lakes Symposium on VLSI
Gianluca Giustolisi, Giuseppe Palmisano, Gaetano Palumbo, C. Strano
1998 — conf
A high-performance CMOS voltage follower.
ICECS
Gaetano Palumbo, Salvatore Pennisi
1998 J jnl
A novel fully adjustable CMOS current Schmitt trigger with a 1·5 V power supply.
Int. J. Circuit Theory Appl.
Gaetano Palumbo
1998 — conf
A technique for the reduction of the input resistance of current-mode circuits.
ICECS
Gaetano Palumbo, Salvatore Pennisi
1998 — conf
Design of CML gate with the best propagation delay.
ICECS
Massimo Alioto, Gaetano Palumbo
1998 J jnl
Harmonic distortion in non-linear amplifier with non-linear feedback.
Int. J. Circuit Theory Appl.
Gaetano Palumbo, Salvatore Pennisi
1998 J jnl
High-drive CMOS current amplifier.
IEEE J. Solid State Circuits
Giuseppe Palmisano, Gaetano Palumbo, Salvatore Pennisi
1998 — conf
Novel Simple Models Of Cml Propagation Delay.
Great Lakes Symposium on VLSI
Massimo Alioto, Gaetano Palumbo
1996 J jnl
Area-efficient design of three- and four-stage voltage multipliers for power integrated circuits.
Int. J. Circuit Theory Appl.
Giuseppe Di Cataldo, Gaetano Palumbo
1996 — conf
Low harmonic distortion class AB CMOS current output stage.
ICECS
Giuseppe Palmisano, Gaetano Palumbo, Salvatore Pennisi
1996 — conf
Simplified model of an amplifier with two poles and a pole-zero doublet.
ICECS
Giuseppe Palmisano, Gaetano Palumbo
1995 C conf
A CMOS CCII+.
ISCAS
Giuseppe Di Cataldo, Giuseppe Palmisano, Gaetano Palumbo
1995 J jnl
A schmitt trigger by means of a ccii+.
Int. J. Circuit Theory Appl.
G. Diutaldo, Gaetano Palumbo, Salvatore Pennisi
1995 J jnl
A simple cmos CCII+.
Int. J. Circuit Theory Appl.
Giuseppe Palmisano, Gaetano Palumbo
1995 J jnl
An Area Efficient Current limiter for Automotive IC: Analysis and Design.
J. Circuits Syst. Comput.
Giovanni Calí, Giuseppe Palmisano, Gaetano Palumbo, N. Aiello
1994 C conf
A High-Accuracy High-Speed CMOS Current Comparator.
ISCAS
Giuseppe Palmisano, Gaetano Palumbo, Salvatore Pennisi
1994 J jnl
A high-frequency differential sc integrator with highly accurate gain compensation.
Int. J. Circuit Theory Appl.
Giuseppe Palmisano, Gaetano Palumbo, Victor da Fonte Dias
1994 J jnl
Cmos current comparator: Simplified analysis of the delay time.
Int. J. Circuit Theory Appl.
Gaetano Palumbo
1994 C conf
Design of the Wilson and Improved Wilson MOS Current Mirrors to Reach the Best Settling time.
ISCAS
Gaetano Palumbo
1994 J jnl
Double and triple charge pumps with mos diodes: Dynamic models to an optimized design.
Int. J. Circuit Theory Appl.
Giuseppe Di Cataldo, Gaetano Palumbo
1994 J jnl
Improved dynamic model of double and triple charge pumps to take current leakage into account.
Int. J. Circuit Theory Appl.
Giuseppe Di Cataldo, Gaetano Palumbo
1994 C conf
Optimized Design of 4 Stage Dickson Voltage Multiplier.
ISCAS
Giuseppe Di Cataldo, Gaetano Palumbo
1993 J jnl
New CMOS current mirrors with improved high-frequency response.
Int. J. Circuit Theory Appl.
Giuseppe Di Cataldo, Gaetano Palumbo, S. Stivala