Gabriele Saucier

81 papers A* 12A 14B 5C 8Misc 1Journal 18Unranked 22

Year	Rank	Type	Title / Venue / Authors
2002	A	`conf`	E-Design Based on the Reuse Paradigm. DATE L. Ghanmi, A. Ghrab, M. Hamdoun, B. Missaoui, K. Skiba, Gabriele Saucier
2002	A	`conf`	Who Owns the Platform? DATE Vassilios Gerousis, Oz Levia, Pierre G. Paulin, Mark Pinto, Chris Rowen, Gabriele Saucier
2000	C	`conf`	FPGA Technology Snapshot: Current Devices and Design Tools. IEEE International Workshop on Rapid System Prototyping Helena Krupnova, Gabriele Saucier
2000	B	`conf`	FPGA-Based Emulation: Industrial and Custom Prototyping Solutions. FPL Helena Krupnova, Gabriele Saucier
1999	C	`conf`	FPGA Partitioning for Rapid Prototyping: A 1 Million Gate Design Case Study. IEEE International Workshop on Rapid System Prototyping Helena Krupnova, Christian Rabedaoro, Gabriele Saucier
1999	B	`conf`	Hierarchical Interactive Approach to Partition Large Designs into FPGAs. FPL Helena Krupnova, Gabriele Saucier
1999	A	`conf`	Iterative Improvement Based Multi-Way Netlist Partitioning for FPGAs. DATE Helena Krupnova, Gabriele Saucier
1999	A	`conf`	Partitioning Large Designs by Filling PFGA Devices with Hierarchy Blocks. FPGA Helena Krupnova, Gabriele Saucier
1998	B	`conf`	A Knowledge-Based System for Prototyping on FPFAs. FPL Helena Krupnova, Vu DucAnh Dinh, Gabriele Saucier
1998	A	`conf`	Block and IP Wrapping for Efficient Design on FPGAs (Abstract). FPGA Helena Krupnova, B. Behnam, Gabriele Saucier
1998	Misc	`conf`	Fast Arithmetic on Xilinx 5200 FPGA. VLSI Design Bernard Laurent, Gilles Bosco, Gabriele Saucier
1998	C	`conf`	Real Time Prototyping Method and a Case Study. International Workshop on Rapid System Prototyping Helena Krupnova, Dinh Duc Anh Vu, Gabriele Saucier, Michel Boubal
1998	A	`conf`	Timing Driven Floorplanning on Programmable Hierarchical Targets. FPGA S. A. Senouci, Aadil Amoura, Helena Krupnova, Gabriele Saucier
1998	J	`jnl`	Using cone structures for circuit partitioning into FPGA packages. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Daniel R. Brasen, Gabriele Saucier
1997	A*	`conf`	A Hierarchy-Driven FPGA Partitioning Method. DAC Helena Krupnova, Ali Abbara, Gabriele Saucier
1997	B	`conf`	Structural versus algorithmic approaches for efficient adders on Xilinx 5200 FPGA. FPL Bernard Laurent, Gilles Bosco, Gabriele Saucier
1997	A	`conf`	Synthesis and Floorplanning for Large Hierarchical FPGAs. FPGA Helena Krupnova, Christian Rabedaoro, Gabriele Saucier
1995	—	`conf`	Design of defect-tolerant scan chains for MCMs with an active substrate. DFT P. Brahic, Régis Leveugle, Gabriele Saucier
1995	—	`conf`	Efficient synthesis of fault-tolerant controllers. ED&TC Raphaël Rochet, Régis Leveugle, Gabriele Saucier
1994	—	`conf`	Alternative Approaches to Fault Detection in FSMs. DFT Régis Leveugle, Raphaël Rochet, Gabriele Saucier
1994	A*	`conf`	Design Automation Tools for FPGA Design (Panel). DAC Kella Knack, Gordan Hyland, Jim Jasmin, John Frediani, Tom Reiner, Steven Trimberger, Gabriele Saucier
1994	—	`conf`	Design of a Digital Neural Chip: Application to Optical Character Recognition by Neural Network. EDAC-ETC-EUROASIC D. Jacquet, Gabriele Saucier
1994	—	`conf`	FPGA Partitioning for Critical Paths. EDAC-ETC-EUROASIC Daniel R. Brasen, Gabriele Saucier
1994	—	`conf`	Taking Advantage of ASICs to Improve Dependability with Very Low Overheads. EDAC-ETC-EUROASIC T. Michel, Régis Leveugle, Gabriele Saucier, R. Doucet, P. Chapier
1994	—	`conf`	Taking Advantage of High Level Functional Information to Refine Timing Analysis and Timing Modeling. EDAC-ETC-EUROASIC C. Safinia, Régis Leveugle, Gabriele Saucier
1994	J	`jnl`	The Hyeti Defect Tolerant Microprocessor: A Practical Experiment and its Cost-Effectiveness Analysis. IEEE Trans. Computers Régis Leveugle, Zahava Koren, Israel Koren, Gabriele Saucier, Norbert Wehn
1993	—	`conf`	A Synthesis Tool for Fault-Tolerant Finite State Machines. FTCS Régis Leveugle, Raphaël Rochet, Gabriele Saucier, L. Martinez, C. Pitot
1993	—	`conf`	Analysis and Comparison of Fault Tolerant FSM Architectures Based on SEC Codes. DFT Raphaël Rochet, Régis Leveugle, Gabriele Saucier
1993	—	`conf`	Design of a dedicated neural network on silicon: application to optical character recognition. VLSI D. Jacquet, Gabriele Saucier
1993	J	`jnl`	Functional versus random test generation for sequential circuits. J. Electron. Test. Margot Karam, Gabriele Saucier
1993	C	`conf`	Influence of Error Correlations on the Signature Analysis Aliasing. ICCD Régis Leveugle, X. Delord, Gabriele Saucier
1993	J	`jnl`	Input-driven partitioning methods and application to synthesis on table-lookup-based FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Pierre Abouzeid, Belgacem Babba, Michel Crastes de Paulet, Gabriele Saucier
1993	J	`jnl`	Lexicographical expressions of Boolean functions with application to multilevel synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Gabriele Saucier, Pierre Abouzeid
1993	A	`conf`	Partitioning with cone structures. ICCAD Gabriele Saucier, Daniel R. Brasen, J. P. Hiol
1993	—	`ed.`	Synthesis for Control Dominated Circuits, Selected papers from the IFIP WG10.2/WG10.5 Workshops, Grenoble, France, April and September, 1992 Synthesis for Control Dominated Circuits Gabriele Saucier, Jacques Trilhe
1992	—	`conf`	ASYL: A Control Driven RTL Synthesis System using Library Blocks. Synthesis for Control Dominated Circuits Anne Mignotte, Marie-Claude Bertrand, Michel Crastes de Paulet, Jérôme Rampon, Gabriele Saucier
1992	J	`jnl`	Automatic synthesis of large Moore sequencers. Integr. Laurent Gerbaux, Gabriele Saucier
1992	J	`jnl`	Configuring a Wafer-Scale Two-Dimensional Array of Single-Bit Processors. Computer Ahmed Boubekeur, Jean-Luc Patry, Gabriele Saucier, Jacques Trilhe
1992	—	`conf`	Logic Synthesis for Automatic Layout. Synthesis for Control Dominated Circuits Pierre Abouzeid, Régis Leveugle, Gabriele Saucier
1992	—	`conf`	Specification and Synthesis of Communicating Finite State Machines. Synthesis for Control Dominated Circuits H. Belhadj, Laurent Gerbaux, Marie-Claude Bertrand, Gabriele Saucier
1992	—	`conf`	Synthesis of large controllers using ROM or PLA generators. Synthesis for Control Dominated Circuits Laurent Gerbaux, Régis Leveugle, Gabriele Saucier
1992	C	`conf`	Synthesis on Multiplexer-Based F.P.G.A. Using Binary Decision Diagrams. ICCD T. Besson, H. Bouzouzou, M. Crastes, Ion Floricica, Gabriele Saucier
1991	—	`conf`	A Customizable Neural Processor for Distributed Neural Network. VLSI J. Quali, Gabriele Saucier, P. Y. Alla, Jacques Trilhe, Laurent Masse-Navette
1991	—	`conf`	A New Approach to Control Flow Checking Without Program Modification. FTCS T. Michel, Régis Leveugle, Gabriele Saucier
1991	A*	`conf`	A Technology Mapping Method Based On Perfect And Semi-Perfect Matchings. DAC M. Crastes, K. Sakouti, Gabriele Saucier
1991	J	`jnl`	A reconfigurable wafer-scale memory. IEEE J. Solid State Circuits Ahmed Boubekeur, Gabriele Saucier, Jacques Trilhe
1991	A	`conf`	Formalizing Signature Analysis for Control Flow Checking of Pipelined RISC Multiprocessors. ITC X. Delord, Gabriele Saucier
1991	A	`conf`	Hierarchical Test Generation Based on Delayed Propagation. ITC Margot Karam, Régis Leveugle, Gabriele Saucier
1991	A	`conf`	State Assignment Based on the Reduced Dependency Theory and Recent Experimental Results. ICCAD Christopher Duff, Gabriele Saucier
1990	—	`conf`	Design of microprocessors with built-in on-line test. FTCS Régis Leveugle, T. Michel, Gabriele Saucier
1990	—	`conf`	Multi-level synthesis on PALs. EURO-DAC Gabriele Saucier, Pascal Sicard, Laurent Bouchet
1990	A*	`conf`	Multilevel Synthesis Minimizing the Routing Factor. DAC Pierre Abouzeid, K. Sakouti, Gabriele Saucier, Franck Poirot
1990	J	`jnl`	Optimized Synthesis of Concurrently Checked Controllers. IEEE Trans. Computers Régis Leveugle, Gabriele Saucier
1990	B	`conf`	Silicon compiler for neuro-ASICs. IJCNN J. Ouali, Gabriele Saucier
1990	—	`conf`	State assignment of controllers for optimal area implementation. EURO-DAC Gabriele Saucier, Christopher Duff, Franck Poirot
1989	C	`conf`	A channelless layout for multilevel synthesis with compiled cells. ICCD Gabriele Saucier, Régis Leveugle, Pierre Abouzeid
1989	C	`conf`	A flexible architecture for neural networks. ICCD J. Ouali, Gabriele Saucier
1989	C	`conf`	Concurrent checking in dedicated controllers. ICCD Régis Leveugle, Gabriele Saucier
1989	A	`conf`	Optimized Synthesis of Dedicated Controllers with Concurrent Checking Capabilities. ITC Régis Leveugle, Gabriele Saucier
1989	A*	`conf`	State Assignment Using a New Embedding Method Based on an Intersecting Cube Theory. DAC Gabriele Saucier, Christopher Duff, Franck Poirot
1989	A	`conf`	Testability Expertise and Test Planning from High-Level Specifications. ITC Michel Crastes de Paulet, Margot Karam, Gabriele Saucier
1988	—	`conf`	Entwurf eines systolischen Arrays in Wafer Scale Technik für die digitale Signalverarbeitung. GI Jahrestagung (2) Manfred Glesner, M. Huch, Peter A. Ivey, T. Midwinter, Gabriele Saucier, Jacques Trilhe
1988	J	`jnl`	Optimized Layout of MOS Cells. IEEE Trans. Computers Ghislaine Thuau, Gabriele Saucier
1987	J	`jnl`	ASYL: A Rule-Based System for Controller Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Gabriele Saucier, Michel Crastes de Paulet, Pascal Sicard
1987	A*	`conf`	An Application of Exploratory Data Analysis Techniques to Floorplan Design. DAC E. F. M. Kouka, Gabriele Saucier
1986	—	`conf`	A Rule-Based System for the Optimal State Assignment of Controllers. FJCC E. Dupont, Jeanne Idt, Gabriele Saucier
1985	A*	`conf`	Systematic and optimized layout of MOS cells. DAC Gabriele Saucier, Ghislaine Thuau
1984	A	`conf`	CADOC : A System for Computer Aided Functional Test. ITC Catherine Bellon, Gabriele Saucier
1984	J	`jnl`	Design synthesis in VLSI and software engineering. J. Syst. Softw. Robert Cuykendall, Antun Domic, William H. Joyner, Stephen C. Johnson, Steven H. Kelem, Dennis McBride, Jack Mostow, John E. Savage, Gabriele Saucier
1984	A*	`conf`	VLSI test expertise system using a control flow model. DAC Gabriele Saucier, Catherine Bellon
1982	A*	`conf`	Automatic generation of microprocessor test programs. DAC Catherine Bellon, A. Liothin, Sylvain Sadier, Gabriele Saucier, Raoul Velazco, Francois Grillot, M. Issenman
1982	J	`jnl`	Protection Against External Errors in a Dedicated System. IEEE Trans. Computers Catherine Bellon, Gabriele Saucier
1982	A*	`conf`	Top down design and testability of VLSI circuits. DAC Philippe Basset, Gabriele Saucier
1981	A*	`conf`	Hardware description levels and test for complex circuits. DAC Catherine Bellon, Gabriele Saucier, José-Maria Gobbi
1978	J	`jnl`	Dynamic Testing of Control Units. IEEE Trans. Computers Chantal Robach, Gabriele Saucier
1976	A*	`conf`	A Design Tool for the Multilevel Description and Simulation of Systems of Interconnected Modules. ISCA M. Moalla, Gabriele Saucier, Joseph Sifakis, Marianthi Zachariades
1976	J	`jnl`	Processor Testability and Design Consequences. IEEE Trans. Computers Chantal Robach, Gabriele Saucier, J. Lebrun
1975	J	`jnl`	Diversified Test Methods for Local Control Units. IEEE Trans. Computers Chantal Robach, Gabriele Saucier
1975	—	`conf`	On balancing hardware-firmware for designing a fault-tolerant computers' series. MICRO (2) Bernard Courtois, Gabriele Saucier
1972	J	`jnl`	Next-State Equations of Asynchronous Sequential Machines. IEEE Trans. Computers Gabriele Saucier
1972	J	`jnl`	State Assignment of Asynchronous Sequential Machines Using Graph Techniques. IEEE Trans. Computers Gabriele Saucier