Gabriele Manganaro

42 papers C 3Journal 26Unranked 13
YearRankTypeTitle / Venue / Authors
2025 — conf
24.6 A Power- and Area-Efficient 4nm Self-Calibrated 12b/16GS/s Hierarchical Time-Interleaving ADC.
ISSCC
Cheng-En Hsieh, Gabriele Manganaro, Sheng-Hui Liao, Jack Weng, Tsun-Yuan Fan, Alec Chin, Tsung-Chih Hung, Jonathan X. Wu, Chi-Lun Lo, Andy Pan, Ming-Hang Hsieh, Yun-Shiang Shu, Wei-Hsin Tseng, Kuan-Dar Chen
2024 — conf
A 16GS/s 10b Time-domain ADC using Pipelined-SAR TDC with Delay Variability Compensation and Background Calibration Achieving 153.8dB FoM in 4nm CMOS.
VLSI Technology and Circuits
Juzheng Liu, Ayman Shabra, Stacy Ho, Gabriele Manganaro, Mike Shuo-Wei Chen
2024 J jnl
A 6.4-GS/s 1-GHz BW Continuous-Time Pipelined ADC With Time-Interleaved Sub-ADC-DAC Achieving 61.7-dB SNDR in 16-nm FinFET.
IEEE J. Solid State Circuits
Rishabh Mittal, Hajime Shibata, Sharvil Patil, Erik Krommenhoek, Prawal Shrestha, Gabriele Manganaro, Anantha P. Chandrakasan, Hae-Seung Lee
2024 J jnl
Inaugural Issue of the IEEE Transactions on Circuits and Systems for Artificial Intelligence.
IEEE Trans. Circuits Syst. Artif. Intell.
Yiran Chen, Gabriele Manganaro, Manuel Delgado-Restituto
2023 — conf
A 14b 16GS/s Time-Interleaving Oirect-RF Synthesis OAe with T-OEM Achieving -70dBc IM3 up to 7.8GHz in 7nm.
ISSCC
Wei-Hsin Tseng, Willy Lin, Chung-Wei Hsu, Chang-Yang Huang, Yu-Sian Lin, Hung-Yi Huang, HsinWei Chen, Sheng-Hui Liao, Kuan-Dar Chen, Jon Strange, Gabriele Manganaro
2023 — conf
A 6.4-GS/s 1-GHz BW Continuous-Time Pipelined ADC with Time-Interleaved Sub-ADC-DAC Achieving 61.7-dB SNDR in 16-nm FinFET.
VLSI Technology and Circuits
Rishabh Mittal, Hajime Shibata, Sharvil Patil, Erik Krommenhoek, Prawal Shrestha, Gabriele Manganaro, Anantha P. Chandrakasan, Hae-Seung Lee
2023 J jnl
Generalized Sampling-Based Multi-Channel Sampling of Signals Realized With Pure Delay Analog Filters and Digital FIR Reconstruction Filters.
IEEE Trans. Circuits Syst. II Express Briefs
Bibhudatta Sahoo, Gabriele Manganaro
2023 J jnl
New Year Editorial 2023.
IEEE Open J. Circuits Syst.
Gabriele Manganaro, Nicole McFarlane
2022 — conf
A 30GHz-BW < -57dB-IM3 Direct RF Receiver Analog Front End in 16nm FinFET.
VLSI Technology and Circuits
Athanasios Ramkaj, Adalberto Cantoni, Gabriele Manganaro, Siddharth Devarajan, Michiel Steyaert, Filip Tavernier
2022 J jnl
Editorial: Where Are We Now and Where Do We Go From Here.
IEEE Open J. Circuits Syst.
Gabriele Manganaro
2021 J jnl
Editorial on the Special Section on the 2021 IEEE International Symposium on Integrated Circuits and Systems.
IEEE Open J. Circuits Syst.
Gabriele Manganaro
2021 J jnl
New Year Editorial.
IEEE Open J. Circuits Syst.
Gabriele Manganaro
2020 J jnl
Inaugural Issue of the IEEE Open Journal of Circuits and Systems: Welcome Note.
IEEE Open J. Circuits Syst.
Gabriele Manganaro
2018 — conf
Emerging data converter architectures and techniques.
CICC
Gabriele Manganaro
2018 C conf
In-situ nonlinear calibration of a RF signal chain.
ISCAS
Nevena Rakuljic, Carroll Speir, Eric Otte, Jeff Bray, Corey Petersen, Gabriele Manganaro
2017 J jnl
A 12-b 10-GS/s Interleaved Pipeline ADC in 28-nm CMOS Technology.
IEEE J. Solid State Circuits
Siddharth Devarajan, Larry Singer, Dan Kelly, Tao Pan, José B. Silva, Janet Brunsilius, Daniel Rey-Losada, Frank Murden, Carroll Speir, Jeff Bray, Eric Otte, Nevena Rakuljic, Phil Brown, Todd Weigandt, Qicheng Yu, Donald Paterson, Corey Petersen, Jeffrey C. Gealow, Gabriele Manganaro
2014 J jnl
A 12 mW Low Power Continuous-Time Bandpass ΔΣ Modulator With 58 dB SNDR and 24 MHz Bandwidth at 200 MHz IF.
IEEE J. Solid State Circuits
Hyungil Chae, Jaehun Jeong, Gabriele Manganaro, Michael P. Flynn
2013 J jnl
Outgoing Editorial.
IEEE Trans. Circuits Syst. I Regul. Pap.
Gabriele Manganaro
2013 J jnl
Progress update and a look ahead.
IEEE Trans. Circuits Syst. I Regul. Pap.
Gabriele Manganaro
2012 — conf
A 12mW low-power continuous-time bandpass ΔΣ modulator with 58dB SNDR and 24MHz bandwidth at 200MHz IF.
ISSCC
Hyungil Chae, Jaehun Jeong, Gabriele Manganaro, Michael P. Flynn
2012 J jnl
Guest Editorial Special Issue on ISCAS 2011.
IEEE Trans. Circuits Syst. I Regul. Pap.
Tor Sverre Lande, Peter T. J. Liang, Gabriele Manganaro, Eduardo A. B. da Silva, Aleksandar Tasic
2012 J jnl
Incoming Editorial.
IEEE Trans. Circuits Syst. I Regul. Pap.
Gabriele Manganaro
2011 — conf
Advanced transmitters for wireless infrastructure.
ISSCC
Gabriele Manganaro, Domine Leenaerts, Francesco Dantoni, Andrea Baschirotto, Robert Bogdan Staszewski, Nikolaus Klemmer, Seongchol Hong
2011 J jnl
Guest Editorial Special Issue on ISCAS 2010.
IEEE Trans. Circuits Syst. I Regul. Pap.
Maged Ghoneima, Yong Lian, Gabriele Manganaro, Shahriar Mirabbasi, Christian Piguet, Wouter A. Serdijn
2011 J jnl
Guest Editorial Special Section on 2010 IEEE Custom Integrated Circuits Conference (CICC 2010).
IEEE Trans. Circuits Syst. I Regul. Pap.
Mohab Anis, Howard C. Luong, Gabriele Manganaro
2010 J jnl
Guest Editorial Special Section on 2009 IEEE Custom Integrated Circuits Conference.
IEEE Trans. Circuits Syst. I Regul. Pap.
Shahriar Mirabbasi, John W. M. Rogers, Gabriele Manganaro
2010 J jnl
Guest Editorial Special Section on 2009 IEEE System-on-Chip Conference.
IEEE Trans. Circuits Syst. I Regul. Pap.
Andrew Marshall, Sakir Sezer, Gabriele Manganaro
2008 J jnl
40 MHz IF 1 MHz Bandwidth Two-Path Bandpass ΣΔ Modulator With 72 dB DR Consuming 16 mW.
IEEE J. Solid State Circuits
Ivano Galdi, Edoardo Bonizzoni, Piero Malcovati, Gabriele Manganaro, Franco Maloberti
2008 J jnl
A 14-b 100-MS/s Pipelined ADC With a Merged SHA and First MDAC.
IEEE J. Solid State Circuits
Byung Geun Lee, Byung-Moo Min, Gabriele Manganaro, Jonathan W. Valvano
2008 — conf
A 14b 100MS/s Pipelined ADC with a Merged Active S/H and First MDAC.
ISSCC
Byung Geun Lee, Byung-Moo Min, Gabriele Manganaro, Jonathan W. Valvano
2007 — conf
A 1.8V 10b 210MS/s CMOS Pipelined ADC Featuring 86dB SFDR without Calibration.
CICC
J. Li, Robert Leboeuf, Matthew Courcy, Gabriele Manganaro
2007 — conf
Two-path band-pass Δ∑ modulator with 40-MHz IF 72-dB DR at 1-MHz bandwidth consuming 16 mW.
ESSCIRC
Ivano Galdi, Edoardo Bonizzoni, Franco Maloberti, Gabriele Manganaro, Piero Malcovati
2004 J jnl
A dual 10-b 200-MSPS pipelined D/A converter with DLL-based clock synthesizer.
IEEE J. Solid State Circuits
Gabriele Manganaro, Sung-Ung Kwak, Alex R. Bugeja
2003 J jnl
A behavioral modeling approach to the design of a low jitter clock source.
IEEE Trans. Circuits Syst. II Express Briefs
Gabriele Manganaro, Sung-Ung Kwak, SeongHwan Cho, Anurag Pulincherry
2003 — conf
A dual 10b 200MSPS pipeline D/A converter with DLL-based clock synthesizer.
CICC
Gabriele Manganaro, Sung-Ung Kwak, Alex R. Bugeja
2001 — conf
An improved phase clock generator for interleaved and double-sampled switched-capacitor circuits.
ICECS
Gabriele Manganaro
2000 C conf
A triple 8b, 80MSPS 3.3 V graphics digitizer.
ISCAS
Irfan A. Chaudrhry, Sung-Ung Kwak, Gabriele Manganaro, Maher Sarraj, T. Lakshmi Viswanathan
2000 J jnl
Nonlinear Computability Based on Chaos.
Int. J. Bifurc. Chaos
Gabriele Manganaro, José Pineda de Gyvez
1997 J jnl
Cellular neural networks to explore complexity.
Soft Comput.
Paolo Arena, Riccardo Caponetto, Luigi Fortuna, Gabriele Manganaro
1997 C conf
DNA computing based on chaos.
ICEC
Gabriele Manganaro, José Pineda de Gyvez
1996 J jnl
Generation of n-double scrolls via cellular neural networks.
Int. J. Circuit Theory Appl.
Paolo Arena, Salvatore Baglio, Luigi Fortuna, Gabriele Manganaro
1995 J jnl
Complexity in an Industrial flyback converter.
J. Circuits Syst. Comput.
Salvatore Baglio, Luigi Fortuna, Gabriele Manganaro, Rosario Cristaudo