Gabriel Rodriguez-Canal

18 papers A 2B 1Journal 9Unranked 6
YearRankTypeTitle / Venue / Authors
2026 A conf
Towards Scheduling of Pipelined Dataflow Graphs in MLIR.
FPGA
Gabriel Rodriguez-Canal, Nicolas Bohm Agostini, Ankur Limaye, Vito Giovanni Castellana, Joseph B. Manzano, Antonino Tumeo, Maurice Jamieson, Nick Brown
2025 — conf
An MLIR pipeline for offloading Fortran to FPGAs via OpenMP.
SC Workshops
Gabriel Rodriguez-Canal, David Katz, Nick Brown
2025 J jnl
An MLIR pipeline for offloading Fortran to FPGAs via OpenMP.
CoRR
Gabriel Rodriguez-Canal, David Katz, Nick Brown
2025 — conf
Programmer productivity and performance on AMD's AI Engines: Offloading Fortran intrinsics via MLIR a case-study.
SC Workshops
Nick Brown, Gabriel Rodriguez-Canal
2025 A conf
Seamless Acceleration of Fortran Intrinsics via AMD AI Engines.
FPGA
Nick Brown, Gabriel Rodriguez-Canal
2025 J jnl
Seamless acceleration of Fortran intrinsics via AMD AI engines.
CoRR
Nick Brown, Gabriel Rodriguez-Canal
2024 — conf
A shared compilation stack for distributed-memory parallelism in stencil DSLs.
ASPLOS (3)
George Bisbas, Anton Lydike, Emilien Bauer, Nick Brown, Mathieu Fehr, Lawrence Mitchell, Gabriel Rodriguez-Canal, Maurice Jamieson, Paul H. J. Kelly, Michel Steuwer, Tobias Grosser
2024 J jnl
A shared compilation stack for distributed-memory parallelism in stencil DSLs.
CoRR
George Bisbas, Anton Lydike, Emilien Bauer, Nick Brown, Mathieu Fehr, Lawrence Mitchell, Gabriel Rodriguez-Canal, Maurice Jamieson, Paul H. J. Kelly, Michel Steuwer, Tobias Grosser
2023 B conf
Fortran High-Level Synthesis: Reducing the Barriers to Accelerating HPC Codes on FPGAs.
FPL
Gabriel Rodriguez-Canal, Nick Brown, Tim Dykes, Jessica R. Jones, Utz-Uwe Haus
2023 J jnl
Fortran High-Level Synthesis: Reducing the barriers to accelerating HPC codes on FPGAs.
CoRR
Gabriel Rodriguez-Canal, Nick Brown, Tim Dykes, Jessica R. Jones, Utz-Uwe Haus
2023 — conf
Stencil-HMLS: A multi-layered approach to the automatic optimisation of stencil codes on FPGA.
SC Workshops
Gabriel Rodriguez-Canal, Nick Brown, Maurice Jamieson, Emilien Bauer, Anton Lydike, Tobias Grosser
2023 J jnl
Stencil-HMLS: A multi-layered approach to the automatic optimisation of stencil codes on FPGA.
CoRR
Gabriel Rodriguez-Canal, Nick Brown, Maurice Jamieson, Emilien Bauer, Anton Lydike, Tobias Grosser
2023 J jnl
Task-based preemptive scheduling on FPGAs leveraging partial reconfiguration.
Concurr. Comput. Pract. Exp.
Gabriel Rodriguez-Canal, Nick Brown, Yuri Torres, Arturo González-Escribano
2023 J jnl
Task-based preemptive scheduling on FPGAs leveraging partial reconfiguration.
CoRR
Gabriel Rodriguez-Canal, Nick Brown, Yuri Torres, Arturo González-Escribano
2022 — conf
FPGAs in Supercomputers: Performance Through Dataflow Programming and Flexibility.
Euro-Par Workshops
Gabriel Rodriguez-Canal
2022 — conf
Programming Abstractions for Preemptive Scheduling on FPGAs Using Partial Reconfiguration.
Euro-Par Workshops
Gabriel Rodriguez-Canal, Nick Brown, Yuri Torres, Arturo González-Escribano
2022 J jnl
Programming abstractions for preemptive scheduling in FPGAs using partial reconfiguration.
CoRR
Gabriel Rodriguez-Canal, Nick Brown, Yuri Torres, Arturo González-Escribano
2021 J jnl
Efficient heterogeneous programming with FPGAs using the Controller model.
J. Supercomput.
Gabriel Rodriguez-Canal, Yuri Torres, Francisco J. Andújar, Arturo González-Escribano