Gabriel H. Loh

129 papers A* 45A 10B 11C 8Misc 1Journal 32Unranked 22

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	Cloud-Hardware Co-Design for Memory Bandwidth-Bound HPC Workloads: Performance and Characteristics of Azure HBv5 Virtual Machines. SCA/HPC Asia Amirreza Rastegari, Sai Kovouri, Michael Cui, Zehra Naz, Jay Fleischman, Saurabh Gupta, Anil Harwani, Gabriel H. Loh, Joe Greenseid, Evan Burness, Prabhat Ram, Michael F. Ringenburg
2025	J	`jnl`	Interconnect Design for Heterogeneous Integration of Chiplets in the AMD Instinct MI300X Accelerator. IEEE Micro Alan Smith, Gabriel H. Loh, Samuel Naffziger, John J. Wuu, Nathan Kalyanasundharam, Eric Chapman, Raja Swaminathan, Tyrone Huang, Wonjun Jung, Alexander Kaganov, Hugh McIntyre, Ramon Mangaser
2025	—	`conf`	Load and MLP-Aware Thread Orchestration for Recommendation Systems Inference on CPUs. ASPLOS (2) Rishabh Jain, Teyuh Chou, Onur Kayiran, John Kalamatianos, Gabriel H. Loh, Mahmut T. Kandemir, Chita R. Das
2024	—	`conf`	AMD Instinct™ MI300X Accelerator: Packaging and Architecture Co-Optimization. VLSI Technology and Circuits Alan Smith, Gabriel H. Loh, John J. Wuu, Samuel Naffziger, Tyrone Huang, Hugh McIntyre, Ramon Mangaser, Wonjun Jung, Raja Swaminathan
2024	A*	`conf`	Realizing the AMD Exascale Heterogeneous Processor Vision : Industry Product. ISCA Alan Smith, Gabriel H. Loh, Michael J. Schulte, Mike Ignatowski, Samuel Naffziger, Mike Mantor, Nathan Kalyanasundharam, Vamsi Alla, Nicholas Malaya, Joseph L. Greathouse, Eric Chapman, Raja Swaminathan
2023	A*	`conf`	A Research Retrospective on AMD's Exascale Computing Journey. ISCA Gabriel H. Loh, Michael J. Schulte, Mike Ignatowski, Vignesh Adhinarayanan, Shaizeen Aga, Derrick Aguren, Varun Agrawal, Ashwin M. Aji, Johnathan Alsop, Paul T. Bauman, Bradford M. Beckmann, Majed Valad Beigi, Sergey Blagodurov, Travis Boraten, Michael Boyer, William C. Brantley, Noel Chalmers, Shaoming Chen, Kevin Cheng, Michael L. Chu, David Cownie, Nicholas Curtis, Joris Del Pino, Nam Duong, Alexandru Dutu, Yasuko Eckert, Christopher Erb, Chip Freitag, Joseph L. Greathouse, Sudhanva Gurumurthi, Anthony Gutierrez, Khaled Hamidouche, Sachin Hossamani, Wei Huang, Mahzabeen Islam, Nuwan Jayasena, John Kalamatianos, Onur Kayiran, Jagadish Kotra, Alan Lee, Daniel Lowell, Niti Madan, Abhinandan Majumdar, Nicholas Malaya, Srilatha Manne, Susumu Mashimo, Damon McDougall, Elliot Mednick, Michael Mishkin, Mark Nutter, Indrani Paul, Matthew Poremba, Brandon Potter, Kishore Punniyamurthy, Sooraj Puthoor, Steven E. Raasch, Karthik Rao, Gregory Rodgers, Marko Scrbak, Mohammad Seyedzadeh, John Slice, Vilas Sridharan, René van Oostrum, Eric Van Tassell, Abhinav Vishnu, Samuel Wasmundt, Mark Wilkening, Noah Wolfe, Mark Wyse, Adithya Yalavarti, Dmitri Yudanov
2023	—	`conf`	AMD Instinct VLSI Technology and Circuits Raja Swaminathan, Michael J. Schulte, Brett Wilkerson, Gabriel H. Loh, Alan Smith, Norman James
2023	A	`conf`	The Next Era for Chiplet Innovation. DATE Gabriel H. Loh, Raja Swaminathan
2021	—	`conf`	A New Era of Tailored Computing. VLSI Circuits Mark Papermaster, Stephen Kosonocky, Gabriel H. Loh, Samuel Naffziger
2021	J	`jnl`	Accelerating Variational Quantum Algorithms Using Circuit Concurrency. CoRR Salonik Resch, Anthony Gutierrez, Joon Suk Huh, Srikant Bharadwaj, Yasuko Eckert, Gabriel H. Loh, Mark Oskin, Swamit S. Tannu
2021	A*	`conf`	Analyzing and Leveraging Decoupled L1 Caches in GPUs. HPCA Mohamed Assem Ibrahim, Onur Kayiran, Yasuko Eckert, Gabriel H. Loh, Adwait Jog
2021	A*	`conf`	Increasing GPU Translation Reach by Leveraging Under-Utilized On-Chip Resources. MICRO Jagadish B. Kotra, Michael LeBeane, Mahmut T. Kandemir, Gabriel H. Loh
2021	A*	`conf`	Pioneering Chiplet Technology and Design for the AMD EPYC™ and Ryzen™ Processor Families : Industrial Product. ISCA Samuel Naffziger, Noah Beck, Thomas Burd, Kevin Lepak, Gabriel H. Loh, Mahesh Subramony, Sean White
2021	A	`conf`	Understanding Chiplets Today to Anticipate Future Integration Opportunities and Limits. DATE Gabriel H. Loh, Samuel Naffziger, Kevin Lepak
2020	B	`conf`	Analyzing and Leveraging Shared L1 Caches in GPUs. PACT Mohamed Assem Ibrahim, Onur Kayiran, Yasuko Eckert, Gabriel H. Loh, Adwait Jog
2020	A*	`conf`	Experiences with ML-Driven Design: A NoC Case Study. HPCA Jieming Yin, Subhash Sethumurugan, Yasuko Eckert, Chintan Patel, Alan Smith, Eric Morton, Mark Oskin, Natalie D. Enright Jerger, Gabriel H. Loh
2019	A*	`conf`	Efficient System Architecture in the Era of Monolithic 3D: Dynamic Inter-tier Interconnect and Processing-in-Memory. DAC Dylan C. Stow, Itir Akgun, Wenqin Huangfu, Yuan Xie, Xueqi Li, Gabriel H. Loh
2018	J	`jnl`	CODA: Enabling Co-location of Computation and Data for Multiple GPU Systems. ACM Trans. Archit. Code Optim. Hyojong Kim, Ramyad Hadidi, Lifeng Nai, Hyesoon Kim, Nuwan Jayasena, Yasuko Eckert, Onur Kayiran, Gabriel H. Loh
2018	—	`conf`	Challenges of High-Capacity DRAM Stacks and Potential Directions. MCHPC@SC Amin Farmahini Farahani, Sudhanva Gurumurthi, Gabriel H. Loh, Michael Ignatowski
2018	A*	`conf`	Generic System Calls for GPUs. ISCA Ján Veselý, Arkaprava Basu, Abhishek Bhattacharjee, Gabriel H. Loh, Mark Oskin, Steven K. Reinhardt
2018	J	`jnl`	High-Performance and Energy-Effcient Memory Scheduler Design for Heterogeneous Systems. CoRR Rachata Ausavarungnirun, Gabriel H. Loh, Lavanya Subramanian, Kevin K. Chang, Onur Mutlu
2018	J	`jnl`	Holistic Management of the GPGPU Memory Hierarchy to Manage Warp-level Latency Tolerance. CoRR Rachata Ausavarungnirun, Saugata Ghose, Onur Kayiran, Gabriel H. Loh, Chita R. Das, Mahmut T. Kandemir, Onur Mutlu
2018	A	`conf`	Machine learning for performance and power modeling of heterogeneous systems. ICCAD Joseph L. Greathouse, Gabriel H. Loh
2018	A*	`conf`	Modular Routing Design for Chiplet-Based Systems. ISCA Jieming Yin, Zhifeng Lin, Onur Kayiran, Matthew Poremba, Muhammad Shoaib Bin Altaf, Natalie D. Enright Jerger, Gabriel H. Loh
2018	A*	`conf`	Scheduling Page Table Walks for Irregular GPU Applications. ISCA Seunghee Shin, Guilherme Cox, Mark Oskin, Gabriel H. Loh, Yan Solihin, Abhishek Bhattacharjee, Arkaprava Basu
2017	B	`conf`	Avoiding TLB Shootdowns Through Self-Invalidating TLB Entries. PACT Amro Awad, Arkaprava Basu, Sergey Blagodurov, Yan Solihin, Gabriel H. Loh
2017	J	`jnl`	CODA: Enabling Co-location of Computation and Data for Near-Data Processing. CoRR Hyojong Kim, Ramyad Hadidi, Lifeng Nai, Hyesoon Kim, Nuwan Jayasena, Yasuko Eckert, Onur Kayiran, Gabriel H. Loh
2017	A	`conf`	Cost-effective design of scalable high-performance systems using active and passive interposers. ICCAD Dylan C. Stow, Yuan Xie, Taniya Siddiqua, Gabriel H. Loh
2017	A*	`conf`	Design and Analysis of an APU for Exascale Computing. HPCA Thiruvengadam Vijayaraghavan, Yasuko Eckert, Gabriel H. Loh, Michael J. Schulte, Mike Ignatowski, Bradford M. Beckmann, William C. Brantley, Joseph L. Greathouse, Wei Huang, Arun Karunanithi, Onur Kayiran, Mitesh R. Meswani, Indrani Paul, Matthew Poremba, Steven Raasch, Steven K. Reinhardt, Greg Sadowski, Vilas Sridharan
2017	J	`jnl`	GPU System Calls. CoRR Ján Veselý, Arkaprava Basu, Abhishek Bhattacharjee, Gabriel H. Loh, Mark Oskin, Steven K. Reinhardt
2017	A	`conf`	Leveraging near data processing for high-performance checkpoint/restart. SC Abhinav Agrawal, Gabriel H. Loh, James Tuck
2017	A*	`conf`	MemPod: A Clustered Architecture for Efficient and Scalable Migration in Flat Address Space Multi-level Memories. HPCA Andreas Prodromou, Mitesh R. Meswani, Nuwan Jayasena, Gabriel H. Loh, Dean M. Tullsen
2017	A*	`conf`	There and Back Again: Optimizing the Interconnect in Networks of Memory Cubes. ISCA Matthew Poremba, Itir Akgun, Jieming Yin, Onur Kayiran, Yuan Xie, Gabriel H. Loh
2016	J	`jnl`	A case for hierarchical rings with deflection routing: An energy-efficient on-chip communication substrate. Parallel Comput. Rachata Ausavarungnirun, Chris Fallin, Xiangyao Yu, Kevin Kai-Wei Chang, Greg Nazario, Reetuparna Das, Gabriel H. Loh, Onur Mutlu
2016	J	`jnl`	Achieving both High Energy Efficiency and High Performance in On-Chip Communication using Hierarchical Rings with Deflection Routing. CoRR Rachata Ausavarungnirun, Chris Fallin, Xiangyao Yu, Kevin Kai-Wei Chang, Greg Nazario, Reetuparna Das, Gabriel H. Loh, Onur Mutlu
2016	C	`conf`	Building a Low Latency, Highly Associative DRAM Cache with the Buffered Way Predictor. SBAC-PAD Zhe Wang, Daniel A. Jiménez, Tao Zhang, Gabriel H. Loh, Yuan Xie
2016	A*	`conf`	Efficient synthetic traffic models for large, complex SoCs. HPCA Jieming Yin, Onur Kayiran, Matthew Poremba, Natalie D. Enright Jerger, Gabriel H. Loh
2016	J	`jnl`	Enabling Efficient Dynamic Resizing of Large DRAM Caches via A Hardware Consistent Hashing Mechanism. CoRR Kevin Kai-Wei Chang, Gabriel H. Loh, Mithuna Thottethodi, Yasuko Eckert, Mike O'Connor, Srilatha Manne, Lisa Hsu, Lavanya Subramanian, Onur Mutlu
2016	J	`jnl`	Exploiting Interposer Technologies to Disintegrate and Reintegrate Multicore Processors. IEEE Micro Ajaykumar Kannan, Natalie D. Enright Jerger, Gabriel H. Loh
2016	A*	`conf`	OSCAR: Orchestrating STT-RAM cache traffic for heterogeneous CPU-GPU architectures. MICRO Jia Zhan, Onur Kayiran, Gabriel H. Loh, Chita R. Das, Yuan Xie
2016	B	`conf`	Observations and opportunities in architecting shared virtual memory for heterogeneous systems. ISPASS Ján Veselý, Arkaprava Basu, Mark Oskin, Gabriel H. Loh, Abhishek Bhattacharjee
2016	B	`conf`	μC-States: Fine-grained GPU Datapath Power Management. PACT Onur Kayiran, Adwait Jog, Ashutosh Pattnaik, Rachata Ausavarungnirun, Xulong Tang, Mahmut T. Kandemir, Gabriel H. Loh, Onur Mutlu, Chita R. Das
2015	B	`conf`	A Software-Managed Approach to Die-Stacked DRAM. PACT Mark Oskin, Gabriel H. Loh
2015	J	`jnl`	Achieving Exascale Capabilities through Heterogeneous Computing. IEEE Micro Michael J. Schulte, Mike Ignatowski, Gabriel H. Loh, Bradford M. Beckmann, William C. Brantley, Sudhanva Gurumurthi, Nuwan Jayasena, Indrani Paul, Steven K. Reinhardt, Gregory Rodgers
2015	J	`jnl`	Design and Analysis of 3D-MAPS (3D Massively Parallel Processor with Stacked Memory). IEEE Trans. Computers Daehyun Kim, Krit Athikulwongse, Michael B. Healy, Mohammad M. Hossain, Moongon Jung, Ilya Khorosh, Gokul Kumar, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Shreepad Panth, Mohit Pathak, Minzhen Ren, Guanhao Shen, Taigon Song, Dong Hyuk Woo, Xin Zhao, Joungho Kim, Ho Choi, Gabriel H. Loh, Hsien-Hsin S. Lee, Sung Kyu Lim
2015	A*	`conf`	Enabling interposer-based disintegration of multi-core processors. MICRO Ajaykumar Kannan, Natalie D. Enright Jerger, Gabriel H. Loh
2015	B	`conf`	Exploiting Inter-Warp Heterogeneity to Improve GPGPU Performance. PACT Rachata Ausavarungnirun, Saugata Ghose, Onur Kayiran, Gabriel H. Loh, Chita R. Das, Mahmut T. Kandemir, Onur Mutlu
2015	A*	`conf`	Heterogeneous memory architectures: A HW/SW approach for mixing die-stacked and off-package memories. HPCA Mitesh R. Meswani, Sergey Blagodurov, David Roberts, John Slice, Mike Ignatowski, Gabriel H. Loh
2015	—	`conf`	HpMC: An Energy-aware Management System of Multi-level Memory Architectures. MEMSYS Chun-Yi Su, David Roberts, Edgar A. León, Kirk W. Cameron, Bronis R. de Supinski, Gabriel H. Loh, Dimitrios S. Nikolopoulos
2015	—	`conf`	Interconnect-Memory Challenges for Multi-chip, Silicon Interposer Systems. MEMSYS Gabriel H. Loh, Natalie D. Enright Jerger, Ajaykumar Kannan, Yasuko Eckert
2015	A*	`conf`	Large pages and lightweight memory management in virtualized environments: can you have it both ways? MICRO Binh Pham, Ján Veselý, Gabriel H. Loh, Abhishek Bhattacharjee
2014	J	`jnl`	A Configurable and Strong RAS Solution for Die-Stacked DRAM Caches. IEEE Micro Jaewoong Sim, Gabriel H. Loh, Vilas Sridharan, Mike O'Connor
2014	C	`conf`	Design and Evaluation of Hierarchical Rings with Deflection Routing. SBAC-PAD Rachata Ausavarungnirun, Chris Fallin, Xiangyao Yu, Kevin Kai-Wei Chang, Greg Nazario, Reetuparna Das, Gabriel H. Loh, Onur Mutlu
2014	A	`conf`	Efficient RAS support for die-stacked DRAM. ITC Hyeran Jeon, Gabriel H. Loh, Murali Annavaram
2014	A*	`conf`	Increasing TLB reach by exploiting clustering in page translations. HPCA Binh Pham, Abhishek Bhattacharjee, Yasuko Eckert, Gabriel H. Loh
2014	A	`conf`	Last-level cache deduplication. ICS Yingying Tian, Samira Manabi Khan, Daniel A. Jiménez, Gabriel H. Loh
2014	A	`conf`	Managing DRAM Latency Divergence in Irregular GPGPU Applications. SC Niladrish Chatterjee, Mike O'Connor, Gabriel H. Loh, Nuwan Jayasena, Rajeev Balasubramonian
2014	A*	`conf`	Managing GPU Concurrency in Heterogeneous Architectures. MICRO Onur Kayiran, Nachiappan Chidambaram Nachiappan, Adwait Jog, Rachata Ausavarungnirun, Mahmut T. Kandemir, Gabriel H. Loh, Onur Mutlu, Chita R. Das
2014	A*	`conf`	NoC Architectures for Silicon Interposer Systems: Why Pay for more Wires when you Can Get them (from your interposer) for Free? MICRO Natalie D. Enright Jerger, Ajaykumar Kannan, Zimo Li, Gabriel H. Loh
2014	—	`conf`	Toward efficient programmer-managed two-level memory hierarchies in exascale computers. Co-HPC@SC Mitesh R. Meswani, Gabriel H. Loh, Sergey Blagodurov, David Roberts, John Slice, Mike Ignatowski
2014	A*	`conf`	Unison Cache: A Scalable and Effective Die-Stacked DRAM Cache. MICRO Djordje Jevdjic, Gabriel H. Loh, Cansu Kaynak, Babak Falsafi
2013	J	`jnl`	Guest Editorial. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yuan Xie, Gabriel H. Loh
2013	J	`jnl`	Optimizing GPU energy efficiency with 3D die-stacking graphics memory and reconfigurable memory interface. ACM Trans. Archit. Code Optim. Jishen Zhao, Guangyu Sun, Gabriel H. Loh, Yuan Xie
2013	A*	`conf`	Resilient die-stacked DRAM caches. ISCA Jaewoong Sim, Gabriel H. Loh, Vilas Sridharan, Mike O'Connor
2013	J	`jnl`	Top Picks from the 2012 Computer Architecture Conferences. IEEE Micro Babak Falsafi, Gabriel H. Loh
2012	—	`conf`	3D-MAPS: 3D Massively parallel processor with stacked memory. ISSCC Dae Hyun Kim, Krit Athikulwongse, Michael B. Healy, Mohammad M. Hossain, Moongon Jung, Ilya Khorosh, Gokul Kumar, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Shreepad Panth, Mohit Pathak, Minzhen Ren, Guanhao Shen, Taigon Song, Dong Hyuk Woo, Xin Zhao, Joungho Kim, Ho Choi, Gabriel H. Loh, Hsien-Hsin S. Lee, Sung Kyu Lim
2012	A*	`conf`	A Mostly-Clean DRAM Cache for Effective Hit Speculation and Self-Balancing Dispatch. MICRO Jaewoong Sim, Gabriel H. Loh, Hyesoon Kim, Mike O'Connor, Mithuna Thottethodi
2012	—	`conf`	Computer architecture for die stacking. VLSI-DAT Gabriel H. Loh
2012	A	`conf`	Energy-efficient GPU design with reconfigurable in-package graphics memory. ISLPED Jishen Zhao, Guangyu Sun, Gabriel H. Loh, Yuan Xie
2012	J	`jnl`	Exploiting New Interconnect Technologies in On-Chip Communication. IEEE J. Emerg. Sel. Topics Circuits Syst. John Kim, Kiyoung Choi, Gabriel H. Loh
2012	A*	`conf`	Fundamental Latency Trade-off in Architecting DRAM Caches: Outperforming Impractical SRAM-Tags with a Simple and Practical Design. MICRO Moinuddin K. Qureshi, Gabriel H. Loh
2012	J	`jnl`	Guest Editorial New Interconnect Technologies in On-Chip Communication. IEEE J. Emerg. Sel. Topics Circuits Syst. Kiyoung Choi, John Kim, Gabriel H. Loh
2012	A*	`conf`	Staged memory scheduling: Achieving high performance and scalability in heterogeneous systems. ISCA Rachata Ausavarungnirun, Kevin Kai-Wei Chang, Lavanya Subramanian, Gabriel H. Loh, Onur Mutlu
2012	J	`jnl`	Supporting Very Large DRAM Caches with Compound-Access Scheduling and MissMap. IEEE Micro Gabriel H. Loh, Mark D. Hill
2011	A*	`conf`	A register-file approach for row buffer caches in die-stacked DRAMs. MICRO Gabriel H. Loh
2011	A*	`conf`	Efficiently enabling conventional block sizes for very large die-stacked DRAM caches. MICRO Gabriel H. Loh, Mark D. Hill
2011	A*	`conf`	Preventing PCM banks from seizing too much power. MICRO Andrew W. Hay, Karin Strauss, Timothy Sherwood, Gabriel H. Loh, Doug Burger
2011	C	`conf`	Thread-aware dynamic shared cache compression in multi-core processors. ICCD Yuejian Xie, Gabriel H. Loh
2010	J	`jnl`	3D Stacked Microprocessor: Are We There Yet? IEEE Micro Gabriel H. Loh, Yuan Xie
2010	—	`conf`	Design and analysis of 3D-MAPS: A many-core 3D processor with stacked memory. CICC Michael B. Healy, Krit Athikulwongse, Rohan Goel, Mohammad M. Hossain, Dae Hyun Kim, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Moongon Jung, Brian Ouellette, Mohit Pathak, Hemant Sane, Guanhao Shen, Dong Hyuk Woo, Xin Zhao, Gabriel H. Loh, Hsien-Hsin S. Lee, Sung Kyu Lim
2010	A*	`conf`	Quantifying and coping with parametric variations in 3D-stacked microarchitectures. DAC Serkan Ozdemir, Yan Pan, Abhishek Das, Gokhan Memik, Gabriel H. Loh, Alok N. Choudhary
2010	—	`conf`	Scalable Shared-Cache Management by Containing Thrashing Workloads. HiPEAC Yuejian Xie, Gabriel H. Loh
2010	A*	`conf`	Use ECP, not ECC, for hard failures in resistive memories. ISCA Stuart E. Schechter, Gabriel H. Loh, Karin Strauss, Doug Burger
2009	J	`jnl`	3D-Integrated SRAM Components for High-Performance Microprocessors. IEEE Trans. Computers Kiran Puttaswamy, Gabriel H. Loh
2009	A*	`conf`	Criticality-based optimizations for efficient load processing. HPCA Samantika Subramaniam, Anne Bracy, Hong Wang, Gabriel H. Loh
2009	J	`jnl`	Design and optimization of the store vectors memory dependence predictor. ACM Trans. Archit. Code Optim. Samantika Subramaniam, Gabriel H. Loh
2009	A*	`conf`	Extending the effectiveness of 3D-stacked DRAM caches with an adaptive multi-queue policy. MICRO Gabriel H. Loh
2009	A*	`conf`	PIPP: promotion/insertion pseudo-partitioning of multi-core shared caches. ISCA Yuejian Xie, Gabriel H. Loh
2009	—	`conf`	Thermal optimization in multi-granularity multi-core floorplanning. ASP-DAC Michael B. Healy, Hsien-Hsin S. Lee, Gabriel H. Loh, Sung Kyu Lim
2009	B	`conf`	Zesto: A cycle-level simulator for highly detailed microarchitecture exploration. ISPASS Gabriel H. Loh, Samantika Subramaniam, Yuejian Xie
2008	A*	`conf`	3D-Stacked Memory Architectures for Multi-core Processors. ISCA Gabriel H. Loh
2008	C	`conf`	A Segmented Bloom Filter Algorithm for Efficient Predictors. SBAC-PAD Maurício Breternitz Jr., Gabriel H. Loh, Bryan Black, Jeff Rupley, Peter G. Sassone, Wesley Attrot, Youfeng Wu
2008	—	`conf`	A modular 3d processor for flexible product design and technology migration. Conf. Computing Frontiers Gabriel H. Loh
2008	J	`jnl`	Modulo Path History for the Reduction of Pipeline Overheads in Path-based Neural Branch Predictors. Int. J. Parallel Program. Gabriel H. Loh, Daniel A. Jiménez
2008	A*	`conf`	PEEP: Exploiting predictability of memory dependences in SMT processors. HPCA Samantika Subramaniam, Milos Prvulovic, Gabriel H. Loh
2007	A*	`conf`	Matrix scheduler reloaded. ISCA Peter G. Sassone, Jeff Rupley, Edward Brekelbaum, Gabriel H. Loh, Bryan Black
2007	J	`jnl`	Multiobjective Microarchitectural Floorplanning for 2-D and 3-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Michael B. Healy, Mario Vittes, Mongkol Ekpanyapong, Chinnakrishnan S. Ballapuram, Sung Kyu Lim, Hsien-Hsin S. Lee, Gabriel H. Loh
2007	J	`jnl`	Processor Design in 3D Die-Stacking Technologies. IEEE Micro Gabriel H. Loh, Yuan Xie, Bryan Black
2007	A*	`conf`	Scalability of 3D-Integrated Arithmetic Units in High-Performance Microprocessors. DAC Kiran Puttaswamy, Gabriel H. Loh
2007	J	`jnl`	Static strands: Safely exposing dependence chains for increasing embedded power efficiency. ACM Trans. Embed. Comput. Syst. Peter G. Sassone, D. Scott Wills, Gabriel H. Loh
2007	A*	`conf`	Thermal Herding: Microarchitecture Techniques for Controlling Hotspots in High-Performance 3D-Integrated Processors. HPCA Kiran Puttaswamy, Gabriel H. Loh
2006	A*	`conf`	Adaptive Caches: Effective Shaping of Cache Behavior to Workloads. MICRO Ranjith Subramanian, Yannis Smaragdakis, Gabriel H. Loh
2006	C	`conf`	Controlling the Power and Area of Neural Branch Predictors for Practical Implementation in High-Performance Processors. SBAC-PAD Daniel A. Jiménez, Gabriel H. Loh
2006	J	`jnl`	Design space exploration for 3D architectures. ACM J. Emerg. Technol. Comput. Syst. Yuan Xie, Gabriel H. Loh, Bryan Black, Kerry Bernstein
2006	A*	`conf`	Die Stacking (3D) Microarchitecture. MICRO Bryan Black, Murali Annavaram, Ned Brekelbaum, John DeVale, Lei Jiang, Gabriel H. Loh, Don McCaule, Patrick Morrow, Donald W. Nelson, Daniel Pantuso, Paul Reed, Jeff Rupley, Sadasivan Shankar, John Paul Shen, Clair Webb
2006	—	`conf`	Dynamic instruction schedulers in a 3-dimensional integration technology. ACM Great Lakes Symposium on VLSI Kiran Puttaswamy, Gabriel H. Loh
2006	Misc	`conf`	Entropy-based low power data TLB design. CASES Chinnakrishnan S. Ballapuram, Kiran Puttaswamy, Gabriel H. Loh, Hsien-Hsin S. Lee
2006	A*	`conf`	Fire-and-Forget: Load/Store Scheduling with No Store Queue at All. MICRO Samantika Subramaniam, Gabriel H. Loh
2006	—	`conf`	Implementing Register Files for High-Performance Microprocessors in a Die-Stacked (3D) Technology. ISVLSI Kiran Puttaswamy, Gabriel H. Loh
2006	A	`conf`	Microarchitectural floorplanning under performance and thermal tradeoff. DATE Michael B. Healy, Mario Vittes, Mongkol Ekpanyapong, Chinnakrishnan S. Ballapuram, Sung Kyu Lim, Hsien-Hsin S. Lee, Gabriel H. Loh
2006	B	`conf`	Revisiting the performance impact of branch predictor latencies. ISPASS Gabriel H. Loh
2006	A*	`conf`	Store vectors for scalable memory dependence prediction and scheduling. HPCA Samantika Subramaniam, Gabriel H. Loh
2006	C	`conf`	The impact of 3-dimensional integration on the design of arithmetic units. ISCAS Kiran Puttaswamy, Gabriel H. Loh
2006	—	`conf`	Thermal analysis of a 3D die-stacked high-performance microprocessor. ACM Great Lakes Symposium on VLSI Kiran Puttaswamy, Gabriel H. Loh
2005	—	`conf`	A Simple Divide-and-Conquer Approach for Neural-Class Branch Prediction. IEEE PACT Gabriel H. Loh
2005	J	`jnl`	Deconstructing the Frankenpredictor for Implementable Branch Predictors. J. Instr. Level Parallelism Gabriel H. Loh
2005	C	`conf`	Implementing Caches in a 3D Technology for High Performance Processors. ICCD Kiran Puttaswamy, Gabriel H. Loh
2005	B	`conf`	Simulation Differences Between Academia and Industry: A Branch Prediction Case Study. ISPASS Gabriel H. Loh
2005	B	`conf`	Static strands: safely collapsing dependence chains for increasing embedded power efficiency. LCTES Peter G. Sassone, D. Scott Wills, Gabriel H. Loh
2003	J	`jnl`	Exploiting Bias in the Hysteresis Bit of 2-bit Saturating Counters in Branch Predictors. J. Instr. Level Parallelism Gabriel H. Loh, Dana S. Henry, Arvind Krishnamurthy
2003	J	`jnl`	Width-Partitioned Load Value Predictors. J. Instr. Level Parallelism Gabriel H. Loh
2002	J	`jnl`	A Comparison of Asymptotically Scalable Superscalar Processors. Theory Comput. Syst. Bradley C. Kuszmaul, Dana S. Henry, Gabriel H. Loh
2002	C	`conf`	Applying Machine Learning for Ensemble Branch Predictors. IEA/AIE Gabriel H. Loh, Dana S. Henry
2002	A*	`conf`	Exploiting data-width locality to increase superscalar execution bandwidth. MICRO Gabriel H. Loh
2002	—	`conf`	Predicting Conditional Branches With Fusion-Based Hybrid Predictors. IEEE PACT Gabriel H. Loh, Dana S. Henry
2002	—	`conf`	Speculative Clustered Caches for Clustered Processors. ISHPC Dana S. Henry, Gabriel H. Loh, Rahul Sami
2001	—	`conf`	A time-stamping algorithm for efficient performance estimation of superscalar processors. SIGMETRICS/Performance Gabriel H. Loh
2000	A*	`conf`	Circuits for wide-window superscalar processors. ISCA Dana S. Henry, Bradley C. Kuszmaul, Gabriel H. Loh, Rahul Sami
1999	B	`conf`	A Comparison of Scalable Superscalar Processors. SPAA Bradley C. Kuszmaul, Dana S. Henry, Gabriel H. Loh