G. Venkatesh

19 papers A* 1A 2Misc 8Journal 6Unranked 2
YearRankTypeTitle / Venue / Authors
1998 Misc conf
Algorithmic and Architectural Transformations for Low Power Realization of FIR Filters.
VLSI Design
Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh
1998 Misc conf
Coefficient Transformations for Area-Efficient Implementation of Multiplier-less FIR Filters.
VLSI Design
Mahesh Mehendale, Somdipta Basu Roy, Sunil D. Sherlekar, G. Venkatesh
1998 Misc conf
Extensions to Programmable DSP architectures for Reduced Power Dissipation.
VLSI Design
Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh
1998 J jnl
Low-power realization of FIR filters on programmable DSPs.
IEEE Trans. Very Large Scale Integr. Syst.
Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh
1997 Misc conf
Area-Delay Tradeoff in Distributed Arithmetic Based Implementation of FIR Filters.
VLSI Design
Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh
1996 Misc conf
Low power realization of FIR filters using multirate architectures.
VLSI Design
Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh
1996 J jnl
Monitoring machine based synthesis technique for concurrent error detection in finite state machines.
J. Electron. Test.
Rubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar
1996 A* conf
Optimized Code Generation of Multiplication-free Linear Transforms.
DAC
Mahesh Mehendale, G. Venkatesh, Sunil D. Sherlekar
1995 Misc conf
A new methodology for the design of low-cost fail safe circuits and networks.
VLSI Design
B. Ravi Kishore, Rubin A. Parekhji, Sandeep Pagey, Sunil D. Sherlekar, G. Venkatesh
1995 J jnl
Concurrent Error Detection Using Monitoring Machines.
IEEE Des. Test Comput.
Rubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar
1995 A conf
Synthesis of multiplier-less FIR filters with minimum number of additions.
ICCAD
Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh
1995 — conf
Techniques for low power realization for FIR filters.
ASP-DAC
Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh
1993 Misc conf
State Assignment for Optimal Design of Monitored Self-Checking Sequential Circuits.
VLSI Design
Rubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar
1992 Misc conf
A Behavioral Fault Simulator For Ideal.
VLSI Design
Ajay Khoche, Sunil D. Sherlekar, G. Venkatesh
1992 J jnl
A Behavioral Fault Simulator for Ideal.
IEEE Des. Test Comput.
Ajay Khoche, Sunil D. Sherlekar, G. Venkatesh, Raja Venkateswaran
1992 — conf
Path breaker: a tool for the optimal design of speed independent asynchronous controllers.
EURO-DAC
Yogesh Mishra, Sunil D. Sherlekar, G. Venkatesh
1991 A conf
A Methodology for Designing Optimal Self-Checking Sequential Circuits.
ITC
Rubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar
1991 J jnl
A methodology for the design of SFS/SCD circuits for a class of unordered codes.
J. Electron. Test.
Sandeep Pagey, Sunil D. Sherlekar, G. Venkatesh
1989 J jnl
Ideas: a tool for VLSI CAD.
IEEE Des. Test
Alok Kumar, Vijeta Kashyap, Sunil D. Sherlekar, G. Venkatesh, S. Biswas, Anshul Kumar, P. C. P. Bhatt, Sashi Kumar