G. S. Visweswaran

25 papers A 2Misc 11Journal 4Unranked 8

Year	Rank	Type	Title / Venue / Authors
2018	Misc	`conf`	A 0.6V Retention VMIN Ultra-Low Leakage High Density 6T SRAM in 40nm CMOS Technology Using Adaptive Source Bias. VLSID Ashish Kumar, G. S. Visweswaran
2017	J	`jnl`	A 32 kb 0.35-1.2 V, 50 MHz-2.5 GHz Bit-Interleaved SRAM With 8 T SRAM Cell and Data Dependent Write Assist in 28-nm UTBB-FDSOI CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. Anuj Grover, G. S. Visweswaran, Chittoor R. Parthasarathy, Mohammad Daud, David Turgis, Bastien Giraud, Jean-Philippe Noel, Ivan Miro Panades, Guillaume Moritz, Edith Beigné, Philippe Flatresse, Promod Kumar, Shamsi Azmi
2017	J	`jnl`	Charge-Controlled Oscillators and Their Application in Frequency Synthesis. IEEE Trans. Circuits Syst. II Express Briefs Roohie Kaushik, Shouri Chatterjee, G. S. Visweswaran
2016	Misc	`conf`	A 0.5V VMIN 6T SRAM in 28nm UTBB FDSOI Technology Using Compensated WLUD Scheme with Zero Performance Loss. VLSID Ashish Kumar, G. S. Visweswaran, Vinay Kumar, Kaushik Saha
2016	—	`conf`	A method to estimate effectiveness of weak bit test: Comparison of weak pMOS and WL boost based test - 28nm FDSOI implementation. SoCC Nidhi Batra, Shashwat Kaushik, Anil Kumar Gundu, Mohammad S. Hashmi, G. S. Visweswaran, Anuj Grover
2016	—	`conf`	An effective test methodology enabling detection of weak bits in SRAMs: Case study in 28nm FDSOI. VDAT Nidhi Batra, Anil Kumar Gundu, Mohammad S. Hashmi, G. S. Visweswaran, Anuj Grover
2016	—	`conf`	Heterogeneous memory assembly exploration using a floorplan and interconnect aware framework. SoCC Prakhar Raj Gupta, G. S. Visweswaran, Gaurav Narang, Anuj Grover
2016	Misc	`conf`	Impact of crosstalk and process variation on capture power reduction for at-speed test. VTS Surya Piplani, G. S. Visweswaran, Anshul Kumar
2015	—	`conf`	A 6T-SRAM in 28nm FDSOI technology with Vmin of 0.52V using assisted read and write operation. ICICDT Ashish Kumar, Vinay Kumar, Dhori Kedar Janardan, G. S. Visweswaran, Kaushik Saha
2015	—	`conf`	Low Standby Power Capacitively Coupled Sense Amplifier for wide voltage range operation of dual rail SRAMs. ICICDT Anuj Grover, Promod Kumar, Mohammad Daud, G. S. Visweswaran, Chittoor R. Parthasarathy, Jean-Philippe Noel, David Turgis, Bastien Giraud, Guillaume Moritz
2015	—	`conf`	Low voltage error resilient SRAM using run-time error detection and correction. ESSCIRC Ashish Kumar, G. S. Visweswaran, Kaushik Saha
2011	J	`jnl`	Digital fractional-order differentiator and integrator models based on first-order and higher order operators. Int. J. Circuit Theory Appl. Maneesha Gupta, Pragya Varshney, G. S. Visweswaran
2011	J	`jnl`	New Approach to Realize Fractional Power in z-Domain at Low Frequency. IEEE Trans. Circuits Syst. II Express Briefs G. S. Visweswaran, Pragya Varshney, Maneesha Gupta
2010	—	`conf`	FFT based sign modulated DWT filter bank. EUSIPCO Lalit K. Jiwani, Shiv Dutt Joshi, G. S. Visweswaran
2008	—	`conf`	Novel Digital Differentiator and Corresponding Fractional Order Differentiator Models. SIGMAP Maneesha Gupta, Pragya Varshney, G. S. Visweswaran, B. Kumar
2008	A	`conf`	Texture filter memory: a power-efficient and scalable texture memory architecture for mobile graphics processors. ICCAD B. V. N. Silpa, Anjul Patney, Tushar Krishna, Preeti Ranjan Panda, G. S. Visweswaran
2006	A	`conf`	Battery aware dynamic scheduling for periodic task graphs. IPDPS Venkat Rao, Nicolas Navet, Gaurav Singhal, Anshul Kumar, G. S. Visweswaran
2005	Misc	`conf`	A Relative Comparative Based Datapath for Increasing Resolution in a Capacitive Fingerprint Sensor Chip. VLSI Design Mukul Milind Ojha, Arun Kumar Anand, G. S. Visweswaran, D. Nagchoudhuri
2004	Misc	`conf`	Inclusion of Thermal Effects in the Simulation of Bipolar Circuits using Circuit Level Behavioral Modeling. VLSI Design Tushar S. Shelar, G. S. Visweswaran
2000	Misc	`conf`	A 3.3V Compatible 2.5V TTL-to-CMOS Bidirectional I/O Buffer. VLSI Design Sanjeev Kumar Maheshwari, G. S. Visweswaran
2000	Misc	`conf`	Jitter Estimation Methodology for Clock Chips. VLSI Design Sanjeev Kumar Maheshwari, R. S. Krishanan, G. S. Visweswaran
1999	Misc	`conf`	A Low Power 256 KB SRAM Design. VLSI Design Basabi Bhaumik, Pravas Pradhan, G. S. Visweswaran, Rajamohan Varambally, Anand Hardi
1999	Misc	`conf`	A New Test Compression Scheme. VLSI Design Basabi Bhaumik, G. S. Visweswaran, R. Lakshminarasimhan
1998	Misc	`conf`	Current Mode Ternary D/A Converter. VLSI Design Saeid Nooshabadi, G. S. Visweswaran, D. Nagchoudhuri
1997	Misc	`conf`	Micropipeline Architecture for Multiplier-less FIR Filters. VLSI Design Saeid Nooshabadi, Juan A. Montiel-Nelson, G. S. Visweswaran, D. Nagchoudhuri