Fábio Luís Livi Ramos

21 papers C 3Journal 6Unranked 12
YearRankTypeTitle / Venue / Authors
2025 — conf
Design Landscape of VVC Binary Arithmetic Decoder using Multiple Bypass Bins Processing.
SBCCI
Gabriel Rosa Dias, Jiovana Sousa Gomes, Sergio Bampi, Fábio Luís Livi Ramos
2025 J jnl
End-to-End Neural Video Compression: A Review.
IEEE Open J. Circuits Syst.
Jiovana Sousa Gomes, Mateus Grellert, Fábio Luís Livi Ramos, Sergio Bampi
2025 J jnl
Hardware accelerator for VVC/H.266 residual syntax elements: a unified and resource-efficient architecture.
J. Real Time Image Process.
Gabriel Bitencourt Cardoso, Heitor Mauro Chavez Huarachi, Daniel Felipe Tomm, Jiovana Sousa Gomes, Rodrigo N. Wuerdig, Marcelo Romero de Moraes, Sergio Bampi, Fábio Luís Livi Ramos
2025 — conf
High-Performance Binary Arithmetic Encoder with Multiple Bypass Bin Scheme for VVC CABAC.
LASCAS
Vinícius Martins Faria, Jiovana Sousa Gomes, Sergio Bampi, Fábio Luís Livi Ramos
2025 — conf
NNCodec Neural Network Compression Assessment and Binarization Step Hardware Design.
SBCCI
Gabriel Bitencourt Cardoso, Jiovana Sousa Gomes, Ricardo Peixoto Robaina, Sergio Bampi, Fábio Luís Livi Ramos
2024 — conf
Statistical Analysis of VVC Residual and Entropy Coding aiming Efficient Hardware Design.
LASCAS
Gabriel Bitencourt Cardoso, Daniel Felipe Tomm, Jiovana Sousa Gomes, Rodrigo N. Wuerdig, Sergio Bampi, Fábio Luís Livi Ramos
2023 — conf
AV1 Residual Syntax Elements Assessment and Efficient VLSI Architecture.
SBCCI
Jiovana Sousa Gomes, Rodrigo N. Wuerdig, Fábio Luís Livi Ramos, Sergio Bampi
2023 — conf
Analysis of AV1 Arithmetic Decoder Design Space with a Novel Multi-Boolean Approach.
LASCAS
Jiovana Sousa Gomes, Tulio Pereira Bitencourt, Sergio Bampi, Fábio Luís Livi Ramos
2022 C conf
Area and Power Efficient 8K Real-Time Design for AV1 Arithmetic Decoding.
PCS
Jiovana Sousa Gomes, Tulio Pereira Bitencourt, Sergio Bampi, Fábio Luís Livi Ramos
2022 J jnl
Low-Power High-Throughput Architecture for AV1 Arithmetic Decoder.
IEEE Des. Test
Jiovana Sousa Gomes, Tulio Pereira Bitencourt, Sergio Bampi, Fábio Luís Livi Ramos
2022 J jnl
Power-Saving 8K Real-Time AV1 Arithmetic Encoder Architecture.
IEEE Des. Test
Tulio Pereira Bitencourt, Fábio Luís Livi Ramos, Sergio Bampi
2022 C conf
Power-Throughput Trade-off Analysis for a Novel Multi-Boolean AV1 Arithmetic Encoder Design.
PCS
Tulio Pereira Bitencourt, Fábio Luís Livi Ramos, Sergio Bampi
2021 J jnl
Energy-Throughput Configurable Design for Video Processing Binary Arithmetic Encoder.
IEEE Trans. Circuits Syst. Video Technol.
Fábio Luís Livi Ramos, Bruno Zatt, Marcelo Schiavon Porto, Sergio Bampi
2020 J jnl
Residual Syntax Elements Analysis and Design Targeting High-Throughput HEVC CABAC.
IEEE Trans. Circuits Syst. I Regul. Pap.
Fábio Luís Livi Ramos, Alessandro Via Piana Saggiorato, Bruno Zatt, Marcelo Schiavon Porto, Sergio Bampi
2018 — conf
HEVC Residual Syntax Elements Generation Architecture for High-Throughput CABAC Design.
ICECS
Alessandro Via Piana Saggiorato, Fábio Luís Livi Ramos, Bruno Zatt, Marcelo Schiavon Porto, Sergio Bampi
2018 C conf
High-Throughput Binary Arithmetic Encoder using Multiple-Bypass Bins Processing for HEVC CABAC.
ISCAS
Fábio Luís Livi Ramos, Bruno Zatt, Marcelo Schiavon Porto, Sergio Bampi
2017 — conf
Low-power HEVC binarizer architecture for the CABAC block targeting UHD video processing.
SBCCI
Camila de Matos Alonso, Fábio Luís Livi Ramos, Bruno Zatt, Marcelo Schiavon Porto, Sergio Bampi
2017 — conf
Low-power multi-size HEVC DCT architecture proposal for QFHD video processing.
SBCCI
Luana Vieira Martinez Bonatto, Fábio Luís Livi Ramos, Bruno Zatt, Marcelo Schiavon Porto, Sergio Bampi
2017 — conf
Novel multiple bypass bins scheme for low-power UHD video processing HEVC binary arithmetic encoder architecture.
SBCCI
Fábio Luís Livi Ramos, Bruno Zatt, Marcelo Schiavon Porto, Sergio Bampi
2016 — conf
Low-power hardware design for the HEVC Binary Arithmetic Encoder targeting 8K videos.
SBCCI
Fábio Luís Livi Ramos, Jones Goebel, Bruno Zatt, Marcelo Schiavon Porto, Sergio Bampi
2010 — conf
A high throughput CAVLC hardware architecture with parallel coefficients processing for HDTV H.264/AVC enconding.
ICECS
Fábio Luís Livi Ramos, Bruno Zatt, Thaísa Leal da Silva, Altamiro Amadeu Susin, Sergio Bampi