Fur-Shing Tsai

13 papers A* 2A 3Journal 6Unranked 2
YearRankTypeTitle / Venue / Authors
2007 — conf
Bridging RTL and gate: correlating different levels of abstraction for design debugging.
HLDVT
Eric Cheung, Xi Chen, Fur-Shing Tsai, Yu-Chin Hsu, Harry Hsieh
2006 A* conf
Visibility enhancement for silicon debug.
DAC
Yu-Chin Hsu, Fur-Shing Tsai, Wells Jong, Ying-Tsai Chang
2003 A* conf
Advanced techniques for RTL debugging.
DAC
Yu-Chin Hsu, Bassam Tabbara, Yirng-An Chen, Fur-Shing Tsai
2002 J jnl
Optimal time borrowing analysis and timing budgeting optimization for latch-based designs.
ACM Trans. Design Autom. Electr. Syst.
Shi-Zheng Eric Lin, Chieh Changfan, Yu-Chin Hsu, Fur-Shing Tsai
2000 J jnl
Timing optimization on routed designs with incremental placementand routing characterization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chieh Changfan, Yu-Chin Hsu, Fur-Shing Tsai
1999 — conf
Post-routing timing optimization with routing characterization.
ISPD
Chieh Changfan, Yu-Chin Hsu, Fur-Shing Tsai
1997 J jnl
Layout Modeling and Design Space Exploration in Pss1 System.
VLSI Design
Fur-Shing Tsai, Yu-Chin Hsu
1992 J jnl
STAR: An automatic data path allocator.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Fur-Shing Tsai, Yu-Chin Hsu
1990 A conf
Data Path Construction and Refinement.
ICCAD
Fur-Shing Tsai, Yu-Chin Hsu
1990 J jnl
Hybrid routing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Youn-Long Lin, Yu-Chin Hsu, Fur-Shing Tsai
1989 A conf
Routing using a pyramid data structure.
ICCAD
Youn-Long Lin, Yu-Chin Hsu, Fur-Shing Tsai
1989 J jnl
SILK: a simulated evolution router.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Youn-Long Lin, Yu-Chin Hsu, Fur-Shing Tsai
1988 A conf
A detailed router based on simulated evolution.
ICCAD
Youn-Long Lin, Yu-Chin Hsu, Fur-Shing Tsai