Fumiyasu Hirose

17 papers A* 3A 3C 2Misc 1Journal 3Unranked 4
YearRankTypeTitle / Venue / Authors
2006 — ed.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006
ASP-DAC
Fumiyasu Hirose
1999 — conf
Speeding Up Look-up-Table Driven Logic Simulation.
VLSI
Rajeev Murgai, Fumiyasu Hirose, Masahiro Fujita
1998 C conf
An approach to verify a large scale system-on-a-chip using symbolic model checking.
ICCD
Koichiro Takayama, Taizo Satoh, Tsuneo Nakata, Fumiyasu Hirose
1997 — conf
Acceleration of behavioral simulation on simulation specific machines.
ED&TC
Minoru Shoji, Fumiyasu Hirose, Shintaro Shimogori, Satoshi Kowatari, Hiroshi Nagai
1997 — conf
Acceleration of mincut partitioning using hardware CAD accelerator TP5000.
ASP-DAC
Masahiro Sano, Shintaro Shimogori, Fumiyasu Hirose
1996 A conf
CTL model checking based on forward state traversal.
ICCAD
Hiroaki Iwashita, Tsuneo Nakata, Fumiyasu Hirose
1995 C conf
Logic synthesis for a single large look-up table.
ICCD
Rajeev Murgai, Masahiro Fujita, Fumiyasu Hirose
1995 — conf
Panel: New Research Problems in the Emerging Test Technology.
Asian Test Symposium
Vishwani D. Agrawal, Bernard Courtois, Fumiyasu Hirose, Sandip Kundu, Chung-Len Lee, Yinghua Min, Parimal Pal Chaudhuri
1994 A conf
Automatic test program generation for pipelined processors.
ICCAD
Hiroaki Iwashita, Satoshi Kowatari, Tsuneo Nakata, Fumiyasu Hirose
1992 A* conf
Performance Evaluation of an Event-Driven Logic Simulation Machine.
DAC
Fumiyasu Hirose
1992 Misc conf
Test pattern generation system for delay faults using a high speed simulation processor 'SP'.
VTS
Yukiko Izuta, Fumiyasu Hirose
1990 J jnl
A high-speed test-generation method using a test generation circuit.
Syst. Comput. Jpn.
Fumiyasu Hirose, Koichiro Takayama, Nobuaki Kawato
1989 J jnl
Logic simulation engines in Japan.
IEEE Des. Test
Shigeru Takasaki, Fumiyasu Hirose, Akihiko Yamada
1989 J jnl
Simulation processor "SP".
Syst. Comput. Jpn.
Hiroshi Yamada, Fumiyasu Hirose, Junichi Niitsuma, Tatsuya Shindo
1988 A conf
A Method to Generate Tests for Combinational Logic Circuits Using an Ultra-High-Speed Logic Simulator.
ITC
Fumiyasu Hirose, Koichiro Takayama, Nobuaki Kawato
1988 A* conf
Logic Simulation System Using Simulation Processor (SP).
DAC
Minoru Saitoh, Kenji Iwata, Akiko Nokamura, Makoto Kakegawa, Junichi Masuda, Hirofumi Hamamura, Fumiyasu Hirose, Nobuaki Kawato
1980 A* conf
Efficient placement and routing techniques for master slice LSI.
DAC
Hiroshi Shiraishi, Fumiyasu Hirose