Fumio Yuki

18 papers C 1Journal 7Unranked 10
YearRankTypeTitle / Venue / Authors
2020 J jnl
A 100-Gbps 4-Lane Transceiver for 47-dB Loss Copper Cable in 28-nm CMOS.
IEEE Trans. Circuits Syst.
Takayasu Norimatsu, Kenji Kogo, Takemasa Komori, Naohiro Kohmu, Fumio Yuki, Takashi Kawamoto
2016 — conf
3.3 A 25Gb/s multistandard serial link transceiver for 50dB-loss copper cable in 28nm CMOS.
ISSCC
Takayasu Norimatsu, Takashi Kawamoto, Kenji Kogo, Naohiro Kohmu, Fumio Yuki, Norio Nakajima, Takashi Muto, Junya Nasu, Takemasa Komori, Hideki Koba, Tatsunori Usugi, Tomofumi Hokari, Tsuneo Kawamata, Yuichi Ito, Seiichi Umai, Masatoshi Tsuge, Takeo Yamashita, Masatoshi Hasegawa, Keiichi Higeta
2015 — conf
3.2 multi-standard 185fsrms 0.3-to-28Gb/s 40dB backplane signal conditioner with adaptive pattern-match 36-Tap DFE and data-rate-adjustment PLL in 28nm CMOS.
ISSCC
Takashi Kawamoto, Takayasu Norimatsu, Kenji Kogo, Fumio Yuki, Norio Nakajima, Masatoshi Tsuge, Tatsunori Usugi, Tomofumi Hokari, Hideki Koba, Takemasa Komori, Junya Nasu, Tsuneo Kawamata, Yuichi Ito, Seiichi Umai, Jun Kumazawa, Hiroaki Kurahashi, Takashi Muto, Takeo Yamashita, Masatoshi Hasegawa, Keiichi Higeta
2014 J jnl
A 25-Gb/s 2.2-W 65-nm CMOS Optical Transceiver Using a Power-Supply-Variation-Tolerant Analog Front End and Data-Format Conversion.
IEEE J. Solid State Circuits
Takashi Takemoto, Hiroki Yamashita, Fumio Yuki, Noboru Masuda, Hidehiro Toyoda, Norio Chujo, Yong Lee, Shinji Tsuji, Shinji Nishimura
2013 — conf
Compact and power-efficient 100-Gbps CMOS-based transceiver.
OFC/NFOEC
Takashi Takemoto, Hiroki Yamashita, Fumio Yuki, Shinji Tsuji, Yong Lee, Koichiro Adachi, Kazunori Shinoda, Yasunobu Matsuoka, Toshiki Sugawara, Shinji Nishimura, Norio Chujo, Masaaki Nido, Kazuhiko Kurata, Junji Baba, Yoshinori Watanabe, Naoya Ikeda
2013 — conf
High-frequency circuit design for 25 Gb/s×4 optical transceiver.
ASP-DAC
Norio Chujo, Takashi Takemoto, Fumio Yuki, Hiroki Yamashita
2012 — conf
A 25-Gb/s 2.2-W optical transceiver using an analog FE tolerant to power supply noise and redundant data format conversion in 65-nm CMOS.
VLSIC
Takashi Takemoto, Hiroki Yamashita, Takehito Kamimura, Fumio Yuki, Noboru Masuda, Hidehiro Toyoda, Norio Chujo, Kenji Kogo, Yong Lee, Shinji Tsuji, Shinji Nishimura
2011 — conf
10: 4 MUX and 4: 10 DEMUX gearbox LSI for 100-gigabit Ethernet link.
ISSCC
Goichi Ono, Keiki Watanabe, Takashi Muto, Hiroki Yamashita, Koji Fukuda, Noboru Masuda, Ryo Nemoto, Eiichi Suzuki, Takashi Takemoto, Fumio Yuki, Masayoshi Yagyu, Hidehiro Toyoda, Akihiro Kambe, Tatsuya Saito, Shinji Nishimura
2011 J jnl
A 10: 4 MUX and 4: 10 DEMUX Gearbox LSI for 100-Gigabit Ethernet Link.
IEEE J. Solid State Circuits
Goichi Ono, Keiki Watanabe, Takashi Muto, Hiroki Yamashita, Koji Fukuda, Noboru Masuda, Ryo Nemoto, Eiichi Suzuki, Takashi Takemoto, Fumio Yuki, Masayoshi Yagyu, Hidehiro Toyoda, Masashi Kono, Akihiro Kambe, Seiichi Umai, Tatsuya Saito, Shinji Nishimura
2010 J jnl
A 12.3-mW 12.5-Gb/s Complete Transceiver in 65-nm CMOS Process.
IEEE J. Solid State Circuits
Koji Fukuda, Hiroki Yamashita, Goichi Ono, Ryo Nemoto, Eiichi Suzuki, Noboru Masuda, Takashi Takemoto, Fumio Yuki, Tatsuya Saito
2010 — conf
A 12.3mW 12.5Gb/s complete transceiver in 65nm CMOS.
ISSCC
Koji Fukuda, Hiroki Yamashita, Goichi Ono, Ryo Nemoto, Eiichi Suzuki, Takashi Takemoto, Fumio Yuki, Tatsuya Saito
2010 — conf
A 25 Gb/s × 4-channel 74 mW/ch transimpedance amplifier in 65 nm CMOS.
CICC
Takashi Takemoto, Fumio Yuki, Hiroki Yamashita, Shinji Tsuji, Tatsuya Saito, Shinji Nishimura
2010 C conf
A 25 Gbps inductorless receiver front-end in 65-nm CMOS for serial links.
ISCAS
Norio Chujo, Takehito Kamimura, Goichi Ono, Fumio Yuki
2009 — conf
10Gb/s receiver with track-and-hold-type linear phase detector and charge-redistribution 1
ISSCC
Koji Fukuda, Hiroki Yamashita, Fumio Yuki, Goichi Ono, Ryo Nemoto, Eiichi Suzuki, Takashi Takemoto, Tatsuya Saito
2009 J jnl
A 10-Gb/s Receiver With Track-and-Hold-Type Linear Phase Detector and Charge-Redistribution First-Order ΔΣ Modulator in 90-nm CMOS.
IEEE J. Solid State Circuits
Koji Fukuda, Hiroki Yamashita, Fumio Yuki, Goichi Ono, Ryo Nemoto, Eiichi Suzuki, Takashi Takemoto, Masashi Kono, Tatsuya Saito
2008 — conf
An 8Gb/s Transceiver with 3×-Oversampling 2-Threshold Eye-Tracking CDR Circuit for -36.8dB-loss Backplane.
ISSCC
Koji Fukuda, Hiroki Yamashita, Fumio Yuki, Masayoshi Yagyu, Ryo Nemoto, Takashi Takemoto, Tatsuya Saito, Norio Chujo, Keiichi Yamamoto, Hisaaki Kanai, Atsuhiro Hayashi
2006 J jnl
A Low-Power Write Driver for Hard Disk Drives.
IEICE Trans. Electron.
Tatsuya Kawashimo, Hiroki Yamashita, Masayoshi Yagyu, Fumio Yuki
2004 J jnl
A 50-mW/ch 2.5-Gb/s/ch data recovery circuit for the SFI-5 interface with digital eye-tracking.
IEEE J. Solid State Circuits
Yoshio Miki, Tatsuya Saito, Hiroki Yamashita, Fumio Yuki, Takashige Baba, Akio Koyama, Masahito Sonehara