Fuminori Kobayashi

38 papers A 5B 2C 3Misc 2Journal 2Unranked 24

Year	Rank	Type	Title / Venue / Authors
2022	C	`conf`	Analog Correlator by a Dynamically-Reconfigured Switched-Capacitor Circuit. ISCAS Fuminori Kobayashi
2016	—	`conf`	Direct optical communication on an optically reconfigurable gate array. FGCT Shinya Furukawa, Ili Shairah Abdul Halim, Minoru Watanabe, Fuminori Kobayashi
2015	—	`conf`	Integrally accurate resolver-to-digital converter (RDC). ASCC Nordinah Ismail, Fuminori Kobayashi, Manabu Inoue
2011	—	`conf`	Optically reconflgurable gate array with a polymer-dispersed liquid crystal holographic memory. AHS Takayuki Mabuchi, Minoru Watanabe, Akifumi Ogiwara, Fuminori Kobayashi
2010	—	`conf`	A motor speed control system using a hybrid of dual-loop PLL and feed-forward. AMC Hidekazu Machida, Michinobu Kambara, Kouta Tanaka, Fuminori Kobayashi
2009	—	`conf`	A PLL configuration for reducing both incoming and inherent jitters. ICECS Fuminori Kobayashi, Yuhta Egashira, Hitoshi Kondoh
2008	—	`conf`	Low-jitter PLL by interpolate compensation. APCCAS Yutaka Nakanishi, Fuminori Kobayashi, Hitoshi Kondoh
2008	—	`conf`	MISC: Mono Instruction-Set Computer based on Dynamic Reconfiguration - a 6502 Perspective. ERSA Fuminori Kobayashi, Yasuyuki Morikawa, Minoru Watanabe
2007	—	`conf`	272 Gate Count Optically Differential Reconfigurable Gate Array VLSI. ERSA Minoru Watanabe, Takenori Shiki, Fuminori Kobayashi
2007	—	`conf`	A 0.35um CMOS 1, 632-gate-count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI. ASP-DAC Minoru Watanabe, Fuminori Kobayashi
2007	A	`conf`	A multi-context holographic memory recording system for Optically Reconfigurable Gate Arrays. IPDPS Rio Miyazaki, Minoru Watanabe, Fuminori Kobayashi
2007	C	`conf`	Holographic memory reconfigurable VLSI. ISCAS Minoru Watanabe, Fuminori Kobayashi
2006	—	`conf`	A 1, 632 Gate-Count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI. ARC Minoru Watanabe, Fuminori Kobayashi
2006	—	`conf`	A 476-gate-count dynamic optically reconfigurable gate array VLSI chip in a standard 0.35 micrometer CMOS technology. ASP-DAC Minoru Watanabe, Fuminori Kobayashi
2006	B	`conf`	A Reconfiguration Speed Adjustment Technique for ORGAs with a Holographic Memory. FPL Minoru Watanabe, Fuminori Kobayashi
2006	A	`conf`	An optically differential reconfigurable gate array with a holographic memory. IPDPS Minoru Watanabe, Mototsugu Miyano, Fuminori Kobayashi
2006	—	`conf`	Differential Reconfiguration Architecture suitable for a Holographic Memory. ERSA Minoru Watanabe, Mototsugu Miyano, Fuminori Kobayashi
2006	—	`conf`	Logic Synthesis and Place-and-Route Environment for ORGAs. ERSA Minoru Watanabe, Fuminori Kobayashi
2006	—	`conf`	Optically Reconfigurable Gate Arrays vs. ASICs. APCCAS Minoru Watanabe, Fuminori Kobayashi
2006	A	`conf`	Power consumption advantage of a dynamic optically reconfigurable gate array. IPDPS Minoru Watanabe, Fuminori Kobayashi
2006	—	`conf`	Shield Effect Analysis for a Gate Array on An Optically Reconfigurable Gate Array. ERSA Minoru Watanabe, Fuminori Kobayashi
2005	—	`conf`	A 16, 000-gate-count optically reconfigurable gate array in a standard 0.35µm CMOS technology. ISCAS (2) Minoru Watanabe, Fuminori Kobayashi
2005	—	`conf`	A Zero-Overhead Dynamic Optically Reconfigurable Gate Array. FPT Minoru Watanabe, Fuminori Kobayashi
2005	—	`conf`	An Improved Dynamic Optically Reconfigurable Gate Array. ISVLSI Minoru Watanabe, Fuminori Kobayashi
2005	A	`conf`	An Optically Differential Reconfigurable Gate Array VLSI Chip with a Dynamic Reconfiguration Circuit. IPDPS Minoru Watanabe, Fuminori Kobayashi
2005	—	`conf`	Optically Differential Reconfigurable Gate Array Using an Optical System with VCSELs. ISVLSI Mototsugu Miyano, Minoru Watanabe, Fuminori Kobayashi
2005	—	`conf`	Rapid Reconfiguration of an Optically Differential Reconfigurable Gate Array with Pulse Lasers. FPT Mototsugu Miyano, Minoru Watanabe, Fuminori Kobayashi
2004	B	`conf`	A High-Density Optically Reconfigurable Gate Array Using Dynamic Method. FPL Minoru Watanabe, Fuminori Kobayashi
2004	Misc	`conf`	An Optically Differential Reconfigurable Gate Array with a partial reconfiguration optical system and its power consumption estimation. VLSI Design Minoru Watanabe, Fuminori Kobayashi
2004	—	`conf`	An optically differential reconfigurable gate array using a 0.18 μm CMOS process. SoCC Minoru Watanabe, Fuminori Kobayashi
2004	—	`conf`	Testing Method for Optical Connections Using Gate Array Structure in ORGAs. ERSA Minoru Watanabe, Fuminori Kobayashi
2004	—	`conf`	Timing Analysis of an Optically Differential Reconfigurable Gate Array for Dynamically Reconfigurable Processors. ERSA Minoru Watanabe, Fuminori Kobayashi
2003	A	`conf`	An Optically Differential Reconfigurable Gate Array with a Dynamic Reconfiguration Circuit. IPDPS Minoru Watanabe, Fuminori Kobayashi
2002	—	`conf`	An optically differential reconfigurable gate array and its power consumption estimation. FPT Minoru Watanabe, Fuminori Kobayashi
1996	J	`jnl`	Efficient digital techniques for implementing a class of fast phase-locked loops (PLL's). IEEE Trans. Ind. Electron. Fuminori Kobayashi, Masayuki Haratsu, Masateru Yabumoto, Michio Nakano
1995	C	`conf`	A Digital PLL with Finite Impulse Responses. ISCAS Fuminori Kobayashi, Masayuki Haratsu
1992	J	`jnl`	Interpolative variable-speed repetitive control and its application to a deburring robot with cutting load control. Adv. Robotics Yoichi Kimura, Ryoji Mukai, Fuminori Kobayashi, Masaru Kobayashi
1987	Misc	`conf`	Time-varying signals analysis using squared analytic signals. ICASSP Fuminori Kobayashi, Hiroshi Suzuki