Fumihiko Tachibana

18 papers C 1Journal 6Unranked 11
YearRankTypeTitle / Venue / Authors
2025 J jnl
Quantization Strategy for Achieving Low-Cost, Accurate, Pareto-Optimal Convolutional Neural Networks Based on Analysis of Quantized Weight Parameters.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Kengo Nakata, Daisuke Miyashita, Asuka Maki, Fumihiko Tachibana, Shinichi Sasaki, Jun Deguchi, Ryuichi Fujimoto
2024 J jnl
A Mueller-Müller CDR with False-Lock-Aware Locking Scheme for a 56-Gb/s ADC-Based PAM4 Transceiver.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Fumihiko Tachibana, Huy Cu Ngo, Go Urakawa, Takashi Toi, Mitsuyuki Ashida, Yuta Tsubouchi, Mai Nozawa, Junji Wadatsumi, Hiroyuki Kobayashi, Jun Deguchi
2022 — conf
A 56-Gb/s PAM4 Transceiver with False-Lock-Aware Locking Scheme for Mueller-Müller CDR.
ESSCIRC
Fumihiko Tachibana, Huy Cu Ngo, Go Urakawa, Takashi Toi, Mitsuyuki Ashida, Yuta Tsubouchi, Mai Nozawa, Junji Wadatsumi, Hiroyuki Kobayashi, Jun Deguchi
2021 — conf
Quantization Strategy for Pareto-optimally Low-cost and Accurate CNN.
AICAS
Kengo Nakata, Daisuke Miyashita, Asuka Maki, Fumihiko Tachibana, Shinichi Sasaki, Jun Deguchi, Ryuichi Fujimoto
2020 J jnl
Weight Compression MAC Accelerator for Effective Inference of Deep Learning.
IEICE Trans. Electron.
Asuka Maki, Daisuke Miyashita, Shinichi Sasaki, Kengo Nakata, Fumihiko Tachibana, Tomoya Suzuki, Jun Deguchi, Ryuichi Fujimoto
2019 J jnl
A 12.8-Gb/s Daisy Chain-Based Downlink I/F Employing Spectrally Compressed Multi-Band Multiplexing for High-Bandwidth, Large-Capacity Storage Systems.
IEEE J. Solid State Circuits
Yuta Tsubouchi, Daisuke Miyashita, Takashi Toi, Yuji Satoh, Fumihiko Tachibana, Junji Wadatsumi, Makoto Morimoto, Ryuichi Fujimoto, Jun Deguchi
2019 C conf
Live Demonstration: FPGA-Based CNN Accelerator with Filter-Wise-Optimized Bit Precision.
ISCAS
Kengo Nakata, Asuka Maki, Daisuke Miyashita, Fumihiko Tachibana, Tomoya Suzuki, Jun Deguchi
2018 — conf
A 12.8 GB/S Daisy Chain-Based Downlink I/F Employing Spectrally Compressed Multi-Band Multiplexing for High-Bandwidth and Large-Capacity Storage Systems.
VLSI Circuits
Yuta Tsubouchi, Daisuke Miyashita, Yuji Satoh, Takashi Toi, Fumihiko Tachibana, Makoto Morimoto, Junji Wadatsumi, Jun Deguchi
2018 — conf
FPGA-based CNN Processor with Filter-Wise-Optimized Bit Precision.
A-SSCC
Asuka Maki, Daisuke Miyashita, Kengo Nakata, Fumihiko Tachibana, Tomoya Suzuki, Jun Deguchi
2014 J jnl
A 27% Active and 85% Standby Power Reduction in Dual-Power-Supply SRAM Using BL Power Calculator and Digitally Controllable Retention Circuit.
IEEE J. Solid State Circuits
Fumihiko Tachibana, Osamu Hirabayashi, Yasuhisa Takeyama, Miyako Shizuno, Atsushi Kawasumi, Keiichi Kushida, Azuma Suzuki, Yusuke Niki, Shinichi Sasaki, Tomoaki Yabe, Yasuo Unekawa
2013 — conf
A 187.5µVrms-read-noise 51mW 1.4Mpixel CMOS image sensor with PMOSCAP column CDS and 10b self-differential offset-cancelled pipeline SAR-ADC.
ISSCC
Jun Deguchi, Fumihiko Tachibana, Makoto Morimoto, Masayoshi Chiba, Takeshi Miyaba, Hideki Tanaka, Kyoichi Takenaka, Satoshi Funayama, Kunihiko Amano, Kazuhide Sugiura, Ryuta Okamoto, Shouhei Kousai
2013 — conf
A 27% active and 85% standby power reduction in dual-power-supply SRAM using BL power calculator and digitally controllable retention circuit.
ISSCC
Fumihiko Tachibana, Osamu Hirabayashi, Yasuhisa Takeyama, Miyako Shizuno, Atsushi Kawasumi, Keiichi Kushida, Azuma Suzuki, Yusuke Niki, Shinichi Sasaki, Tomoaki Yabe, Yasuo Unekawa
2012 — conf
A 47% access time reduction with a worst-case timing-generation scheme utilizing a statistical method for ultra low voltage SRAMs.
VLSIC
Atsushi Kawasumi, Yasuhisa Takeyama, Osamu Hirabayashi, Keiichi Kushida, Fumihiko Tachibana, Yusuke Niki, Shinichi Sasaki, Tomoaki Yabe
2012 — conf
Energy efficiency deterioration by variability in SRAM and circuit techniques for energy saving without voltage reduction.
ICICDT
Atsushi Kawasumi, Yasuhisa Takeyama, Osamu Hirabayashi, Keiichi Kushida, Fumihiko Tachibana, Yusuke Niki, Shinichi Sasaki, Tomoaki Yabe
2011 J jnl
A Digitized Replica Bitline Delay Technique for Random-Variation-Tolerant Timing Generation of SRAM Sense Amplifiers.
IEEE J. Solid State Circuits
Yusuke Niki, Atsushi Kawasumi, Azuma Suzuki, Yasuhisa Takeyama, Osamu Hirabayashi, Keiichi Kushida, Fumihiko Tachibana, Yuki Fujimura, Tomoaki Yabe
2011 — conf
A trimless, 0.5V-1.0V wide voltage operation, high density SRAM macro utilizing dynamic cell stability monitor and multiple memory cell access.
A-SSCC
Keiichi Kushida, Osamu Hirabayashi, Fumihiko Tachibana, Hiroyuki Hara, Atsushi Kawasumi, Azuma Suzuki, Yasuhisa Takeyama, Yuki Fujimura, Yusuke Niki, Miyako Shizuno, Shinichi Sasaki, Tomoaki Yabe
2008 — conf
A 9.7mW AAC-Decoding, 620mW H.264 720p 60fps Decoding, 8-Core Media Processor with Embedded Forward-Body-Biasing and Power-Gating Circuit in 65nm CMOS Technology.
ISSCC
Shuou Nomura, Fumihiko Tachibana, Tetsuya Fujita, Chen Kong Teh, Hiroyuki Usui, Fumiyuki Yamane, Yukimasa Miyamoto, Chaiyasit Kumtornkittikul, Hiroyuki Hara, Takahiro Yamashita, Jun Tanabe, Masaru Uchiyama, Yoshiro Tsuboi, Takashi Miyamori, Takeshi Kitahara, Hironori Sato, Y. Homma, Shuuji Matsumoto, Keiko Seki, Y. Watanabe, Mototsugu Hamada, Makoto Takahashi
2008 — conf
A process variation compensation scheme using cell-based forward body-biasing circuits usable for 1.2V design.
CICC
Fumihiko Tachibana, Hironori Sato, Takahiro Yamashita, Hiroyuki Hara, Takeshi Kitahara, Shuou Nomura, Fumiyuki Yamane, Yoshiro Tsuboi, Keiko Seki, Shuuji Matsumoto, Yoshinori Watanabe, Mototsugu Hamada