Fule Li - RankMe

77 papers C 23Journal 21Unranked 33

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	A 1-GS/s 12-bit Pipelined-SAR ADC With Dither-Based Background Calibration of Interstage Gain and Comparator Offset in 28-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. Peng Wang, Nan Wu, Fule Li, Zhihua Wang
2025	C	`conf`	A 550MHz-B and width 40dB-Gain Range Analog Baseband with Dynamic PVT Compensation Achieving 26.1 dBm OIP3 in 28-nm CMOS. ISCAS Guo Wei, Xuanyan Liu, Tian Tian, Yanshu Guo, Wenqiang Huang, Fule Li, Zhihua Wang, Hanjun Jiang
2025	C	`conf`	A Dynamic Biasing Circuit for Low-Power Push-Pull Input Buffer. ISCAS Rui Zhang, Yidong Yuan, Peng Wang, Lingxiao Shen, Fule Li, Zhihua Wang, Yi Hu, Zhenguo Li
2025	C	`conf`	A High-Speed High-Precision Comparator with Offset Calibration for SHA_less Pipeline ADCs. ISCAS Shuoxiong Yang, Dejian Li, Peng Wang, Fule Li, Zhihua Wang
2025	C	`conf`	A SHA-Less Front-end Stage Structure Suitable for Time-Interleaved Pipeline ADC. ISCAS Meng Ni, Peng Wang, Fule Li, Hanjun Jiang, Zhihua Wang
2025	J	`jnl`	A Single-Channel 8-bit 1.6-GS/s Alternate-Comparator SAR ADC With Dither-Based Background Offset Calibration in 28-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. Peng Wang, Fule Li, Zhihua Wang
2024	J	`jnl`	A 14-Bit 4 GS/s Two-Way Interleaved Pipelined ADC With Aperture Error Tunning. IEEE Trans. Circuits Syst. II Express Briefs Peilin Yang, Fule Li, Zhihua Wang
2024	—	`conf`	A 3-MHz-3-GHz 8-Phase Reset-Free Anti-Harmonic Delay-Locked Loop Using Phase Difference Composition in 65-nm CMOS. MWSCAS Jianming Pan, Meng Su, Fule Li, Yidong Yuan, Yi Hu, Zhenguo Li, Rui Zhang, Jiali Hou, Yabin Wang
2024	C	`conf`	A Floating-Ring Hybrid Amplifier Insensitive to PVT and Common-mode Variation without CMFB for High-Speed ADCs. ISCAS Yaning Wang, Zhenguo Li, Peng Wang, Yihang Cheng, Fule Li, Yi Hu, Jiali Hou, Meng Su, Mengjiao Li
2024	—	`conf`	A High Linearity ADC Front-End Circuit for Single-Ended Inputs. MWSCAS Rui Zhang, Yabin Wang, Fule Li, Yidong Yuan, Yi Hu, Hongwei Shen, Zhenguo Li, Jiaming Pan, Jiali Hou
2024	C	`conf`	A Reconfigurable Continuous-Time Delta-Sigma Modulator Structure Using Hybrid Loop Filter and Time-Interleaved Quantizer. ISCAS Chen Chen, Fangzhen Jiang, Peng Wang, Yongli Chen, Yan Xiao, Fule Li, Xiang Xie
2024	J	`jnl`	Corrigendum to 'Distributed sliding mode control for a class of impulsive uncertain delayed partial differential equations via sliding mode compensator approach' [European Journal of Control 77 (2024) 100984]. Eur. J. Control Hailong Xing, Yonggui Kao, Guangbin Wang, Fule Li
2024	J	`jnl`	Distributed sliding mode control for a class of impulsive uncertain delayed partial differential equations via sliding mode compensator approach. Eur. J. Control Hailong Xing, Yonggui Kao, Guangbin Wang, Fule Li
2023	—	`conf`	A Low Noise High Speed Dynamic Comparator Insensitive to PVT and Common-mode Input. NEWCAS Yaning Wang, Yihang Cheng, Yongli Chen, Fule Li, Chun Zhang, Zhihua Wang
2023	—	`conf`	A Wide Input Common-mode Range Pipelined ADC Front-end with Common-mode Refreshing. NEWCAS Junjie Jing, Yang Ding, Lingxiao Shen, Peng Wang, Fule Li
2023	C	`conf`	All-Digital Background Calibration of a Pipelined-SAR ADC Using the "Split ADC" Architecture. ISCAS Zhiqiang Luo, Peng Wang, Jingpeng Zhou, Fule Li
2023	C	`conf`	Current-Steering DAC Calibration Using Q-Learning. ISCAS Yaoyu Li, Yanshu Guo, Wen Jia, Fule Li, Zhihua Wang, Hanjun Jiang
2023	C	`conf`	High Linearity Front-End Circuit for RF Sampling ADCs with Nonlinear Junction Capacitor Cancellation. ISCAS Yihang Cheng, Yaning Wang, Fule Li, Chun Zhang, Zhihua Wang
2022	J	`jnl`	A 13-Bit 2-GS/s Time-Interleaved ADC With Improved Correlation-Based Timing Skew Calibration Strategy. IEEE Trans. Circuits Syst. I Regul. Pap. Meng Ni, Xiao Wang, Fule Li, Woogeun Rhee, Zhihua Wang
2022	C	`conf`	A Self-Regulating Negative Charge Pump Using Multi-Phase Clock for Wideband ADCs. ISCAS Haoran Wang, Junjie Jing, Fule Li
2022	—	`conf`	A statistics-based background capacitor mismatch calibration algorithm for SAR ADC. ICTA Zhiqiang Luo, Peng Wang, Fule Li, Chun Zhang, Zhihua Wang
2021	C	`conf`	A 12-Bit 2-GS/s Pipelined ADC Front-End Stage with Aperture Error Tuning and Split MDAC. ISCAS Peilin Yang, Fule Li, Zhihua Wang
2021	—	`conf`	A 12-bit 800MS/s pipelined A/D converter. ASICON Haoran Wang, Fule Li
2021	J	`jnl`	A 13-bit 312.5-MS/s Pipelined SAR ADC With Open-Loop Integrator-Based Residue Amplifier and Gain-Stabilized Integration Time Generation. IEEE Trans. Very Large Scale Integr. Syst. Meng Ni, Xiao Wang, Fule Li, Zhihua Wang
2020	—	`conf`	A 13-bit 312.5-MS/s Pipelined SAR ADC with Integrator-type Residue Amplifier and Inter-stage Gain Stabilization Technique. MWSCAS Meng Ni, Xiao Wang, Zhe Zhou, Yang Ding, Fule Li, Woogeun Rhee, Zhihua Wang
2020	J	`jnl`	A 14-bit 200-Ms/s SHA-Less Pipelined ADC With Aperture Error Reduction. IEEE Trans. Very Large Scale Integr. Syst. Peilin Yang, Xiao Wang, Chengwei Wang, Fule Li, Hanjun Jiang, Zhihua Wang
2020	J	`jnl`	A 530 nA quiescent current low-dropout regulator with embedded reference for wake-up receivers. Sci. China Inf. Sci. Shaoquan Gao, Hanjun Jiang, Fule Li, Zhihua Wang
2020	—	`conf`	A Correlation-based Timing Skew Calibration Strategy Using a Time-Interleaved Reference ADC. MWSCAS Meng Ni, Xiao Wang, Zhe Zhou, Yang Ding, Fule Li, Woogeun Rhee, Zhihua Wang
2020	J	`jnl`	A Simple Histogram-Based Capacitor Mismatch Calibration in SAR ADCs. IEEE Trans. Circuits Syst. Xiao Wang, Fule Li, Zhihua Wang
2019	J	`jnl`	A 14-Bit 500-MS/s Time-Interleaved ADC With Autocorrelation-Based Time Skew Calibration. IEEE Trans. Circuits Syst. II Express Briefs Xiao Wang, Fule Li, Wen Jia, Zhihua Wang
2019	—	`conf`	DCO gain calibration technique in fractional-N Δ-Σ PLL based two-point phase modulators. MWSCAS Shaoquan Gao, Hanjun Jiang, Fule Li, Zhihua Wang
2018	J	`jnl`	400-MHz/2.4-GHz Combo WPAN Transceiver IC for Simultaneous Dual-Band Communication With One Single Antenna. IEEE Trans. Circuits Syst. I Regul. Pap. Zhaoyang Weng, Hanjun Jiang, Jingjing Dong, Yang Li, Jingyi Zheng, Yiyu Shen, Fule Li, Woogeun Rhee, Zhihua Wang
2018	C	`conf`	A 14-bit 250MS/s Low-Power Pipeline ADC with Aperture Error Eliminating Technique. ISCAS Chengwei Wang, Xiao Wang, Yang Ding, Fule Li, Zhihua Wang
2018	C	`conf`	A Low-Power 12-bit 2GS/s Time-Interleaved Pipelined-SAR ADC in 28nm CMOS Process. ISCAS Xiao Wang, Chengwei Wang, Fule Li, Zhihua Wang
2017	—	`conf`	A 10 GHz 56 fsrms-integrated-jitter and -247 dB FOM ring-VCO based injection-locked clock multiplier with a continuous frequency-tracking loop in 65 nm CMOS. CICC Xuqiang Zheng, Fangxu Lv, Feng Zhao, Shigang Yue, Chun Zhang, Ziqiang Wang, Fule Li, Hanjun Jiang, Zhihua Wang
2017	—	`conf`	A 13-bit 160MS/s pipelined subranging-SAR ADC with low-offset dynamic comparator. A-SSCC Weitao Li, Fule Li, Jia Liu, Hongyu Li, Zhihua Wang
2017	—	`conf`	A 14bit 320MS/s pipelined-SAR ADC based on multiplexing of dynamic amplifier. ASICON Honghao Chu, Fule Li
2017	—	`conf`	A 4-40 Gb/s PAM4 transmitter with output linearity optimization in 65 nm CMOS. CICC Xuqiang Zheng, Chun Zhang, Fangxu Lv, Feng Zhao, Shigang Yue, Ziqiang Wang, Fule Li, Hanjun Jiang, Zhihua Wang
2017	J	`jnl`	A 40-Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset in 65-nm CMOS. IEEE J. Solid State Circuits Xuqiang Zheng, Chun Zhang, Fangxu Lv, Feng Zhao, Shuai Yuan, Shigang Yue, Ziqiang Wang, Fule Li, Zhihua Wang, Hanjun Jiang
2017	J	`jnl`	A Wireless Body Sound Sensor with a Dedicated Compact Chipset. Circuits Syst. Signal Process. Jingjing Dong, Hanjun Jiang, Kai Yang, Zhaoyang Weng, Fule Li, Jianjun Wei, Yanqing Ning, Xinkai Chen, Zhihua Wang
2017	—	`conf`	A low-offset dynamic comparator with input offset-cancellation. ASICON Ruihan Pei, Jia Liu, Xian Tang, Fule Li, Zhihua Wang
2016	J	`jnl`	A 14-bit 250 MS/s IF Sampling Pipelined ADC in 180 nm CMOS Process. IEEE Trans. Circuits Syst. I Regul. Pap. Xuqiang Zheng, Zhijun Wang, Fule Li, Feng Zhao, Shigang Yue, Chun Zhang, Zhihua Wang
2016	—	`conf`	A 28-Gb/s transmitter with 3-tap FFE and T-coil enhanced terminal in 65-nm CMOS technology. NEWCAS Naiwen Zhou, Linghan Wu, Ziqiang Wang, Xuqiang Zheng, Weidong Cao, Chun Zhang, Fule Li, Zhihua Wang
2016	—	`conf`	A 5-50 Gb/s quarter rate transmitter with a 4-tap multiple-MUX based FFE in 65 nm CMOS. ESSCIRC Xuqiang Zheng, Chun Zhang, Fangxu Lv, Feng Zhao, Shigang Yue, Ziqiang Wang, Fule Li, Zhihua Wang
2016	C	`conf`	A novel autocorrelation-based timing mismatch C alibration strategy in Time-Interleaved ADCs. ISCAS Xiao Wang, Fule Li, Zhihua Wang
2016	—	`conf`	An 11-bit 200MS/s subrange SAR ADC with charge-compensation-based reference buffer. NEWCAS Shushu Wei, Ying Ju, Fule Li, Zhihua Wang
2016	—	`conf`	An improved 40 Gb/s CDR with jitter-suppression filters and phase-compensating interpolators. A-SSCC Xuqiang Zheng, Chun Zhang, Shuai Yuan, Feng Zhao, Shigang Yue, Ziqiang Wang, Fule Li, Zhihua Wang
2016	—	`conf`	Aperture error reduction technique for subrange SAR ADC. NEWCAS Ying Ju, Fule Li, XiuJu He, Chun Zhang, Zhihua Wang
2016	—	`conf`	High speed serial interface transceiver controller based on JESD204B. NEWCAS Zhaoming Wu, Chun Zhang, Fule Li, Zhihua Wang
2015	—	`conf`	A 14-bit 200MS/s low-power pipelined flash-SAR ADC. MWSCAS Jifang Wu, Fule Li, Weitao Li, Chun Zhang, Zhihua Wang
2015	—	`conf`	A 190mW 40Gbps SerDes transmitter and receiver chipset in 65nm CMOS technology. CICC Ke Huang, Deng Luo, Ziqiang Wang, Xuqiang Zheng, Fule Li, Chun Zhang, Zhihua Wang
2015	—	`conf`	A 40Gb/s 27mW 3-tap closed-loop decision feedback equalizer in 65nm CMOS. NEWCAS Weidong Cao, Ziqiang Wang, Dongmei Li, Xuqiang Zheng, Ke Huang, Shuai Yuan, Fule Li, Zhihua Wang
2015	—	`conf`	A 40Gb/s 39mW 3-tap adaptive closed-loop decision feedback equalizer in 65nm CMOS. MWSCAS Weidong Cao, Ziqiang Wang, Dongmei Li, Xuqiang Zheng, Fule Li, Chun Zhang, Zhihua Wang
2015	—	`conf`	A 50Gb/s low power PAM4 SerDes transmitter with 4-tap FFE and high linearity output voltage in 65nm CMOS technology. ASICON Fangxu Lv, Xuqiang Zheng, Ziqiang Wang, Jianye Wang, Fule Li
2015	J	`jnl`	A Low-Cost UHF RFID System With OCA Tag for Short-Range Communication. IEEE Trans. Ind. Electron. Qi Peng, Chun Zhang, Xijin Zhao, Xuguang Sun, Fule Li, Hong Chen, Zhihua Wang
2015	—	`conf`	A calibration technique for SAR ADC based on code density test. ASICON Xian Gu, XiuJu He, Fule Li
2015	—	`conf`	A digital blind background calibration algorithm for pipelined ADC. NEWCAS Shengjing Li, Weitao Li, Fule Li, Zhihua Wang, Chun Zhang
2015	—	`conf`	A high-speed analog front-end circuit used in a 12bit 1GSps pipeline ADC. ASICON Meng Ni, Fule Li, Weitao Li, Chun Zhang, Zhihua Wang
2015	—	`conf`	A power-efficient 14-bit 250MS/s pipelined ADC. NEWCAS Weitao Li, Fule Li, Ya Wang, Shengjing Li, Chun Zhang, Zhihua Wang
2015	J	`jnl`	A power-efficient reference buffer with wide swing for switched-capacitor ADC. Microelectron. J. Weitao Li, Fule Li, Changyi Yang, Minzeng Li, Zhihua Wang
2015	C	`conf`	Charge-compensation-based reference technique for switched-capacitor ADCs. ISCAS Ya Wang, Fule Li, Chunying Xue, Zhihua Wang
2015	—	`conf`	Dedicated ICs for wearable body sound monitoring. A-SSCC Zhaoyang Weng, Shaoquan Gao, Jingjing Dong, Kai Yang, Hanjun Jiang, Fule Li, Zhihua Wang, Yanqing Ning, Xinkai Chen
2014	J	`jnl`	A low-power DC offset calibration method independent of IF gain for zero-IF receiver. Sci. China Inf. Sci. Jingjing Dong, Hanjun Jiang, Lingwei Zhang, Jianjun Wei, Fule Li, Chun Zhang, Zhihua Wang
2013	C	`conf`	A 14-bit pipelined ADC with digital background nonlinearity calibration. ISCAS Weitao Li, Cao Sun, Fule Li, Zhihua Wang
2013	C	`conf`	A LUT-free DC offset calibration method for removing the PGA-gain-correlated offset residue. ISCAS Lingwei Zhang, Hanjun Jiang, Fule Li, Jingjing Dong, Zhihua Wang
2013	J	`jnl`	A Reconfigurable Sliding-IF Transceiver for 400 MHz/2.4 GHz IEEE 802.15.6/ZigBee WBAN Hubs With Only 21% Tuning Range VCO. IEEE J. Solid State Circuits Lingwei Zhang, Hanjun Jiang, Jianjun Wei, Jingjing Dong, Fule Li, Weitao Li, Jia Gao, Jianwei Cui, Baoyong Chi, Chun Zhang, Zhihua Wang
2013	C	`conf`	A merged first and second stage for low power pipelined ADC. ISCAS Changyi Yang, Weitao Li, Fule Li, Zhihua Wang
2013	—	`conf`	An efficient calibration technique for pipeline ADC. MWSCAS Chenchen Zhao, Lili Xu, Fule Li, Zhihua Wang
2013	—	`conf`	Lifetime tracing of cardiopulmonary sounds with ultra-low-power sound sensor stick connected to wireless mobile network. NEWCAS Zhihua Wang, Hanjun Jiang, Kai Yang, Lingwei Zhang, Jianjun Wei, Fule Li, Baoyong Chi, Chun Zhang, Shouhao Wu, Qingliang Lin, Wen Jia
2012	C	`conf`	A 12-bit, 270MS/s pipelined ADC with SHA-eliminating front end. ISCAS Xuan Wang, Changyi Yang, Xiaoxiao Zhao, Chao Wu, Fule Li, Zhihua Wang, Bin Wu
2012	C	`conf`	A current-to-voltage integrator using area-efficient correlated double sampling technique. ISCAS Xuqiang Zheng, Fule Li, Xuan Wang, Chun Zhang
2010	—	`conf`	An energy-efficient SoC for closed-loop medical monitoring and intervention. CICC Xiaoyu Zhang, Hanjun Jiang, Fule Li, Songyuan Cheng, Chun Zhang, Zhihua Wang
2009	C	`conf`	A Robust Radio Frequency Identification System Enhanced with Spread Spectrum Technique. ISCAS Qiuling Zhu, Chun Zhang, Zhongqi Liu, Jingchao Wang, Fule Li, Zhihua Wang
2008	J	`jnl`	A 12-bit 3.7-Msample/s Pipelined A/D Converter Based on the Novel Capacitor Mismatch Calibration Technique. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shuaiqi Wang, Fule Li, Yasuaki Inoue
2007	C	`conf`	A Pipelined A/D Conversion Technique with Low INL and DNL. ISCAS Jingbo Duan, Fule Li, Liyuan Liu, Dongmei Li, Yongming Li, Zhihua Wang
2007	C	`conf`	An Incomplete Settling Technique for Pipelined Analog-to-Digital Converters. ISCAS Fule Li, Zhihua Wang, Dongmei Li
2006	J	`jnl`	A 15-bit 10-Msample/s Pipelined A/D Converter Based on Incomplete Settling Principle. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shuaiqi Wang, Fule Li, Yasuaki Inoue