Fukashi Morishita

30 papers Journal 21Unranked 9

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	A Low Noise 8.3-Mpixel CMOS Image Sensor With Selectable Multiple Sampling Technique by 5.36 GHz Global Counter and Dual Latch Skew Canceler. IEEE Trans. Circuits Syst. I Regul. Pap. Yoichi Iizuka, Akihide Maezono, Wataru Saito, Kazuhiko Takami, Fukashi Morishita
2024	—	`conf`	A Compact Optical Image Stabilization Chip with Actuator Trackability Improvement Controller and Double Offset Cancel Hall Amplifier to Improve Camera Shake Correction. A-SSCC Wataru Saito, Yoichi Iizuka, Tetsuya Takahashi, Toshiya Suzuki, Hiroto Suzuki, Masatomo Shoji, Fukashi Morishita
2023	—	`conf`	A Low Noise 8Mpixel CMOS Image Sensor with 5.36GHz Global Counter and Dual Latch Skew Canceler for Surveillance AI Camera System. A-SSCC Yoichi Iizuka, Akihide Maezono, Wataru Saito, Atsushi Yamane, Kazuhiko Takami, Fukashi Morishita
2022	J	`jnl`	A 30.2-µ Vrms Horizontal Streak Noise 8.3-Mpixel 60-Frames/s CMOS Image Sensor With Skew-Relaxation ADC and On-Chip Testable Ramp Generator for Surveillance Camera. IEEE J. Solid State Circuits Fukashi Morishita, Wataru Saito, Yoichi Iizuka, Norihito Kato, Ryota Otake, Masao Ito
2022	J	`jnl`	Circuit Techniques to Improve Low-Light Characteristics and High-Accuracy Evaluation System for CMOS Image Sensor. Sensors Norihito Kato, Fukashi Morishita, Satoshi Okubo, Masao Ito
2022	J	`jnl`	High Accuracy Test Techniques with Fine Pattern Generator and Ramp Test Circuit for CMOS Image Sensor. IEICE Trans. Electron. Fukashi Morishita, Wataru Saito, Norihito Kato, Yoichi Iizuka, Masao Ito
2021	—	`conf`	A CMOS Image Sensor and an AI Accelerator for Realizing Edge-Computing-Based Surveillance Camera Systems. VLSI Circuits Fukashi Morishita, Norihito Kato, Satoshi Okubo, Takao Toi, Mitsuru Hiraki, Sugako Otani, Hideaki Abe, Yuji Shinohara, Hiroyuki Kondo
2021	—	`conf`	A Low Noise and Linearity Improvement CMOS Image Sensor for Surveillance Camera with Skew-Relaxation Local Multiply Circuit and On-Chip Testable Ramp Generator. A-SSCC Wataru Saito, Yoichi Iizuka, Norihito Kato, Ryota Otake, Fukashi Morishita
2020	—	`conf`	An ADC Test Technique With Dual-Path/Multi-Functional Fine Pattern Generator Realizing High Accuracy Measurement for CMOS Image Sensor. ATS Fukashi Morishita, Masanori Otsuka, Wataru Saito
2015	J	`jnl`	A 3.7 M-Pixel 1300-fps CMOS Image Sensor With 5.0 G-Pixel/s High-Speed Readout Circuit. IEEE J. Solid State Circuits Shunsuke Okura, Osamu Nishikido, Yusuke Sadanaga, Yasuhiro Kosaka, Norihiko Araki, Kazuhiro Ueda, Fukashi Morishita
2014	—	`conf`	A 3.7M-pixel 1300-fps CMOS image sensor with 5.0G-pixel/s high-speed readout circuit. VLSIC Shunsuke Okura, Osamu Nishikido, Yusuke Sadanaga, Yasuhiro Kosaka, Norihiko Araki, Kazuhiro Ueda, Masanori Tachibana, Fukashi Morishita
2013	J	`jnl`	Low-Power On-Chip Charge-Recycling DC-DC Conversion Circuit and System. IEEE J. Solid State Circuits Kazuhiro Ueda, Fukashi Morishita, Shunsuke Okura, Leona Okamura, Tsutomu Yoshihara, Kazutami Arimoto
2009	J	`jnl`	On-Chip Memory Power-Cut Scheme Suitable for Low Power SoC Platform. IEICE Trans. Electron. Hiroki Shimano, Fukashi Morishita, Katsumi Dosaka, Kazutami Arimoto
2007	J	`jnl`	A Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI. IEICE Trans. Electron. Fukashi Morishita, Hideyuki Noda, Isamu Hayashi, Takayuki Gyohten, Mako Okamoto, Takashi Ipposhi, Shigeto Maegawa, Katsumi Dosaka, Kazutami Arimoto
2007	J	`jnl`	A Configurable Enhanced TTRAM Macro for System-Level Power Management Unified Memory. IEEE J. Solid State Circuits Fukashi Morishita, Isamu Hayashi, Takayuki Gyohten, Hideyuki Noda, Takashi Ipposhi, Hiroki Shimano, Katsumi Dosaka, Kazutami Arimoto
2007	J	`jnl`	A High-Density Scalable Twin Transistor RAM (TTRAM) With Verify Control for SOI Platform Memory IPs. IEEE J. Solid State Circuits Kazutami Arimoto, Fukashi Morishita, Isamu Hayashi, Katsumi Dosaka, Hiroki Shimano, Takashi Ipposhi
2007	J	`jnl`	A Voltage Scalable Advanced DFM RAM with Accelerated Screening for Low Power SoC Platform. IEICE Trans. Electron. Hiroki Shimano, Fukashi Morishita, Katsumi Dosaka, Kazutami Arimoto
2006	J	`jnl`	A Reliability-Enhanced TCAM Architecture with Associated Embedded DRAM and ECC. IEICE Trans. Electron. Hideyuki Noda, Katsumi Dosaka, Hans Jürgen Mattausch, Tetsushi Koide, Fukashi Morishita, Kazutami Arimoto
2006	—	`conf`	A Scalable ET2RAM (SETRAM) with Verify Control for SoC Platform Memory IP on SOI. CICC Kazutami Arimoto, Fukashi Morishita, Isamu Hayashi, Tetsushi Tanizaki, Takashi Ipposhi, Katsumi Dosaka
2006	J	`jnl`	An On-Chip Supply-Voltage Control System Considering PVT Variations for Worst-Caseless Lower Voltage SoC Design. IEICE Trans. Electron. Takayuki Gyohten, Fukashi Morishita, Isamu Hayashi, Mako Okamoto, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Yasutaka Horiba
2005	J	`jnl`	A 312-MHz 16-Mb random-cycle embedded DRAM macro with a power-down data retention mode for mobile applications. IEEE J. Solid State Circuits Fukashi Morishita, Isamu Hayashi, Hideto Matsuoka, Kazuhiro Takahashi, Kuniyasu Shigeta, Takayuki Gyohten, Mitsutaka Niiro, Hideyuki Noda, Mako Okamoto, Atsushi Hachisuka, Atsushi Amo, Hiroki Shinkawata, Tatsuo Kasaoka, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara
2005	J	`jnl`	A 322 MHz random-cycle embedded DRAM with high-accuracy sensing and tuning. IEEE J. Solid State Circuits Masahisa Iida, Naoki Kuroda, Hidefumi Otsuka, Masanobu Hirose, Yuji Yamasaki, Kiyoto Ohta, Kazuhiko Shimakawa, Takashi Nakabayashi, Hiroyuki Yamauchi, Tomohiko Sano, Takayuki Gyohten, Masanao Maruta, Akira Yamazaki, Fukashi Morishita, Katsumi Dosaka, Masahiko Takeuchi, Kazutami Arimoto
2005	J	`jnl`	A Study of Sense-Voltage Margins in Low-Voltage-Operating Embedded DRAM Macros. IEICE Trans. Electron. Akira Yamazaki, Fukashi Morishita, Naoya Watanabe, Teruhiko Amano, Masaru Haraguchi, Hideyuki Noda, Atsushi Hachisuka, Katsumi Dosaka, Kazutami Arimoto, Setsuo Wake, Hideyuki Ozaki, Tsutomu Yoshihara
2005	—	`conf`	A capacitorless twin-transistor random access memory (TTRAM) on SOI. CICC Fukashi Morishita, Hideyuki Noda, Takayuki Gyohten, Mako Okamoto, Takashi Ipposhi, Shigeto Maegawa, Katsumi Dosaka, Kazutami Arimoto
2005	J	`jnl`	A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture. IEEE J. Solid State Circuits Hideyuki Noda, Kazunari Inoue, Masayuki Kuroiwa, Futoshi Igaue, Kouji Yamamoto, Hans Jürgen Mattausch, Tetsushi Koide, Atsushi Amo, Atsushi Hachisuka, Shinya Soeda, Isamu Hayashi, Fukashi Morishita, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara
2005	—	`conf`	A soft-error-immune maintenance-free TCAM architecture with associated embedded DRAM. CICC Hideyuki Noda, Katsumi Dosaka, Fukashi Morishita, Kazutami Arimoto
2003	J	`jnl`	A Low Power Embedded DRAM Macro for Battery-Operated LSIs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Takeshi Fujino, Akira Yamazaki, Yasuhiko Taito, Mitsuya Kinoshita, Fukashi Morishita, Teruhiko Amano, Masaru Haraguchi, Makoto Hatakenaka, Atsushi Amo, Atsushi Hachisuka, Kazutami Arimoto, Hideyuki Ozaki
2000	J	`jnl`	High-performance embedded SOI DRAM architecture for the low-power supply. IEEE J. Solid State Circuits Tadaaki Yamauchi, Fukashi Morishita, Shigenobu Maeda, Kazutami Arimoto, Kazuyasu Fujishima, Hideyuki Ozaki, Tsutomu Yoshihara
1996	J	`jnl`	SOI-DRAM circuit technologies for low power high speed multigiga scale memories. IEEE J. Solid State Circuits Shigehiro Kuge, Fukashi Morishita, Takahiro Tsuruda, Shigeki Tomishima, Masaki Tsukude, Tadato Yamagata, Kazutami Arimoto
1994	J	`jnl`	An SOI-DRAM with wide operating voltage range by CMOS/SIMOX technology. IEEE J. Solid State Circuits Katsuhiro Suma, Takahiro Tsuruda, Hideto Hidaka, Takahisa Eimori, Toshiyuki Oashi, Yasuo Yamaguchi, Toshiaki Iwamatsu, Masakazu Hirose, Fukashi Morishita, Kazutarni Arimoto, Kazuyasu Fujishima, Yasuo Inoue, Tadashi Nishimura, Tsutomu Yoshihara