Fu-Lung Hsueh - RankMe

26 papers C 1Journal 4Unranked 21

Year	Rank	Type	Title / Venue / Authors
2018	J	`jnl`	A 0.66e IEEE J. Solid State Circuits Shang-Fu Yeh, Kuo-Yu Chou, Honyih Tu, Calvin Yi-Ping Chao, Fu-Lung Hsueh
2017	J	`jnl`	A Bluetooth Low-Energy Transceiver With 3.7-mW All-Digital Transmitter, 2.75-mW High-IF Discrete-Time Receiver, and TX/RX Switchable On-Chip Matching Network. IEEE J. Solid State Circuits Feng-Wei Kuo, Sandro Binsfeld Ferreira, Huan-Neng Ron Chen, Lan-Chou Cho, Chewnpu Jou, Fu-Lung Hsueh, Iman Madadi, Massoud Tohidian, Mina Shahmohammadi, Masoud Babaie, Robert Bogdan Staszewski
2016	—	`conf`	10.2 A 38mW 40Gb/s 4-lane tri-band PAM-4 / 16-QAM transceiver in 28nm CMOS for high-speed Memory interface. ISSCC Wei-Han Cho, Yilei Li, Yuan Du, Chien-Heng Wong, Jieqiong Du, Po-Tsang Huang, Sheau Jiung Lee, Huan-Neng Ron Chen, Chewnpu Jou, Fu-Lung Hsueh, Mau-Chung Frank Chang
2016	—	`conf`	2.1 An integrated 0.56THz frequency synthesizer with 21GHz locking range and -74dBc/Hz phase noise at 1MHz offset in 65nm CMOS. ISSCC Yan Zhao, Zuow-Zun Chen, Gabriel Virbila, Yinuo Xu, Richard Al Hadi, Yanghyo Kim, Adrian Tang, Theodore Reck, Huan-Neng Ron Chen, Chewnpu Jou, Fu-Lung Hsueh, Mau-Chung Frank Chang
2016	—	`conf`	6.8 A 1.5V 33Mpixel 3D-stacked CMOS image sensor with negative substrate bias. ISSCC Charles Chih-Min Liu, Manoj M. Mhala, Chin-Hao Chang, Honyih Tu, Po-Sheng Chou, Calvin Chao, Fu-Lung Hsueh
2016	—	`conf`	A Bluetooth low-energy (BLE) transceiver with TX/RX switchable on-chip matching network, 2.75mW high-IF discrete-time receiver, and 3.6mW all-digital transmitter. VLSI Circuits Feng-Wei Kuo, Sandro Binsfeld Ferreira, Masoud Babaie, Huan-Neng Ron Chen, Lan-Chou Cho, Chewnpu Jou, Fu-Lung Hsueh, Guanzhong Huang, Iman Madadi, Massoud Tohidian, Robert Bogdan Staszewski
2016	J	`jnl`	A Fully Integrated Bluetooth Low-Energy Transmitter in 28 nm CMOS With 36% System Efficiency at 3 dBm. IEEE J. Solid State Circuits Masoud Babaie, Feng-Wei Kuo, Huan-Neng Ron Chen, Lan-Chou Cho, Chewnpu Jou, Fu-Lung Hsueh, Mina Shahmohammadi, Robert Bogdan Staszewski
2016	—	`conf`	F5: Advanced IC design for ultra-low-noise sensing. ISSCC Makoto Ikeda, David Stoppa, Michiel A. P. Pertijs, Yusuke Oike, Maurits Ortmanns, Vadim Ivanov, Fu-Lung Hsueh
2015	—	`conf`	14.9 Sub-sampling all-digital fractional-N frequency synthesizer with -111dBc/Hz in-band phase noise and an FOM of -242dB. ISSCC Zuow-Zun Chen, Yen-Hsiang Wang, Jaewook Shin, Yan Zhao, Seyed Arash Mirhaj, Yen-Cheng Kuan, Huan-Neng Ron Chen, Chewnpu Jou, Ming-Hsien Tsai, Fu-Lung Hsueh, Mau-Chung Frank Chang
2015	—	`conf`	A 0.66e VLSIC Shang-Fu Yeh, Kuo-Yu Chou, Honyih Tu, Calvin Yi-Ping Chao, Fu-Lung Hsueh
2015	—	`conf`	A fully integrated 28nm Bluetooth Low-Energy transmitter with 36% system efficiency at 3dBm. ESSCIRC Feng-Wei Kuo, Masoud Babaie, Huan-Neng Ron Chen, Kyle Yen, Jinn-Yeh Chien, Lanchou Cho, Fred Kuo, Chewnpu Jou, Fu-Lung Hsueh, Robert Bogdan Staszewski
2014	—	`conf`	8.4 A 28Gb/s 1pJ/b shared-inductor optical receiver with 56% chip-area reduction in 28nm CMOS. ISSCC Tsung-Ching Huang, Tao-Wen Chung, Chan-Hong Chern, Ming-Chieh Huang, Chih-Chang Lin, Fu-Lung Hsueh
2014	—	`conf`	A 12mW all-digital PLL based on class-F DCO for 4G phones in 28nm CMOS. VLSIC Feng-Wei Kuo, Huan-Neng Ron Chen, Kyle Yen, Hsien-Yuan Liao, Chewnpu Jou, Fu-Lung Hsueh, Masoud Babaie, Robert Bogdan Staszewski
2014	—	`conf`	A peripheral switchable 3D stacked CMOS image sensor. VLSIC Charles Chih-Min Liu, Chin-Hao Chang, Honyih Tu, Calvin Yi-Ping Chao, Fu-Lung Hsueh, Szu-Ying Chen, Vincent Hsu, Jen-Cheng Liu, Dun-Nien Yaung, Shou-Gwo Wuu
2013	—	`conf`	A divider-less sub-harmonically injection-locked PLL with self-adjusted injection timing. ISSCC I-Ting Lee, Yen-Jen Chen, Shen-Iuan Liu, Chewnpu Jou, Fu-Lung Hsueh, Hsieh-Hung Hsieh
2013	—	`conf`	Session 11 overview: Emerging memory and wireless technology. ISSCC Fu-Lung Hsueh, Shinichiro Mutoh
2012	—	`conf`	A 2.7GHz 3.9mW Mesh-BJT LC-VCO with -204dBc/Hz FOM in 65nm CMOS. CICC Tao-Wen Chung, Tsung-Ching Huang, S. Chung, Ming-Chieh Huang, Chih-Chang Lin, Chan-Hong Chern, Fu-Lung Hsueh
2012	J	`jnl`	An Embedded Dynamic Voltage Scaling (DVS) System Through 55 nm Single-Inductor Dual-Output (SIDO) Switching Converter for 12-Bit Video Digital-to-Analog Converter. IEEE J. Solid State Circuits Wen-Shen Chou, Tzu-Chi Huang, Yu-Huei Lee, Yao-Yi Yang, Yi-Ping Su, Ke-Horng Chen, Chen-Chih Huang, Ying-Hsi Lin, Chao-Cheng Lee, Kuei-Ann Wen, Ying-Chih Hsu, Yung-Chow Peng, Fu-Lung Hsueh
2012	—	`conf`	Session 17 overview: Diagnostic and therapeutic technologies for health: Technology directions subcommittee. ISSCC Alison J. Burdett, Fu-Lung Hsueh
2011	—	`conf`	55nm CMOS 12-bit 250MHz digital-to-analog converter with dynamic voltage scaling (DVS) technique through single-inductor dual-output (SIDO) converter. ESSCIRC Tzu-Chi Huang, Wen-Shen Chou, Yu-Huei Lee, Yao-Yi Yang, Ke-Horng Chen, Yung-Chow Peng, Fu-Lung Hsueh
2011	—	`conf`	A 64-channel neuron recording system. EMBC Yi-Kai Lo, Wentai Liu, Kuanfu Chen, Ming-Hsien Tsai, Fu-Lung Hsueh
2011	—	`conf`	Analysis and design of data transmission protocol for 1024-channel retinal prosthesis. EMBC Kuanfu Chen, Ming-Hsien Tsai, Fu-Lung Hsueh, Wentai Liu
2010	—	`conf`	A 2.5-8Gb/s transceiver with 5-tap DFE and Second order CDR against 28-inch channel and 5000ppm SSC in 40nm CMOS technology. CICC Wei-Chih Chen, Chien-Chun Tsai, Chih-Hsien Chang, Yung-Chow Peng, Fu-Lung Hsueh, Tsung-Hsin Yu, Jinn-Yeh Chien, Wen-Hung Huang, Chi-Chang Lu, Mu-Shan Lin, Chin-Ming Fu, Shu-Chun Yang, Chung-Wing Wong, Wan-Te Chen, Chin-Hua Wen, Li Yueh Wang, Chiang Pu
2010	—	`conf`	A V-band divide-by-three differential direct injection-locked frequency divider in 65-nm CMOS. CICC Hsieh-Hung Hsieh, Fu-Lung Hsueh, Chewnpu Jou, Fred Kuo, Sean Chen, Tzu-Jin Yeh, Kevin Kai-Wen Tan, Po-Yi Wu, Yu-Ling Lin, Ming-Hsien Tsai
2010	—	`conf`	A practice of ESL verification methodology from SystemC to FPGA: using EPC class-1 generation-2 RFID tag design as an example. ASP-DAC W. M. Young, Chua-Huang Huang, Alan P. Su, Chewnpu Jou, Fu-Lung Hsueh
2007	C	`conf`	A Low-Cost Triple-Channel 10-bit 250MHz DAC IP in 65nm CMOS Process. ISCAS Wen-Shen Chou, Shu-Chieh Yang, Fu-Lung Hsueh, Heng-Chang Huang, Chih-Ji Hsiao