Friedel Gerfers

110 papers A 2C 31Journal 18Unranked 59

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	A 2×2 10GS/s TTD BF Receiver Utilizing Charge-Based Summation with 10.5GHz Bandwidth and SNDR/SFDR with 49.5dB/57.5dBc in 22nm CMOS. ISSCC Enne Wittenhagen, Dominik Wilding, Patrick J. Artz, Sebastian Linnhoff, Philipp Scholz, Friedel Gerfers
2025	J	`jnl`	A Behavioral Model for High-Speed 4:1 Analog Multiplexers, Utilizing Stochastic Modelfitting. IEEE Trans. Circuits Syst. II Express Briefs Jonathan Andree, Giresse T. Belinga Tamokeu, Samuel Wazynski, Markus Grözing, Christian Schmidt, Markus Nölle, Volker Jungnickel, Georg Rademacher, Ronald Freund, Friedel Gerfers
2025	—	`conf`	A DAC-based Transmitter with VCSEL Bias-Current Generation enabling 180 Gbit/s PAM-8 Electrical and 100 Gbit/s PAM-4 VCSEL-based Transmission in 22nm SOI. CICC Urs Hecht, Philipp Scholz, Patrick Kurth, Frowin Buballa, Helia Ordouei, Friedel Gerfers
2025	C	`conf`	A Nyquist-rate 128 GS/s 6-Bit 64x Time-Interleaved SAR ADC in 22nm FD-SOI. ISCAS Christian Rudorf, Nima Lotfi, Sebastian Linnhoff, Enne Wittenhagen, Äantas Kesten, Friedel Gerfers
2025	C	`conf`	A Wideband Open-Loop Residue Amplifier for a 7-bit 10GS/s Two-Step Flash ADC in 22nm SOI CMOS Process. ISCAS Jenny Lichtenstein, Äantas Kesten, Friedel Gerfers
2025	C	`conf`	Halfbex: A RISC-V Microarchitecture with Narrow Data Path for Improved Energy Efficiency. ISCAS Äantas Kesten, Tobias Kaiser, Jenny Lichtenstein, Christian Rudorf, Friedel Gerfers
2025	J	`jnl`	Halfbex: RISC-V Narrow Data Path Optimization for Energy Reduction. IEEE Trans. Circuits Syst. II Express Briefs Äantas Kesten, Tobias Kaiser, Jenny Lichtenstein, Christian Rudorf, Friedel Gerfers
2025	J	`jnl`	Pasithea-1: An Energy-Efficient Sequential Reconfigurable Array With CPU-Like Programmability. IEEE Open J. Circuits Syst. Tobias Kaiser, Esther Gottschalk, Kai Biethahn, Friedel Gerfers
2024	C	`conf`	A 16 GS/s Voltage-to-Time Conversion Sampler with 35.9 dB SNDR in 22 nm CMOS FDSOI. ISCAS Kai Misselwitz, Friedel Gerfers
2024	J	`jnl`	A Multiport Coaxial Interconnection for MTCA.4 Based High-Frequency Instrumentation Applications. IEEE Trans. Instrum. Meas. Johannes Zink, Frank Ludwig, Szymon Jablonski, Uros Mavric, Michael Fenner, Stanislav Chystiakov, Holger Schlarb, Friedel Gerfers
2024	C	`conf`	A mmw Low-Noise Sub-Sampling Phase-Locked Loop with a Non-Pulsed Charge Pump, Frequency Calibration and a Compact Ultra-High-Q Resonator. ISCAS Patrick Kurth, Philipp Scholz, Philipp Nickel, Urs Hecht, Enne Wittenhagen, Kai Misselwitz, Friedel Gerfers
2024	C	`conf`	An 11-Bit 12 GS/s Beam-Forming Receiver ADC for a 2x2 Antenna Array utilizing True Time-Delay with 68 dBc SFDR and 55 dB SNDR. ISCAS Enne Wittenhagen, Dominik Wilding, Patrick Kurth, Sebastian Linnhoff, Frowin Buballa, Urs Hecht, Patrick J. Artz, Friedel Gerfers
2023	C	`conf`	25Gbps Automotive Ethernet ECU PCB: MDI Design Implementation and Insertion Loss Characterization. VEHITS Jamila Josip Borda, Kirsten Matheus, Friedel Gerfers
2023	C	`conf`	25Gbps Automotive Ethernet: System PHY Characterization of ESD Based EM Interferences. ETFA Jamila Josip Borda, Friedel Gerfers
2023	—	`conf`	A 0.4 pJ/bit NRZ Voltage Mode VCSEL Driver for up to 224 Gbit/s SWDM Links. OFC Urs Hecht, Helia Ordouei, Nikolay Ledentsov Jr., Philipp Scholz, Patrick Kurth, Ilya E. Titkov, Nikolay N. Ledentsov, Friedel Gerfers
2023	—	`conf`	A 10Bit 6 GS/s Time-Interleaved SAR ADC with a Single Full-Rate Front-End Track-and-Hold. NEWCAS Sebastian Linnhoff, Frowin Buballa, Julius Edler, Enne Wittenhagen, Urs Hecht, Friedel Gerfers
2023	—	`conf`	A 12 GS/s RF-Sampler Employing Inductive Peaking with >57 dB \|THD\| and >49.3 dB SNDR in 22 nm FD-SOI CMOS. NEWCAS Enne Wittenhagen, Patrick Kurth, Urs Hecht, Frowin Buballa, Sebastian Linnhoff, Nima Lotfi, Friedel Gerfers
2023	—	`conf`	A 2.41-μW/MHz, 437-PE/mm COOL CHIPS Tobias Kaiser, Friedel Gerfers
2023	—	`conf`	A 4 GBaud 5 Vpp Class-B Pre-Driver Design for GaN-Based Switching Power Amplifier in 22 nm SOI-CMOS Utilizing LDMOS. NEWCAS Frowin Buballa, Sebastian Linnhoff, Enne Wittenhagen, Urs Hecht, Friedel Gerfers
2023	—	`conf`	A 4.4 GS/s 220 MHz ΣΔ ADC with a Linearized Back-Gate Controlled GmC Filter. VLSI Technology and Circuits Julius Edler, Marcel Runge, Sebastian Linnhoff, Friedel Gerfers
2023	C	`conf`	A Charge Pump for Sub-Sampling Phase-Locked Loops with Virtual Reference Frequency Doubling. ISCAS Patrick Kurth, Urs Hecht, Frowin Buballa, Sebastian Linnhoff, Helia Ordouei, Friedel Gerfers
2023	C	`conf`	A Digital Pre-Distortion Technique Canceling Code-and Voltage-Dependent Output Impedance Errors in Current-Steering DACs. ISCAS Helia Ordouei, Clirim Alija, Patrick Kurth, Friedel Gerfers
2023	J	`jnl`	An 18-MS/s 76-dB SNDR Continuous-Time Δ Σ Modulator Incorporating an Input Voltage Tracking GmC Loop Filter. IEEE J. Solid State Circuits Marcel Runge, Julius Edler, Tobias Kaiser, Kai Misselwitz, Friedel Gerfers
2023	—	`conf`	True Voltage-Mode NRZ VCSEL Transmitter enabling 60 Gbit/s at 0.37 pJ/bit in 22 nm FDSOI. ESSCIRC Urs Hecht, Helia Ordouei, Nikolay Ledentsov Jr., Philipp Scholz, Patrick Kurth, Nikolay N. Ledentsov, Friedel Gerfers
2023	—	`conf`	Undersampling and SNR Degradation in Practical Direct RF Sampling Systems. EuCNC/6G Summit Dennis Osterland, Andreas Benzin, Friedel Gerfers, Giuseppe Caire
2022	—	`conf`	6G D-Band Receiver Model with High Spectral Efficiency Enabling Global System Optimization. MWSCAS Patrick J. Artz, Friedel Gerfers
2022	—	`conf`	A 224 Gbit/s Transceiver Front-end Design for Next Generation Data Centers. ICECS 2022 Enne Wittenhagen, Urs Hecht, Halil Cirit, Saman Behtash, Srinivas Venkataram, Friedel Gerfers
2022	—	`conf`	A 30-MHz BW 74.6-dB SNDR 92-dB SFDR CT ΔΣ Modulator with Active Body-Bias DAC Calibration in 22nm FDSOI CMOS. CICC Marcel Runge, Julius Edler, Dario Schmock, Tobias Kaiser, Friedel Gerfers
2022	—	`conf`	A Calibration-Free 96.7 dB SNDR 4 MS/s CT I-SD Modulator With Single Feedback DAC. ICECS 2022 Kai Misselwitz, Marcel Runge, Friedel Gerfers
2022	—	`conf`	A Divider-less General PLL Lock Assist and Automatic Frequency Calibration System for Millimeter-Wave Sub-Sampling Phase-Locked Loops. ICECS 2022 Patrick Kurth, Philipp Nickel, Urs Hecht, Friedel Gerfers
2022	—	`conf`	A TI 12 GS/s Sampled Beam-Forming Receiver for a $2\times 2$ Antenna-Array with 69 dBc SFDR. ICECS 2022 Enne Wittenhagen, Patrick Kurth, Tobias Kaiser, Friedel Gerfers
2022	C	`conf`	A novel OFDM-based Radar and Communication System Design using Digital IQ-Modulation and 52 GS/s Direct-RF Data Converter. ISCAS Silvio Waldmann, Helia Ordouei, Friedel Gerfers
2022	C	`conf`	Beyond 10Gbps Electrical Automotive Ethernet Channel Insertion Loss Characterization. IV Jamila Josip Borda, Kirsten Matheus, Friedel Gerfers
2022	C	`conf`	Characterization of Multi-Gigabit Automotive Ethernet Channel Radiated Emissions in Relation to ECU PCB Shield-Ground Implementations. ETFA Jamila Josip Borda, Kirsten Matheus, Friedel Gerfers
2022	C	`conf`	In-Vehicle Network Standards - Overview and Implementation Examples. ISCAS Helia Ordouei, Friedel Gerfers, Silvio Waldmann
2022	C	`conf`	PAM-4/6/8 Performance and Power Analysis for Next Generation 224Gbit/s Links. ISCAS Urs Hecht, Enne Wittenhagen, Halil Cirit, Saman Behtash, Srinivas Venkataram, Friedel Gerfers
2022	—	`conf`	Pasithea-1: An Energy-Efficient Self-contained CGRA with RISC-Like ISA. ARCS Tobias Kaiser, Friedel Gerfers
2022	—	`conf`	Sturdy-MASH Delta-Sigma Modulator with Improved Resolution Using Noise-coupling Multi-bit Quantizer. MWSCAS Akif Omer Ucar, Friedel Gerfers
2021	—	`conf`	A 0.9V 45MS/s CT ΔΣ Modulator with 94dB SFDR and 25.6fJ/conv. enabled by a Digital Static and ISI Calibration in 22 FDSOI CMOS. CICC Marcel Runge, Dario Schmock, Tobias Kaiser, Friedel Gerfers
2021	C	`conf`	A 12 Bit 500 MS/s Sub-2 Radix SAR ADC for a Time-Interleaved 8 GS/s ADC in 28 nm CMOS. ISCAS Frowin Buballa, Sebastian Linnhoff, Michael Reinhold, Friedel Gerfers
2021	C	`conf`	A 12 Bit 8 GS/s Randomly-Time-Interleaved SAR ADC with Adaptive Mismatch Correction. ISCAS Sebastian Linnhoff, Erik Sippel, Frowin Buballa, Michael Reinhold, Martin Vossiek, Friedel Gerfers
2021	—	`conf`	A 18MS/s 76dB SNDR 93dB SFDR CT ΔΣ Modulator with Input Voltage Tracking 2nd-Order GmVC Filter and Shared FIR DAC in 22nm FDSOI CMOS. CICC Marcel Runge, Julius Edler, Tobias Kaiser, Friedel Gerfers
2021	C	`conf`	A 56 GHz 19 fs RMS-Jitter Sub-Sampling Phase-Locked Loop for 112 Gbit/s Transceivers. ISCAS Patrick Kurth, Kai Misselwitz, Urs Hecht, Friedel Gerfers
2021	—	`conf`	A Divider-less Automatic Frequency Calibration for Millimeter-Wave Sub-Sampling Phase-Locked Loops. MWSCAS Patrick Kurth, Urs Hecht, Enne Wittenhagen, Friedel Gerfers
2021	—	`conf`	A Dynamic Body-Bias Linearization Technique Enabling Wide-Band GmC based Continous-Time Sigma-Delta Converters in 22 nm FD-SOI CMOS. MWSCAS Julius Edler, Marcel Runge, Friedel Gerfers
2021	J	`jnl`	A Power Efficiency Enhancements of a Multi-Bit Accelerator for Memory Prohibitive Deep Neural Networks. IEEE Open J. Circuits Syst. Suhas Shivapakash, Hardik Jain, Olaf Hellwich, Friedel Gerfers
2021	J	`jnl`	Advanced Mixed Signal Concepts Exploiting the Strong Body-Bias Effect in CMOS 22FDX IEEE Trans. Circuits Syst. I Regul. Pap. Enne Wittenhagen, Marcel Runge, Nima Lotfi, Hossein Ghafarian, Yuan Tian, Friedel Gerfers
2021	J	`jnl`	FantastIC4: A Hardware-Software Co-Design Approach for Efficiently Running 4Bit-Compact Multilayer Perceptrons. IEEE Open J. Circuits Syst. Simon Wiedemann, Suhas Shivapakash, Daniel Becking, Pablo Wiedemann, Wojciech Samek, Friedel Gerfers, Thomas Wiegand
2021	J	`jnl`	Introduction to the Special Issue on the 2020 IEEE International Solid-State Circuits Conference (ISSCC). IEEE J. Solid State Circuits Friedel Gerfers, Ping-Hsuan Hsieh, Dejan Markovic, Jun Deguchi, Eric Karl
2020	—	`conf`	A 12 bit 8 GS/s Time-Interleaved SAR ADC in 28nm CMOS. ICECS Sebastian Linnhoff, Frowin Buballa, Michael Reinhold, Friedel Gerfers
2020	—	`conf`	A 64 GBaud 6-Bit Current Steering DAC With a Binary Tree Current Summing Network. ICECS Paul Hollmann, Marcel Runge, Friedel Gerfers
2020	C	`conf`	A DAC Linearization Technique Enabling 15-Bit INL through Adaptive Body-Biasing in 22FDX. ISCAS Marcel Runge, Dario Schmock, Enne Wittenhagen, Friedel Gerfers
2020	C	`conf`	A Power Efficient Multi-Bit Accelerator for Memory Prohibitive Deep Neural Networks. ISCAS Suhas Shivapakash, Hardik Jain, Olaf Hellwich, Friedel Gerfers
2020	C	`conf`	A Sub-Sampling Beam-Forming Summation Track and Hold for Software Defined Radio. ISCAS Enne Wittenhagen, Marcel Runge, Wilhelm Keusgen, Friedel Gerfers
2020	—	`conf`	A Transmission-Line-based Phase Shifter for High-Speed, Ultra-Low-Power N-PSK Transmitters. ICECS Patrick Kurth, Kai Misselwitz, Urs Hecht, Friedel Gerfers
2020	J	`jnl`	FantastIC4: A Hardware-Software Co-Design Approach for Efficiently Running 4bit-Compact Multilayer Perceptrons. CoRR Simon Wiedemann, Suhas Shivapakash, Pablo Wiedemann, Daniel Becking, Wojciech Samek, Friedel Gerfers, Thomas Wiegand
2020	—	`conf`	Optical Interconnects using Single-Mode and Multi-Mode VCSEL and Multi-Mode Fiber. OFC Nikolay N. Ledentsov, V. A. Shchukin, Vladimir P. Kalosha, Nikolay Ledentsov Jr., Lukasz Chorchos, Jaroslaw P. Turkiewicz, Urs Hecht, Patrick Kurth, Friedel Gerfers, Justin Lavrencik, Siddharth Varughese, Stephen E. Ralph
2020	C	`conf`	Towards pW-Class IoT Nodes using Crystalline Oxide Semiconductor Dynamic Logic. ISCAS Tobias Kaiser, Friedel Gerfers
2020	—	`conf`	Up to 30-Fold BER Improvement using a Data-Dependent FFE Switching Technique for 112Gbit/s PAM-4 VCSEL Based Links. OFC Urs Hecht, Nikolay Ledentsov Jr., Lukasz Chorchos, Patrick Kurth, Nikolay N. Ledentsov, Friedel Gerfers
2019	—	`conf`	A CMOS-Based Electrochemical DNA Hybridization Microarray for Diagnostic Applications with 109 Test Sites. BioCAS Norman Dodel, Roland Thewes, Anouar Laifi, Dirk Eberhardt, Stefan Keil, Leonhard Sturm, Armin Klumpp, Oliver Freudenberg, Friedel Gerfers, Gerhard Hartwich
2019	C	`conf`	A Single-Channel 18.5 GS/s 5-bit Flash ADC using a Body-Biased Comparator Architecture in 22nm FD-SOI. ISCAS Nima Lotfi, Pedro Lehmann Ibáñez, Marcel Runge, Friedel Gerfers
2019	—	`conf`	An UWB 18.5 GS/s Sampling Front-End for a 74 GS/s 5-bit ADC in 22nm FDSOI. NEWCAS Nima Lotfi, Friedel Gerfers
2019	—	`conf`	Body-Bias Techniques in CMOS 22FDX® for Mixed-Signal Circuits and Systems. ICECS Friedel Gerfers, Nima Lotfi, Enne Wittenhagen, Hossein Ghafarian, Yuan Tian, Marcel Runge
2019	C	`conf`	High Performance Electronic Design Education - from Technology towards High Frequency Chip Sets. FIE Andreas Mai, Philipp Scholz, Gerhard G. Fischer, Friedel Gerfers
2019	—	`conf`	Impedance Calibration Technique Canceling Process and Temperature Variation in Source Terminated DAC Drivers in 22nm FDSOI. MWSCAS Hossein Ghafarian, Helia Ordouei, Friedel Gerfers
2019	C	`conf`	Optimized Zero Placement within Noise Coupling Transfer Functions for Oversampled ADCs. ISCAS Marcel Runge, Nima Lotfi, Friedel Gerfers
2018	—	`conf`	A 0.02-mm2 9-bit 100-MS/s Charge-Injection Cell Based SAR-ADC in 65-nm LP CMOS. ESSCIRC Marcel Runge, Dario Schmock, Philipp Scholz, Georg Böck, Friedel Gerfers
2018	—	`conf`	A Temperature and Process Corner Insensitive Design Method for Digital Circuits in 40nm CMOS. MWSCAS Marcel Runge, Sebastian Linnhoff, Friedel Gerfers
2018	—	`conf`	AMDAC Common-Mode Shifting Technique enabling Power Consumption Reduction in Pipeline ADCs. MWSCAS Nima Lotfi, Marcel Runge, Friedel Gerfers
2018	—	`conf`	Analysis of Package Impedance Effects on the Linearity of Source Series Terminated DACs. MWSCAS Helia Ordouei, Hossein Ghafarian, Friedel Gerfers
2018	—	`conf`	Behavioral Model for a High-Speed 2: 1 Analog Multiplexer. MWSCAS Christian Schmidt, Patrick Zielonka, Volker Jungnickel, Ronald Freund, Tobias Tannert, Markus Grozing, Manfred Berroth, Friedel Gerfers
2018	C	`conf`	Correlation Based Time-Variant DAC Error Estimation in Continuous-Time ∑Δ ADCs With Pseudo Random Noise. ISCAS Marcel Runge, Friedel Gerfers
2018	J	`jnl`	Digital-to-Analog Converters Using Frequency Interleaving: Mathematical Framework and Experimental Verification. Circuits Syst. Signal Process. Christian Schmidt, Christoph Kottke, Vicky H. Tanzil, Ronald Freund, Volker Jungnickel, Friedel Gerfers
2017	C	`conf`	A digital calibration technique canceling non-linear switch and package impedance effects of a 1.6GS/s TX-DAC in 28 nm CMOS. ISCAS Hossein Ghafarian, Friedel Gerfers
2017	C	`conf`	A digital compensation method canceling static and non-linear time-variant feedback DAC errors in ΣΔ analog-to-digital converters. ISCAS Marcel Runge, Friedel Gerfers
2017	—	`conf`	Analysis and compensation technique canceling non-linear switch and package impedance effects of a 3.2GS/S TX-DAC. MWSCAS Hossein Ghafarian, Friedel Gerfers
2017	—	`conf`	Channel analysis for a 6.4 Gb/s DDR5 data buffer receiver front-end. NEWCAS Stefanie Lehmann, Friedel Gerfers
2017	—	`conf`	High output power frequency doubler for digital PLLs in fully integrated 24 GHz CMOS radar systems. ICUWB Soenke Vehring, Yaoshun Ding, Philipp Scholz, Dominic Maurath, Friedel Gerfers, Georg Böck
2017	—	`conf`	Link-budget calculations for CMOS integrated microwave receivers. EUROCON Soenke Vehring, Yaoshun Ding, Dominic Maurath, Friedel Gerfers, Georg Böck
2017	—	`conf`	Noise and non-linearity analysis of a charge-injection-cell-based 10-bit 50-MS/s SAR-ADC. MWSCAS Marcel Runge, Dario Schmock, Friedel Gerfers
2016	C	`conf`	Implementation and design investigation of 40 Gbps driver IC for silicon photonics ring-modulator in SiGe 130-nm. ISCAS Adel Fatemi, Heinrich Klar, Friedel Gerfers
2012	—	`conf`	A 16-port FCC-compliant 10GBase-T transmitter and hybrid with 76dBc SFDR up to 400MHz scalable to 48 ports. ISSCC Friedel Gerfers, Ramin Farjad-Rad, Michael Brown, Ahmad Tavakoli, David Nguyen, Hiok-Tiaq Ng, Ramin Shirani
2012	J	`jnl`	A 48-Port FCC-Compliant 10GBASE-T Transmitter With Mixed-Mode Adaptive Echo Canceller. IEEE J. Solid State Circuits Ramin Farjad-Rad, Friedel Gerfers, Michael Brown, Ahmad Tavakoli, David Nguyen, Hossein Sedarat, Ramin Shirani, Hiok-Tiaq Ng
2008	J	`jnl`	A 0.2-2 Gb/s 6x OSR Receiver Using a Digitally Self-Adaptive Equalizer. IEEE J. Solid State Circuits Friedel Gerfers, Gerrit W. den Besten, Pavel V. Petkov, Jim E. Conder, Andreas J. Koellmann
2007	J	`jnl`	On the Implicit Anti-Aliasing Feature of Continuous-Time Cascaded Sigma-Delta Modulators. IEEE Trans. Circuits Syst. I Regul. Pap. Matthias Keller, Alexander Buhmann, Friedel Gerfers, Maurits Ortmanns, Yiannos Manoli
2006	C	`conf`	A transistor-based clock jitter insensitive DAC architecture. ISCAS Friedel Gerfers, Maurits Ortmanns, P. Schmitz
2006	C	`conf`	An infinite-skew tolerant delay locked loop. ISCAS Pavel V. Petkov, Jim E. Conder, Friedel Gerfers
2005	J	`jnl`	A Case Study on a 2-1-1 Cascaded Continuous-Time Sigma-Delta Modulator. IEEE Trans. Circuits Syst. I Regul. Pap. Maurits Ortmanns, Friedel Gerfers, Yiannos Manoli
2005	J	`jnl`	A continuous-time ΣΔ Modulator with reduced sensitivity to clock jitter through SCR feedback. IEEE Trans. Circuits Syst. I Regul. Pap. Maurits Ortmanns, Friedel Gerfers, Yiannos Manoli
2005	—	`conf`	A new technique for automatic error correction in Sigma-Delta modulators. ISCAS (3) Friedel Gerfers, Maurits Ortmanns, Yiannos Manoli
2005	—	`conf`	Increased jitter sensitivity in continuous- and discrete-time Sigma-Delta modulators due to finite opamp settling speed. ISCAS (3) Friedel Gerfers, Maurits Ortmanns, Yiannos Manoli
2004	—	`conf`	A calibration method for current steering digital to analog converters in continuous time multi-bit sigma delta modulators. ISCAS (1) Matthias Keller, Yiannos Manoli, Friedel Gerfers
2004	—	`conf`	A cascaded continuous-time Sigma Delta modulator with 80 dB dynamic range. ISCAS (1) Maurits Ortmanns, Markus Kuderer, Yiannos Manoli, Friedel Gerfers
2004	J	`jnl`	Compensation of finite gain-bandwidth induced errors in continuous-time sigma-delta modulators. IEEE Trans. Circuits Syst. I Regul. Pap. Maurits Ortmanns, Friedel Gerfers, Yiannos Manoli
2004	—	`conf`	Design issues and performance limitations of a clock jitter insensitive multibit DAC architecture for high-performance low-power CT Sigma Delta modulators. ISCAS (1) Friedel Gerfers, Maurits Ortmanns, Yiannos Manoli
2003	—	`conf`	A 1 V, 12-bit wideband continuous-time ΣΔ modulator for UMTS applications. ISCAS (1) Friedel Gerfers, Maurits Ortmanns, Yiannos Manoli
2003	J	`jnl`	A 1.5-V 12-bit power-efficient continuous-time third-order ΣΔ modulator. IEEE J. Solid State Circuits Friedel Gerfers, Maurits Ortmanns, Yiannos Manoli
2003	—	`conf`	A clock jitter insensitive multibit DAC architecture for high-performance low-power continuous-time ΣΔ modulators. ICECS Friedel Gerfers, Maurits Ortmanns, P. Schmitz, Yiannos Manoli, Kian Min Soh
2003	—	`conf`	A continuous-time sigma-delta modulator with switched capacitor controlled current mode feedback. ESSCIRC Maurits Ortmanns, Friedel Gerfers, Yiannos Manoli
2003	—	`conf`	Compensation of the influence of finite gain-bandwidth on continuous-time sigma-delta modulators. ICECS Maurits Ortmanns, Friedel Gerfers, Yiannos Manoli
2003	—	`conf`	Fundamental limits of jitter insensitivity in discrete and continuous-time sigma delta modulators. ISCAS (1) Maurits Ortmanns, Friedel Gerfers, Yiannos Manoli
2003	—	`conf`	Influence of finite integrator gain bandwidth on continuous-time sigma delta modulators. ISCAS (1) Maurits Ortmanns, Friedel Gerfers, Yiannos Manoli
2002	—	`conf`	A new kind of low-power multibit third order continuous-time lowpass Sigma-Delta modulator. ISCAS (3) Lourans Samid, Maurits Ortmanns, Yiannos Manoli, Friedel Gerfers
2002	—	`conf`	Figure of merit based design strategy for low-power continuous-time Sigma-Delta modulators. ISCAS (4) Friedel Gerfers, Kian Min Soh, Maurits Ortmanns, Yiannos Manoli
2002	—	`conf`	Multirate cascaded continuous time Sigma-Delta modulators. ISCAS (4) Maurits Ortmanns, Lourans Samid, Yiannos Manoli, Friedel Gerfers
2001	A	`conf`	A design strategy for low-voltage low-power continuous-time sigma-delta A/D converters. DATE Friedel Gerfers, Yiannos Manoli
2001	—	`conf`	Clock jitter insensitive continuous-time ΣΔ modulators. ICECS Maurits Ortmanns, Friedel Gerfers, Yiannos Manoli
2001	—	`conf`	On the synthesis of cascaded continuous-time Sigma-Delta modulators. ISCAS (5) Maurits Ortmanns, Friedel Gerfers, Yiannos Manoli
2001	—	`conf`	Successful design of cascaded continuous-time ΣΔ modulators. ICECS Maurits Ortmanns, Friedel Gerfers, Lourans Samid, Yiannos Manoli
2000	A	`conf`	A 1.5V low-power third order continuous-time lowpass Sigma-Delta A/D converter (poster session). ISLPED Friedel Gerfers, Yiannos Manoli