François Marc

33 papers B 1C 7Journal 21Unranked 4
YearRankTypeTitle / Venue / Authors
2022 C conf
Analysis of an Inverter Logic Cell based on 3D Vertical NanoWire Junction-Less Transistors.
VLSI-SoC
Lucas Réveil, Chhandak Mukherjee, Cristell Maneux, Marina Deng, François Marc, Abhishek Kumar, Aurélie Lecestre, Guilhem Larrieu, Arnaud Poittevin, Ian O'Connor, Oskar Baumgartner, David Pirker
2021 — conf
Electro-Thermal Limitations and Device Degradation of SiGe HBTs with Emphasis on Circuit Performance.
BCICTS
Sébastien Fregonese, Chhandak Mukherjee, Holger Rücker, Pascal Chevalier, Gerhard Fischer, Didier Céli, Marina Deng, Marine Couret, François Marc, Cristell Maneux, Thomas Zimmer
2020 C conf
3D Logic Cells Design and Results Based on Vertical NWFET Technology Including Tied Compact Model.
VLSI-SOC
Chhandak Mukherjee, Marina Deng, François Marc, Cristell Maneux, Arnaud Poittevin, Ian O'Connor, Sébastien Le Beux, Cédric Marchand, Abhishek Kumar, Aurélie Lecestre, Guilhem Larrieu
2020 — conf
3D Logic Cells Design and Results Based on Vertical NWFET Technology Including Tied Compact Model.
VLSI-SoC (Selected Papers)
Arnaud Poittevin, Chhandak Mukherjee, Ian O'Connor, Cristell Maneux, Guilhem Larrieu, Marina Deng, Sébastien Le Beux, François Marc, Aurélie Lecestre, Cédric Marchand, Abhishek Kumar
2020 J jnl
3D logic cells design and results based on Vertical NWFET technology including tied compact model.
CoRR
C. Mukherjee, Marina Deng, François Marc, Cristell Maneux, Arnaud Poittevin, Ian O'Connor, Sébastien Le Beux, Abhishek Kumar, Aurélie Lecestre, Guilhem Larrieu
2019 — conf
Impact of SiGe HBT hot-carrier degradation on the broadband amplifier output supply current.
ESSDERC
Marine Couret, Gerhard Fischer, Iria Garcia-Lopez, Magali De Matos, François Marc, Cristell Maneux
2018 J jnl
Influence of temperature of storage, write and read operations on multiple level cells NAND flash memories.
Microelectron. Reliab.
Julien Coutet, François Marc, Flavien Dozolme, Romain Guétard, Aurélien Janvresse, Pierre Lebossé, Antonin Pastre, Jean-Claude Clement
2018 J jnl
Multiscaled Simulation Methodology for Neuro-Inspired Circuits Demonstrated with an Organic Memristor.
IEEE Trans. Multi Scale Comput. Syst.
Christopher H. Bennett, Jean-Etienne Lorival, François Marc, Theo Cabaret, Bruno Jousselme, Vincent Derycke, Jacques-Olivier Klein, Cristell Maneux
2018 J jnl
Simulation and modelling of long term reliability of digital circuits implemented in FPGA.
Microelectron. Reliab.
Jorgue Daniel Aguirre Morales, François Marc, A. Bensoussan, A. Durier
2017 J jnl
Proceedings of the 28th European Symposium on the reliability of electron devices, failure physics and analysis.
Microelectron. Reliab.
Nathalie Labat, François Marc, Hélène Frémont, Marise Bafleur
2016 J jnl
FPGA LUT delay degradation due to HCI: Experiment and simulation results.
Microelectron. Reliab.
Mohammad Naouss, François Marc
2016 B conf
Modelling delay degradation due to NBTI in FPGA Look-up tables.
FPL
Mohammad Naouss, François Marc
2015 J jnl
Design and implementation of a low cost test bench to assess the reliability of FPGA.
Microelectron. Reliab.
Mohammad Naouss, François Marc
2015 J jnl
Editorial.
Microelectron. Reliab.
Marise Bafleur, Philippe Perdu, François Marc, Hélène Frémont, Nicolas Nolhier
2013 J jnl
Editorial.
Microelectron. Reliab.
Nathalie Labat, François Marc
2013 J jnl
On the Simulation of HCI-Induced Variations of IC Timings at High Level.
J. Electron. Test.
Olivier Héron, Clement Bertolini, Chiara Sandionigi, Nicolas Ventroux, François Marc
2012 — conf
Advancements on reliability-aware analog circuit design.
ESSCIRC
Bertrand Ardouin, Jean-Yves Dupuy, Jean Godin, Virginie Nodjiadjim, Muriel Riet, François Marc, Gilles Amadou Koné, Sudip Ghosh, Brice Grandchamp, Cristell Maneux
2012 J jnl
Impact of Power Consumption and Temperature on Processor Lifetime Reliability.
J. Low Power Electron.
Tushar Gupta, Clement Bertolini, Olivier Héron, Nicolas Ventroux, Thomas Zimmer, François Marc
2012 C conf
Relation between HCI-induced performance degradation and applications in a RISC processor.
IOLTS
Clement Bertolini, Olivier Héron, Nicolas Ventroux, François Marc
2011 J jnl
Editorial.
Microelectron. Reliab.
Nathalie Labat, François Marc
2011 J jnl
Investigation of the degradation mechanisms of InP/InGaAs DHBT under bias stress conditions to achieve electrical aging model for circuit design.
Microelectron. Reliab.
Sudip Ghosh, Brice Grandchamp, G. A. Koné, François Marc, Cristell Maneux, Thomas Zimmer, Virginie Nodjiadjim, Muriel Riet, Jean-Yves Dupuy, Jean Godin
2011 J jnl
Reliability of submicron InGaAs/InP DHBT under thermal and electrical stresses.
Microelectron. Reliab.
G. A. Koné, Brice Grandchamp, C. Hainaut, François Marc, Cristell Maneux, Nathalie Labat, Thomas Zimmer, Virginie Nodjiadjim, Muriel Riet, Jean Godin
2010 C conf
High Level Power and Energy Exploration Using ArchC.
SBAC-PAD
Tushar Gupta, Clement Bertolini, Olivier Héron, Nicolas Ventroux, Thomas Zimmer, François Marc
2010 J jnl
Preliminary results of storage accelerated aging test on InP/InGaAs DHBT.
Microelectron. Reliab.
G. A. Koné, Brice Grandchamp, C. Hainaut, François Marc, Cristell Maneux, Nathalie Labat, Thomas Zimmer, Virginie Nodjiadjim, Jean Godin
2010 J jnl
Thermal aging model of InP/InGaAs/InP DHBT.
Microelectron. Reliab.
Sudip Ghosh, François Marc, Cristell Maneux, Brice Grandchamp, G. A. Koné, Thomas Zimmer
2009 J jnl
Electrical aging behavioral modeling for reliability analyses of ionizing dose effects on an n-MOS simple current mirror.
Microelectron. Reliab.
Corinne Bestory, François Marc, S. Duzellier, Hervé Levi
2007 J jnl
Statistical analysis during the reliability simulation.
Microelectron. Reliab.
Corinne Bestory, François Marc, Hervé Levi
2006 C conf
Multi-level Modeling of Hot Carrier Injection for Reliability.
FDL
Corinne Bestory, François Marc, Hervé Levi, Yves Danto
2004 J jnl
Reliability of Low-Cost PCB Interconnections for Telecommunication Applications.
Microelectron. Reliab.
Geneviève Duchamp, Frédéric Verdier, Yannick Deshayes, François Marc, Yves Ousten, Yves Danto
2003 J jnl
Ageing simulation of MOSFET circuit using a VHDL-AMS behavioural modelling: an experimental case study.
Microelectron. Reliab.
B. Mongellaz, François Marc, Yves Danto
2003 C conf
Reliability simulation of electronic circuits with VHDL-AMS.
FDL
François Marc, B. Mongellaz, Yves Danto
2002 J jnl
Contribution to ageing simulation of complex analogue circuit using VHDL-AMS behavioural modelling language.
Microelectron. Reliab.
B. Mongellaz, François Marc, Noëlle Milet-Lewis, Yves Danto
2000 C conf
Genetic algorithm optimisation for evanescent mode waveguide filter design.
ISCAS
Marc Lecouve, Pierre Jarry, Eric Kerherve, Nicolas Boutheiller, François Marc