François Anceau

15 papers C 5Journal 1Unranked 8

Year	Rank	Type	Title / Venue / Authors
2019	J	`jnl`	Synchronized Interconnected ADPLLs for Distributed Clock Generation in 65 nm CMOS Technology. IEEE Trans. Circuits Syst. II Express Briefs Dimitri Galayko, Chuan Shan, Eldar Zianbetov, Mohammad Javidan, Anton Korniienko, François Anceau, Olivier Billoint, Éric Colinet, Elena Blokhina, Jérôme Juillard
2015	—	`conf`	A distributed synchronization of all-digital PLLs network for clock generation in synchronous SOCs. NEWCAS Chuan Shan, Eldar Zianbetov, François Anceau, Olivier Billoint, Dimitri Galayko
2014	C	`conf`	"Swimming pool"-like distributed architecture for clock generation in large many-core SoC. ISCAS Chuan Shan, François Anceau, Dimitri Galayko, Eldar Zianbetov
2014	—	`conf`	A reconfigurable distributed architecture for clock generation in large many-core SoC. ReCoSoC Chuan Shan, Dimitri Galayko, François Anceau, Eldar Zianbetov
2014	C	`conf`	Complexity in heterogeneous systems on chips: Dsign and analysis challenges. ISCAS Dimitri Galayko, Elena Blokhina, Eldar Zianbetov, Andrii Dudka, François Anceau, Éric Colinet, Anton Korniienko, Jérôme Juillard, Philippe Basset
2013	—	`conf`	Distributed clock generator for synchronous SoC using ADPLL network. CICC Eldar Zianbetov, Dimitri Galayko, François Anceau, Mohammad Javidan, Chuan Shan, Olivier Billoint, Anton Korniienko, Éric Colinet, Gérard Scorletti, J. M. Akrea, Jérôme Juillard
2013	—	`conf`	FPGA prototyping of large reconfigurable ADPLL network for distributed clock generation. ReConFig Chuan Shan, Eldar Zianbetov, Weiqiang Yu, François Anceau, Olivier Billoint, Dimitri Galayko
2013	—	`conf`	On-chip clock error characterization for clock distribution system. ISVLSI Chuan Shan, Dimitri Galayko, François Anceau
2012	—	`conf`	Design and Modeling of ADPLL with sliding-window for wide range frequency tracking. NEWCAS Chuan Shan, Dimitri Galayko, François Anceau
2011	C	`conf`	A Digitally Controlled Oscillator in a 65-nm CMOS process for SoC clock generation. ISCAS Eldar Zianbetov, François Anceau, Mohammad Javidan, Dimitri Galayko, Éric Colinet, Jérôme Juillard
2011	C	`conf`	A novel technique to reduce the metastability of Bang-Bang Phase Frequency Detectors. ISCAS Mohammad Javidan, Eldar Zianbetov, François Anceau, Dimitri Galayko, Éric Colinet, Jérôme Juillard
2011	C	`conf`	All-digital PLL array provides reliable distributed clock for SOCs. ISCAS Mohammad Javidan, Eldar Zianbetov, François Anceau, Dimitri Galayko, Anton Korniienko, Éric Colinet, Gérard Scorletti, Jean-Michel Akre, Jérôme Juillard
2011	—	`conf`	FPGA implementation of reconfigurable ADPLL network for distributed clock generation. FPT Chuan Shan, Eldar Zianbetov, Mohammad Javidan, François Anceau, Mehdi Terosiet, Sylvain Feruglio, Dimitri Galayko, Olivier Romain, Éric Colinet, Jérôme Juillard
1989	—	`conf`	Formal Verification: A Significant Step Towards Zero Deffect VLSI Design. IFIP Congress François Anceau
1974	—	`—`	Contribution à l'étude de systèmes hiérarchisés de ressources dans l'architecture des machines informatiques. François Anceau