François-Raymond Boyer

20 papers A 1B 1C 1Misc 1Journal 8Unranked 8
YearRankTypeTitle / Venue / Authors
2025 J jnl
5G Fronthaul in Modular P4: eCPRI Protocol Processing and Precise BMv2 Timestamps for PTP-1588.
IEEE Access
Atabak Nojavan, Bill Pontikakis, François-Raymond Boyer, Yvon Savaria
2025 J jnl
P4Muse: Enabling Modular P4 Programming via Compiler-Managed Code Merging Without Syntax Modifications.
IEEE Access
Mohsen Rahmati, François-Raymond Boyer, Bill Pontikakis, Jean-Pierre David, Yvon Savaria
2019 J jnl
A High-Speed, Scalable, and Programmable Traffic Manager Architecture for Flow-Based Networking.
IEEE Access
Imad Benacer, François-Raymond Boyer, Yvon Savaria
2019 J jnl
HPQS: A Fast, High-Capacity, Hybrid Priority Queuing System for High-Speed Networking Devices.
IEEE Access
Imad Benacer, François-Raymond Boyer, Yvon Savaria
2019 Misc conf
Module-per-Object: A Human-Driven Methodology for C++-Based High-Level Synthesis Design.
FCCM
Jeferson Santiago da Silva, François-Raymond Boyer, J. M. Pierre Langlois
2019 J jnl
Module-per-Object: a Human-Driven Methodology for C++-based High-Level Synthesis Design.
CoRR
Jeferson Santiago da Silva, François-Raymond Boyer, J. M. Pierre Langlois
2018 J jnl
A Fast, Single-Instruction-Multiple-Data, Scalable Priority Queue.
IEEE Trans. Very Large Scale Integr. Syst.
Imad Benacer, François-Raymond Boyer, Yvon Savaria
2018 C conf
Design of a Low Latency 40 Gb/s Flow-Based Traffic Manager Using High-Level Synthesis.
ISCAS
Imad Benacer, François-Raymond Boyer, Yvon Savaria
2018 B conf
Extern Objects in P4: an ROHC Header Compression Scheme Case Study.
NetSoft
Jeferson Santiago da Silva, François-Raymond Boyer, Laurent-Olivier Chiquette, J. M. Pierre Langlois
2018 — conf
HPQ: A High Capacity Hybrid Priority Queue Architecture for High-Speed Network Switches.
NEWCAS
Imad Benacer, François-Raymond Boyer, Yvon Savaria
2018 A conf
P4-Compatible High-Level Synthesis of Low Latency 100 Gb/s Streaming Packet Parsers in FPGAs.
FPGA
Jeferson Santiago da Silva, François-Raymond Boyer, J. M. Pierre Langlois
2017 — conf
A high-speed traffic manager architecture for flow-based networking.
NEWCAS
Imad Benacer, François-Raymond Boyer, Yvon Savaria
2017 J jnl
P4-compatible High-level Synthesis of Low Latency 100 Gb/s Streaming Packet Parsers in FPGAs.
CoRR
Jeferson Santiago da Silva, François-Raymond Boyer, J. M. Pierre Langlois
2016 — conf
A fast systolic priority queue architecture for a flow-based Traffic Manager.
NEWCAS
Imad Benacer, François-Raymond Boyer, Normand Bélanger, Yvon Savaria
2016 J jnl
Extern Objects in P4: an ROHC Compression Case Study.
CoRR
Jeferson Santiago da Silva, François-Raymond Boyer, Laurent-Olivier Chiquette, J. M. Pierre Langlois
2016 — conf
Node configuration for the Aho-Corasick algorithm in Intrusion Detection Systems.
ANCS
Alexsandre B. Lacroix, J. M. Pierre Langlois, François-Raymond Boyer, Antoine Gosselin, Guy Bois
2013 — conf
Design of low power 4-bit flash ADC based on standard cells.
NEWCAS
Marcel Siadjine Njinowa, Hung Tien Bui, François-Raymond Boyer
2009 — conf
Robust estimation of LP parameters in white noise with unknown variance.
ICECS
Abdelaziz Trabelsi, Mounir Boukadoum, François-Raymond Boyer
2007 — conf
Iterative Noise-Compensated Method to Improve LPC Based Speech Analysis.
ICECS
Abdelaziz Trabelsi, François-Raymond Boyer, Yvon Savaria, Mounir Boukadoum
2000 — conf
An efficient verification method for a class of multi-phase sequential circuits.
ICECS
François-Raymond Boyer, El Mostapha Aboulhamid, Yvon Savaria