Frank M. L. van der Goes

16 papers Journal 8Unranked 8

Year	Rank	Type	Title / Venue / Authors
2018	J	`jnl`	A 13-mW 64-dB SNDR 280-MS/s Pipelined ADC Using Linearized Integrating Amplifiers. IEEE J. Solid State Circuits Rohan Sehgal, Frank M. L. van der Goes, Klaas Bult
2018	J	`jnl`	A 66-dB SNDR Pipelined Split-ADC in 40-nm CMOS Using a Class-AB Residue Amplifier. IEEE J. Solid State Circuits Md Shakil Akter, Rohan Sehgal, Frank M. L. van der Goes, Kofi A. A. Makinwa, Klaas Bult
2017	—	`conf`	A 13mW 64dB SNDR 280MS/s pipelined ADC using linearized open-loop class-AB amplifiers. ESSCIRC Rohan Sehgal, Frank M. L. van der Goes, Klaas Bult
2015	J	`jnl`	A 12 b 53 mW 195 MS/s Pipeline ADC with 82 dB SFDR Using Split-ADC Calibration. IEEE J. Solid State Circuits Rohan Sehgal, Frank M. L. van der Goes, Klaas Bult
2015	—	`conf`	A 66 dB SNDR pipelined split-ADC using class-AB residue amplifier with analog gain correction. ESSCIRC Md Shakil Akter, Rohan Sehgal, Frank M. L. van der Goes, Klaas Bult
2014	—	`conf`	11.4 A 1.5mW 68dB SNDR 80MS/s 2× interleaved SAR-assisted pipelined ADC in 28nm CMOS. ISSCC Frank M. L. van der Goes, Christopher M. Ward, Santosh Astgimath, Han Yan, Jeff Riley, Jan Mulder, Sijia Wang, Klaas Bult
2014	—	`conf`	8.5 A sub-1.75W full-duplex 10GBASE-T transceiver in 40nm CMOS. ISSCC Jan R. Westra, Jan Mulder, Yi Ke, Davide Vecchi, Xiaodong Liu, Erol Arslan, Jiansong Wan, Qiongna Zhang, Sijia Wang, Frank M. L. van der Goes, Klaas Bult
2014	J	`jnl`	A 1.5 mW 68 dB SNDR 80 Ms/s 2 × Interleaved Pipelined SAR ADC in 28 nm CMOS. IEEE J. Solid State Circuits Frank M. L. van der Goes, Christopher M. Ward, Santosh Astgimath, Han Yan, Jeff Riley, Zeng Zeng, Jan Mulder, Sijia Wang, Klaas Bult
2014	—	`conf`	A 12b 53 mW 195 MS/s pipeline ADC with 82dB SFDR using split-ADC calibration. ESSCIRC Rohan Sehgal, Frank M. L. van der Goes, Klaas Bult
2014	—	`conf`	Design considerations for low-power analog front ends in full-duplex 10GBASE-T transceivers. CICC Jan R. Westra, Jan Mulder, Yi Ke, Davide Vecchi, Xiaodong Liu, Erol Arslan, Jiansong Wan, Qiongna Zhang, Sijia Wang, Frank M. L. van der Goes, Klaas Bult
2013	J	`jnl`	A 375 mW Multimode DAC-Based Transmitter With 2.2 GHz Signal Bandwidth and In-Band IM3 < -58 dBc in 40 nm CMOS. IEEE J. Solid State Circuits Silvian Spiridon, Johan van der Tang, Han Yan, Hua-Feng Chen, Davide Guermandi, Xiaodong Liu, Erol Arslan, Frank M. L. van der Goes, Klaas Bult
2011	J	`jnl`	An 800 MS/s Dual-Residue Pipeline ADC in 40 nm CMOS. IEEE J. Solid State Circuits Davide Vecchi, Jan Mulder, Frank M. L. van der Goes, Jan R. Westra, Emre Ayranci, Christopher M. Ward, Jiansong Wan, Klaas Bult
2011	—	`conf`	An 800MS/s dual-residue pipeline ADC in 40nm CMOS. ISSCC Jan Mulder, Frank M. L. van der Goes, Davide Vecchi, Jan R. Westra, Emre Ayranci, Christopher M. Ward, Jiansong Wan, Klaas Bult
2009	J	`jnl`	A 12 bit 2.9 GS/s DAC With IM3 ≪ -60 dBc Beyond 1 GHz in 65 nm CMOS. IEEE J. Solid State Circuits Chi-Hung Lin, Frank M. L. van der Goes, Jan R. Westra, Jan Mulder, Yu Lin, Erol Arslan, Emre Ayranci, Xiaodong Liu, Klaas Bult
2009	—	`conf`	A 12b 2.9GS/s DAC with IM3 ≪-60dBc beyond 1GHz in 65nm CMOS. ISSCC Chi-Hung Lin, Frank M. L. van der Goes, Jan R. Westra, Jan Mulder, Yu Lin, Erol Arslan, Emre Ayranci, Xiaodong Liu, Klaas Bult
2004	J	`jnl`	A 21-mW 8-b 125-MSample/s ADC in 0.09-mm IEEE J. Solid State Circuits Jan Mulder, Christopher M. Ward, Chi-Hung Lin, David Kruse, Jan R. Westra, Marcel Lugthart, Erol Arslan, Rudy J. van de Plassche, Klaas Bult, Frank M. L. van der Goes