Frank K. Gürkaynak

95 papers A* 1A 10B 1C 13Misc 2Journal 41Unranked 27

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	A Reliable, Time-Predictable Heterogeneous SoC for AI-Enhanced Mixed-Criticality Edge Applications. CoRR Angelo Garofalo, Alessandro Ottaviano, Matteo Perotti, Thomas Benz, Yvan Tortorella, Robert Balas, Michael Rogenmoser, Chi Zhang, Luca Bertaccini, Nils Wistoff, Maicol Ciani, Cyril Koenig, Mattia Sinigaglia, Luca Valente, Paul Scheffler, Manuel Eggimann, Matheus A. Cavalcante, Francesco Restuccia, Alessandro Biondi, Francesco Conti, Frank K. Gürkaynak, Davide Rossi, Luca Benini
2025	J	`jnl`	A Reliable, Time-Predictable Heterogeneous SoC for AI-Enhanced Mixed-Criticality Edge Applications. IEEE Trans. Circuits Syst. II Express Briefs Angelo Garofalo, Alessandro Ottaviano, Matteo Perotti, Thomas Benz, Yvan Tortorella, Robert Balas, Michael Rogenmoser, Chi Zhang, Luca Bertaccini, Nils Wistoff, Maicol Ciani, Cyril Koenig, Mattia Sinigaglia, Luca Valente, Paul Scheffler, Manuel Eggimann, Matheus A. Cavalcante, Francesco Restuccia, Alessandro Biondi, Francesco Conti, Frank K. Gürkaynak, Davide Rossi, Luca Benini
2025	J	`jnl`	Basilisk: A 34 mm2 End-to-End Open-Source 64-bit Linux-Capable RISC-V SoC in 130nm BiCMOS. CoRR Philippe Sauter, Thomas Benz, Paul Scheffler, Martin Poviser, Frank K. Gürkaynak, Luca Benini
2025	—	`conf`	Basilisk: A 34mm² End-to-End Open-Source 64-bit Linux-Capable RISC-V SoC in 130nm BiCMOS : Integrated Systems Laboratory (ETH Zürich). HCS Philippe Sauter, Thomas Benz, Paul Scheffler, Martin Poviser, Frank K. Gürkaynak, Luca Benini
2025	J	`jnl`	Croc: An End-to-End Open-Source Extensible RISC-V MCU Platform to Democratize Silicon. CoRR Philippe Sauter, Thomas Benz, Paul Scheffler, Hannah Pochert, Luisa Wüthrich, Martin Poviser, Beat Muheim, Frank K. Gürkaynak, Luca Benini
2025	J	`jnl`	FlooNoC: A 645-Gb/s/link 0.15-pJ/B/hop Open-Source NoC With Wide Physical Links and End-to-End AXI4 Parallel Multistream Support. IEEE Trans. Very Large Scale Integr. Syst. Tim Fischer, Michael Rogenmoser, Thomas Benz, Frank K. Gürkaynak, Luca Benini
2025	J	`jnl`	Occamy: A 432-Core Dual-Chiplet Dual-HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12-nm FinFET. IEEE J. Solid State Circuits Paul Scheffler, Thomas Benz, Viviane Potocnik, Tim Fischer, Luca Colagrande, Nils Wistoff, Yichao Zhang, Luca Bertaccini, Gianmarco Ottavi, Manuel Eggimann, Matheus A. Cavalcante, Gianna Paulin, Frank K. Gürkaynak, Davide Rossi, Luca Benini
2025	J	`jnl`	Occamy: A 432-Core Dual-Chiplet Dual-HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12nm FinFET. CoRR Paul Scheffler, Thomas Benz, Viviane Potocnik, Tim Fischer, Luca Colagrande, Nils Wistoff, Yichao Zhang, Luca Bertaccini, Gianmarco Ottavi, Manuel Eggimann, Matheus A. Cavalcante, Gianna Paulin, Frank K. Gürkaynak, Davide Rossi, Luca Benini
2025	J	`jnl`	Work-In-Progress: Accelerating Numpy With OpenBLAS For Open-Source RISC-V Chips. CoRR Cyril Koenig, Enrico Zelioli, Frank K. Gürkaynak, Luca Benini
2024	J	`jnl`	Basilisk: Achieving Competitive Performance with Open EDA Tools on an Open-Source Linux-Capable RISC-V SoC. CoRR Philippe Sauter, Thomas Benz, Paul Scheffler, Zerun Jiang, Beat Muheim, Frank K. Gürkaynak, Luca Benini
2024	J	`jnl`	Basilisk: An End-to-End Open-Source Linux-Capable RISC-V SoC in 130nm CMOS. CoRR Paul Scheffler, Philippe Sauter, Thomas Benz, Frank K. Gürkaynak, Luca Benini
2024	J	`jnl`	Design and Experimental Investigation of Trikarenos: A Fault-Tolerant 28nm RISC-V-based SoC. CoRR Michael Rogenmoser, Philip Wiese, Bruno E. Forlin, Frank K. Gürkaynak, Paolo Rech, Alessandra Menicucci, Marco Ottavi, Luca Benini
2024	J	`jnl`	FlooNoC: A 645 Gbps/link 0.15 pJ/B/hop Open-Source NoC with Wide Physical Links and End-to-End AXI4 Parallel Multi-Stream Support. CoRR Tim Fischer, Michael Rogenmoser, Thomas Benz, Frank K. Gürkaynak, Luca Benini
2024	J	`jnl`	Insights from Basilisk: Are Open-Source EDA Tools Ready for a Multi-Million-Gate, Linux-Booting RV64 SoC Design? CoRR Philippe Sauter, Thomas Benz, Paul Scheffler, Frank K. Gürkaynak, Luca Benini
2024	—	`conf`	Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-Based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET. VLSI Technology and Circuits Gianna Paulin, Paul Scheffler, Thomas Benz, Matheus A. Cavalcante, Tim Fischer, Manuel Eggimann, Yichao Zhang, Nils Wistoff, Luca Bertaccini, Luca Colagrande, Gianmarco Ottavi, Frank K. Gürkaynak, Davide Rossi, Luca Benini
2024	J	`jnl`	Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET. CoRR Gianna Paulin, Paul Scheffler, Thomas Benz, Matheus A. Cavalcante, Tim Fischer, Manuel Eggimann, Yichao Zhang, Nils Wistoff, Luca Bertaccini, Luca Colagrande, Gianmarco Ottavi, Frank K. Gürkaynak, Davide Rossi, Luca Benini
2023	J	`jnl`	FlooNoC: A Multi-Tb/s Wide NoC for Heterogeneous AXI4 Traffic. IEEE Des. Test Tim Fischer, Michael Rogenmoser, Matheus A. Cavalcante, Frank K. Gürkaynak, Luca Benini
2023	J	`jnl`	FlooNoC: A Multi-Tbps Wide NoC for Heterogeneous AXI4 Traffic. CoRR Tim Fischer, Michael Rogenmoser, Matheus A. Cavalcante, Frank K. Gürkaynak, Luca Benini
2023	A	`conf`	PetaOps/W edge-AI $\mu$ Processors: Myth or reality? DATE Manil Dev Gomony, Floran de Putter, Anteneh Gebregiorgis, Gianna Paulin, Linyan Mei, Vikram Jain, Said Hamdioui, Victor Sanchez, Tobias Grosser, Marc Geilen, Marian Verhelst, Friedemann Zenke, Frank K. Gürkaynak, Barry de Bruin, Sander Stuijk, Simon Davidson, Sayandip De, Mounir Ghogho, Alexandra Jimborean, Sherif Eissa, Luca Benini, Dimitrios Soudris, Rajendra Bishnoi, Sam Ainsworth, Federico Corradi, Ouassim Karrakchou, Tim Güneysu, Henk Corporaal
2023	C	`conf`	Quark: An Integer RISC-V Vector Processor for Sub-Byte Quantized DNN Inference. ISCAS MohammadHossein AskariHemmat, Théo Dupuis, Yoan Fournier, Nizar El Zarif, Matheus A. Cavalcante, Matteo Perotti, Frank K. Gürkaynak, Luca Benini, François Leduc-Primeau, Yvon Savaria, Jean-Pierre David
2023	J	`jnl`	Quark: An Integer RISC-V Vector Processor for Sub-Byte Quantized DNN Inference. CoRR MohammadHossein AskariHemmat, Théo Dupuis, Yoan Fournier, Nizar El Zarif, Matheus A. Cavalcante, Matteo Perotti, Frank K. Gürkaynak, Luca Benini, François Leduc-Primeau, Yvon Savaria, Jean-Pierre David
2023	J	`jnl`	Systematic Prevention of On-Core Timing Channels by Full Temporal Partitioning. IEEE Trans. Computers Nils Wistoff, Moritz Schneider, Frank K. Gürkaynak, Gernot Heiser, Luca Benini
2022	J	`jnl`	CONVOLVE: Smart and seamless design of smart edge processors. CoRR Manil Dev Gomony, Floran de Putter, Anteneh Gebregiorgis, Gianna Paulin, Linyan Mei, Vikram Jain, Said Hamdioui, Victor Sanchez, Tobias Grosser, Marc Geilen, Marian Verhelst, Frank K. Zenke, Frank K. Gürkaynak, Barry de Bruin, Sander Stuijk, Simon Davidson, Sayandip De, Mounir Ghogho, Alexandra Jimborean, Sherif Eissa, Luca Benini, Dimitrios Soudris, Rajendra Bishnoi, S. Ainsworth, Federico Corradi, Ouassim Karrakchou, Tim Güneysu, Henk Corporaal
2022	—	`conf`	On-Demand Redundancy Grouping: Selectable Soft-Error Tolerance for a Multicore Cluster. ISVLSI Michael Rogenmoser, Nils Wistoff, Pirmin Vogel, Frank K. Gürkaynak, Luca Benini
2022	J	`jnl`	On-Demand Redundancy Grouping: Selectable Soft-Error Tolerance for a Multicore Cluster. CoRR Michael Rogenmoser, Nils Wistoff, Pirmin Vogel, Frank K. Gürkaynak, Luca Benini
2022	—	`conf`	Soft Tiles: Capturing Physical Implementation Flexibility for Tightly-Coupled Parallel Processing Clusters. ISVLSI Gianna Paulin, Matheus A. Cavalcante, Paul Scheffler, Luca Bertaccini, Yichao Zhang, Frank K. Gürkaynak, Luca Benini
2022	J	`jnl`	Soft Tiles: Capturing Physical Implementation Flexibility for Tightly-Coupled Parallel Processing Clusters. CoRR Gianna Paulin, Matheus A. Cavalcante, Paul Scheffler, Luca Bertaccini, Yichao Zhang, Frank K. Gürkaynak, Luca Benini
2022	J	`jnl`	Systematic Prevention of On-Core Timing Channels by Full Temporal Partitioning. CoRR Nils Wistoff, Moritz Schneider, Frank K. Gürkaynak, Gernot Heiser, Luca Benini
2021	—	`conf`	A 10-core SoC with 20 Fine-Grain Power Domains for Energy-Proportional Data-Parallel Processing over a Wide Voltage and Temperature Range. ESSCIRC Thomas Benz, Luca Bertaccini, Florian Zaruba, Fabian Schuiki, Frank K. Gürkaynak, Luca Benini
2021	J	`jnl`	Arnold: An eFPGA-Augmented RISC-V SoC for Flexible and Low-Power IoT End Nodes. IEEE Trans. Very Large Scale Integr. Syst. Pasquale Davide Schiavone, Davide Rossi, Alfio Di Mauro, Frank K. Gürkaynak, Timothy Saxe, Mao Wang, Ket Chong Yap, Luca Benini
2021	A	`conf`	Microarchitectural Timing Channels and their Prevention on an Open-Source 64-bit RISC-V Core. DATE Nils Wistoff, Moritz Schneider, Frank K. Gürkaynak, Luca Benini, Gernot Heiser
2021	B	`conf`	Security, Reliability and Test Aspects of the RISC-V Ecosystem. ETS Jaume Abella, Sergi Alcaide, Jens Anders, Francisco Bas, Steffen Becker, Elke De Mulder, Nourhan Elhamawy, Frank K. Gürkaynak, Helena Handschuh, Carles Hernández, Michael Hutter, Leonidas Kosmidis, Ilia Polian, Matthias Sauer, Stefan Wagner, Francesco Regazzoni
2020	J	`jnl`	Arnold: an eFPGA-Augmented RISC-V SoC for Flexible and Low-Power IoT End-Nodes. CoRR Pasquale Davide Schiavone, Davide Rossi, Alfio Di Mauro, Frank K. Gürkaynak, Timothy Saxe, Mao Wang, Ket Chong Yap, Luca Benini
2020	J	`jnl`	Prevention of Microarchitectural Covert Channels on an Open-Source 64-bit RISC-V Core. CoRR Nils Wistoff, Moritz Schneider, Frank K. Gürkaynak, Luca Benini, Gernot Heiser
2020	C	`conf`	The ECSEL FRACTAL Project: A Cognitive Fractal and Secure edge based on a unique Open-Safe-Reliable-Low Power Hardware Platform. DSD Aizea Lojo, Leire Rubio, Jesus Miguel Ruano, Tania Di Mascio, Luigi Pomante, Enrico Ferrari, Ignacio Garcìa Vega, Frank K. Gürkaynak, Mikel Labayen Esnaola, Vanessa Orani, Jaume Abella
2020	—	`conf`	XwattPilot: A Full-stack Cloud System Enabling Agile Development of Transprecision Software for Low-power SoCs. COOL CHIPS Dionysios Diamantopoulos, Florian Scheidegger, Stefan Mach, Fabian Schuiki, Germain Haugou, Michael Schaffner, Frank K. Gürkaynak, Christoph Hagleitner, A. Cristiano I. Malossi, Luca Benini
2019	J	`jnl`	A Scalable Near-Memory Architecture for Training Deep Neural Networks on Large In-Memory Datasets. IEEE Trans. Computers Fabian Schuiki, Michael Schaffner, Frank K. Gürkaynak, Luca Benini
2018	J	`jnl`	A Scalable Near-Memory Architecture for Training Deep Neural Networks on Large In-Memory Datasets. CoRR Fabian Schuiki, Michael Schaffner, Frank K. Gürkaynak, Luca Benini
2018	C	`conf`	An 826 MOPS, 210uW/MHz Unum ALU in 65 nm. ISCAS Florian Glaser, Stefan Mach, Abbas Rahimi, Frank K. Gürkaynak, Qiuting Huang, Luca Benini
2018	A	`conf`	High speed ASIC implementations of leakage-resilient cryptography. DATE Robert Schilling, Thomas Unterluggauer, Stefan Mangard, Frank K. Gürkaynak, Michael Muehlberghuber, Luca Benini
2017	J	`jnl`	An 826 MOPS, 210 uW/MHz Unum ALU in 65 nm. CoRR Florian Glaser, Stefan Mach, Abbas Rahimi, Frank K. Gürkaynak, Qiuting Huang, Luca Benini
2017	J	`jnl`	An Extended Shared Logarithmic Unit for Nonlinear Function Kernel Acceleration in a 65-nm CMOS Multicore Cluster. IEEE J. Solid State Circuits Michael Gautschi, Michael Schaffner, Frank K. Gürkaynak, Luca Benini
2017	C	`conf`	Leakage Bounds for Gaussian Side Channels. CARDIS Thomas Unterluggauer, Thomas Korak, Stefan Mangard, Robert Schilling, Luca Benini, Frank K. Gürkaynak, Michael Muehlberghuber
2017	J	`jnl`	Leakage Bounds for Gaussian Side Channels. IACR Cryptol. ePrint Arch. Thomas Unterluggauer, Thomas Korak, Stefan Mangard, Robert Schilling, Luca Benini, Frank K. Gürkaynak, Michael Muehlberghuber
2017	—	`conf`	Multi-core data analytics SoC with a flexible 1.76 Gbit/s AES-XTS cryptographic accelerator in 65 nm CMOS. CS2@HiPEAC Frank K. Gürkaynak, Robert Schilling, Michael Muehlberghuber, Francesco Conti, Stefan Mangard, Luca Benini
2017	J	`jnl`	Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices. IEEE Trans. Very Large Scale Integr. Syst. Michael Gautschi, Pasquale Davide Schiavone, Andreas Traber, Igor Loi, Antonio Pullini, Davide Rossi, Eric Flamand, Frank K. Gürkaynak, Luca Benini
2016	—	`conf`	4.6 A 65nm CMOS 6.4-to-29.2pJ/[email protected] shared logarithmic floating point unit for acceleration of nonlinear function kernels in a tightly coupled processor cluster. ISSCC Michael Gautschi, Michael Schaffner, Frank K. Gürkaynak, Luca Benini
2016	J	`jnl`	A near-threshold RISC-V core with DSP extensions for scalable IoT Endpoint Devices. CoRR Michael Gautschi, Pasquale Davide Schiavone, Andreas Traber, Igor Loi, Antonio Pullini, Davide Rossi, Eric Flamand, Frank K. Gürkaynak, Luca Benini
2016	C	`conf`	Accuracy and Performance Trade-Offs of Logarithmic Number Units in Multi-Core Clusters. ARITH Michael Schaffner, Michael Gautschi, Frank K. Gürkaynak, Luca Benini
2016	—	`conf`	Approximate 32-bit floating-point unit design with 53% power-area product reduction. ESSCIRC Vincent Camus, Jeremy Schlachter, Christian C. Enz, Michael Gautschi, Frank K. Gürkaynak
2016	A	`conf`	High-efficiency logarithmic number unit design based on an improved cotransformation scheme. DATE Youri Popoff, Florian Scheidegger, Michael Schaffner, Michael Gautschi, Frank K. Gürkaynak, Luca Benini
2016	J	`jnl`	Hybrid ASIC/FPGA System for Fully Automatic Stereo-to-Multiview Conversion Using IDW. IEEE Trans. Circuits Syst. Video Technol. Michael Schaffner, Frank K. Gürkaynak, Pierre Greisen, Hubert Kaeslin, Luca Benini, Aljosa Smolic
2015	C	`conf`	Automatic multiview synthesis - Prototype demo. VCIP Michael Schaffner, Frank K. Gürkaynak, Hubert Kaeslin, Luca Benini, Aljosa Smolic
2015	C	`conf`	Automatic multiview synthesis - Towards a mobile system on a chip. VCIP Michael Schaffner, Frank K. Gürkaynak, Hubert Kaeslin, Luca Benini, Aljosa Smolic
2015	A	`conf`	DRAM or no-DRAM?: exploring linear solver architectures for image domain warping in 28 nm CMOS. DATE Michael Schaffner, Frank K. Gürkaynak, Aljoscha Smolic, Luca Benini
2014	A*	`conf`	An Approximate Computing Technique for Reducing the Complexity of a Direct-Solver for Sparse Linear Systems in Real-Time Video Processing. DAC Michael Schaffner, Frank K. Gürkaynak, Aljoscha Smolic, Hubert Kaeslin, Luca Benini
2014	C	`conf`	Dynamic memory-based physically unclonable function for the generation of unique identifiers and true random numbers. ISCAS Christoph Keller, Frank K. Gürkaynak, Hubert Kaeslin, Norbert Felber
2013	—	`conf`	A Complete Real-Time Feature Extraction and Matching System Based on Semantic Kernels Binarized. VLSI-SoC (Selected Papers) Michael Schaffner, Pascal A. Hager, Lukas Cavigelli, Z. Fang, Pierre Greisen, Frank K. Gürkaynak, Aljoscha Smolic, Hubert Kaeslin, Luca Benini
2013	C	`conf`	A real-time 720p feature extraction core based on Semantic Kernels Binarized. VLSI-SoC Michael Schaffner, Pascal Hager, Lukas Cavigelli, Pierre Greisen, Frank K. Gürkaynak, Hubert Kaeslin
2013	—	`conf`	MADmax: A 1080p stereo-to-multiview rendering ASIC in 65 nm CMOS based on image domain warping. ESSCIRC Michael Schaffner, Pierre Greisen, Simon Heinzle, Frank K. Gürkaynak, Hubert Kaeslin, Aljoscha Smolic
2013	—	`conf`	Red team vs. blue team hardware trojan analysis: detection of a hardware trojan on an actual ASIC. HASP@ISCA Michael Muehlberghuber, Frank K. Gürkaynak, Thomas Korak, Philipp Dunst, Michael Hutter
2012	C	`conf`	A general-transformation EWA view rendering engine for 1080p video in 130 nm CMOS. VLSI-SoC Pierre Greisen, Richard Emler, Michael Schaffner, Simon Heinzle, Frank K. Gürkaynak
2012	—	`conf`	FPGA-Based High-Speed Authenticated Encryption System. VLSI-SoC (Selected Papers) Michael Muehlberghuber, Christoph Keller, Frank K. Gürkaynak, Norbert Felber
2012	—	`conf`	Instruction Set Extensions for Cryptographic Hash Functions on a Microcontroller Architecture. ASAP Jeremy Constantin, Andreas Burg, Frank K. Gürkaynak
2012	J	`jnl`	Investigating the Potential of Custom Instruction Set Extensions for SHA-3 Candidates on a 16-bit Microcontroller Architecture. IACR Cryptol. ePrint Arch. Jeremy Constantin, Andreas Burg, Frank K. Gürkaynak
2012	—	`conf`	Spatially-Varying Image Warping: Evaluations and VLSI Implementations. VLSI-SoC (Selected Papers) Pierre Greisen, Michael Schaffner, Danny Luu, Val Mikos, Simon Heinzle, Frank K. Gürkaynak, Aljoscha Smolic
2010	A	`conf`	Developing a Hardware Evaluation Method for SHA-3 Candidates. CHES Luca Henzen, Pietro Gendotti, Patrice Guillet, Enrico Pargaetzi, Martin Zoller, Frank K. Gürkaynak
2009	J	`jnl`	A current sensing completion detection method for asynchronous pipelines operating in the sub-threshold regime. Int. J. Circuit Theory Appl. Omer Can Akgun, Frank K. Gürkaynak, Yusuf Leblebici
2009	J	`jnl`	Breaking ECC2K-130. IACR Cryptol. ePrint Arch. Daniel V. Bailey, Lejla Batina, Daniel J. Bernstein, Peter Birkner, Joppe W. Bos, Hsieh-Chung Chen, Chen-Mou Cheng, Gauthier Van Damme, Giacomo de Meulenaer, Luis J. Dominguez Perez, Junfeng Fan, Tim Güneysu, Frank K. Gürkaynak, Thorsten Kleinjung, Tanja Lange, Nele Mentens, Ruben Niederhagen, Christof Paar, Francesco Regazzoni, Peter Schwabe, Leif Uhsadel, Anthony Van Herrewege, Bo-Yin Yang
2009	J	`jnl`	Evaluating Resistance of MCML Technology to Power Analysis Attacks Using a Simulation-Based Methodology. Trans. Comput. Sci. Francesco Regazzoni, Thomas Eisenbarth, Axel Poschmann, Johann Großschädl, Frank K. Gürkaynak, Marco Macchetti, Zeynep Toprak Deniz, Laura Pozzi, Christof Paar, Yusuf Leblebici, Paolo Ienne
2009	J	`jnl`	Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs. ACM Trans. Reconfigurable Technol. Syst. Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay Kumar Verma, Seyed-Hosein Attarzadeh-Niaki, Chrysostomos Nicopoulos, Frank K. Gürkaynak, Philip Brisk, Yusuf Leblebici, Paolo Ienne
2009	—	`conf`	GALS for Bursty Data Transfer based on Clock Coupling. FMGALS@DATE Milos Krstic, Xin Fan, Eckhard Grass, Frank K. Gürkaynak
2009	J	`jnl`	The Certicom Challenges ECC2-X. IACR Cryptol. ePrint Arch. Daniel V. Bailey, Brian Baldwin, Lejla Batina, Daniel J. Bernstein, Peter Birkner, Joppe W. Bos, Gauthier Van Damme, Giacomo de Meulenaer, Junfeng Fan, Tim Güneysu, Frank K. Gürkaynak, Thorsten Kleinjung, Tanja Lange, Nele Mentens, Christof Paar, Francesco Regazzoni, Peter Schwabe, Leif Uhsadel
2008	A	`conf`	A Generic Standard Cell Design Methodology for Differential Circuit Styles. DATE Stéphane Badel, Erdem Guleyupoglu, Ozgur Inac, Anna Pena Martinez, Paolo Vietti, Frank K. Gürkaynak, Yusuf Leblebici
2008	A	`conf`	Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs. FPGA Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay Kumar Verma, Philip Brisk, Frank K. Gürkaynak, Yusuf Leblebici, Paolo Ienne
2008	Misc	`conf`	Design space exploration for field programmable compressor trees. CASES Seyed-Hosein Attarzadeh-Niaki, Alessandro Cevrero, Philip Brisk, Chrysostomos Nicopoulos, Frank K. Gürkaynak, Yusuf Leblebici, Paolo Ienne
2008	C	`conf`	Improving the power-delay product in SCL circuits using source follower output stage. ISCAS Armin Tajalli, Frank K. Gürkaynak, Yusuf Leblebici, Massimo Alioto, Elizabeth J. Brauer
2008	A	`conf`	Novel Front-End Circuit Architectures for Integrated Bio-Electronic Interfaces. DATE Carlotta Guiducci, Alexandre Schmid, Frank K. Gürkaynak, Yusuf Leblebici
2007	—	`conf`	Design and realization of a fault-tolerant 90nm CMOS cryptographic engine capable of performing under massive defect density. ACM Great Lakes Symposium on VLSI Milos Stanisavljevic, Frank K. Gürkaynak, Alexandre Schmid, Yusuf Leblebici, Maria Gabrani
2007	J	`jnl`	Globally Asynchronous, Locally Synchronous Circuits: Overview and Outlook. IEEE Des. Test Comput. Milos Krstic, Eckhard Grass, Frank K. Gürkaynak, Pascal Vivet
2006	—	`conf`	GALS at ETH Zurich: Success or Failure. ASYNC Frank K. Gürkaynak, Stephan Oetiker, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner
2005	—	`conf`	Design Challenges for a Differential-Power-Analysis Aware GALS-based AES Crypto ASIC. FMGALS@MEMOCODE Frank K. Gürkaynak, Stephan Oetiker, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner
2005	—	`conf`	Improving DPA security by using globally-asynchronous locally-synchronous systems. ESSCIRC Frank K. Gürkaynak, Stephan Oetiker, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner
2004	—	`conf`	A 2 Gb/s balanced AES crypto-chip implementation. ACM Great Lakes Symposium on VLSI Frank K. Gürkaynak, Andreas Burg, Norbert Felber, Wolfgang Fichtner, D. Gasser, Franco Hug, Hubert Kaeslin
2004	—	`conf`	Power-Analysis Attack on an ASIC AES implementation. ITCC (2) Siddika Berna Örs, Frank K. Gürkaynak, Elisabeth Oswald, Bart Preneel
2004	—	`conf`	Towards an AES crypto-chip resistant to differential power analysis. ESSCIRC Norbert Pramstaller, Frank K. Gürkaynak, Simon Haene, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner
2003	—	`conf`	Self-Timed Ring for Globally-Asynchronous Locally-Synchronous Systems. ASYNC Thomas Villiger, Hubert Kaeslin, Frank K. Gürkaynak, Stephan Oetiker, Wolfgang Fichtner
2003	—	`conf`	Variable delay ripple carry adder with carry chain interrupt detection. ISCAS (5) Andreas Burg, Frank K. Gürkaynak, Hubert Kaeslin, Wolfgang Fichtner
2002	A	`conf`	2Gbit/s Hardware Realizations of RIJNDAEL and SERPENT: A Comparative Analysis. CHES Adrian K. Lutz, Jürg Treichler, Frank K. Gürkaynak, Hubert Kaeslin, Gérard Basler, Antonia Erni, Stephan Reichmuth, Pieter Rommens, Stephan Oetiker, Wolfgang Fichtner
2002	—	`conf`	A Functional Test Methodology for Globally-Asynchronous Locally-Synchronous Systems. ASYNC Thomas Villiger, Stephan Oetiker, Frank K. Gürkaynak, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner
2000	J	`jnl`	A Modular and Scalable Architecture for the Realization of High-speed Programmable Rank Order Filters Using Threshold Logic. VLSI Design Ilhan Hatirnaz, Frank K. Gürkaynak, Yusuf Leblebici
2000	Misc	`conf`	A compact modular architecture for high-speed binary sorting. ICASSP Ilhan Hatirnaz, Frank K. Gürkaynak, Yusuf Leblebici
2000	C	`conf`	A compact modular architecture for the realization of high-speed binary sorting engines based on rank ordering. ISCAS Ilhan Hatirnaz, Frank K. Gürkaynak, Yusuf Leblebici
2000	C	`conf`	Higher radix Kogge-Stone parallel prefix adder architectures. ISCAS Frank K. Gürkaynak, Yusuf Leblebici, Laurent Chaouat, Patrik J. McGuinness
1999	—	`conf`	Realization of a programmable rank-order filter architecture using capacitive threshold logic gates. ISCAS (1) Ilhan Hatirnaz, Frank K. Gürkaynak, Yusuf Leblebici