Frank Hannig - RankMe

224 papers A* 2A 9B 11C 21Misc 8Journal 63Unranked 96

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Loop Control Management in Tightly Coupled Processor Arrays (TCPAs). CoRR Dominik Walter, Frank Hannig, Jürgen Teich
2025	—	`conf`	A SIMD MAC RISC-V Extension with Approximate Multipliers for Accelerating CNN Inference in Tiny Embedded Devices. ARCS José Juan Hernández Morales, Frank Hannig, Jürgen Teich
2025	J	`jnl`	Beyond BNNs: Design and Acceleration of Sub-Bit Neural Networks Using RISC-V Custom Functional Units. IEEE Embed. Syst. Lett. Muhammad Sabih, Mohamed Abdo, Frank Hannig, Jürgen Teich
2025	A	`conf`	Design of Machine Learning Accelerators as RISC-V Extensions using an Open Source Tool Flow. ICCAD Batuhan Sesli, Muhammad Sabih, Frank Hannig, Jürgen Teich
2025	J	`jnl`	Evaluation of CGRA Toolchains. CoRR Dominik Walter, Marita Halm, Daniel Seidel, Indrayudh Ghosh, Christian Heidorn, Frank Hannig, Jürgen Teich
2025	J	`jnl`	Hardware/Software Co-Design of RISC-V Extensions for Accelerating Sparse DNNs on FPGAs. CoRR Muhammad Sabih, Abrarul Karim, Jakob Wittmann, Frank Hannig, Jürgen Teich
2025	J	`jnl`	Mapping and Execution of Nested Loops on Processor Arrays: CGRAs vs. TCPAs. CoRR Dominik Walter, Marita Halm, Daniel Seidel, Indrayudh Ghosh, Christian Heidorn, Frank Hannig, Jürgen Teich
2025	J	`jnl`	On-Device Training of Fully Quantized Deep Neural Networks on Cortex-M Microcontrollers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mark Deutel, Frank Hannig, Christopher Mutschler, Jürgen Teich
2025	Misc	`conf`	Special Session - Hardware-Software Co-Design for Machine Learning Systems Made Open-Source. CODES+ISSS Mehdi B. Tahoori, Vincent Meyers, Mahboobe Sadeghipour Roodsari, Huashuangyang Xu, Jürgen Becker, Tanja Harbaum, Felix Frombach, Julian Höfer, Georgios Sotiropoulos, Jörg Henkel, Zeynep Demirdag, Heba Khdr, Hassan Nassar, Ulf Schlichtmann, Johannes Geier, Philipp van Kempen, Georg Sigl, Stefan Koegler, Matthias Probst, Jürgen Teich, Frank Hannig, Muhammad Sabih, Batuhan Sesli, Norbert Wehn, Lukas Steiner, Wolfgang Kunz, Mohamed Shelkamy Ali
2025	—	`conf`	Unsupervised Learning of Variational Autoencoders on Cortex-M Microcontrollers. MCSoC Mark Deutel, Axel Plinge, Dominik Seuß, Christopher Mutschler, Frank Hannig, Jürgen Teich
2024	C	`conf`	ALPACA: An Accelerator Chip for Nested Loop Programs. ISCAS Dominik Walter, Marcel Brand, Christian Heidorn, Michael Witterauf, Frank Hannig, Jürgen Teich
2024	A	`conf`	Accelerating DNNs Using Weight Clustering on RISC-V Custom Functional Units. DATE Muhammad Sabih, Batuhan Sesli, Frank Hannig, Jürgen Teich
2024	—	`conf`	Analysis and Optimization of Block LU Decomposition for Execution on Tightly Coupled Processor Arrays. ASAP Dominik Walter, Thomas Adamtschuk, Frank Hannig, Jürgen Teich
2024	C	`conf`	DSL-Based SNN Accelerator Design Using Chisel. DSD Patrick Plagwitz, Frank Hannig, Jürgen Teich, Oliver Keszöcze
2024	C	`conf`	Efficient Deployment of Neural Networks for Thermal Monitoring on AURIX TC3xx Microcontrollers. VEHITS Christian Heidorn, Frank Hannig, Dominik Riedelbauch, Christoph Strohmeyer, Jürgen Teich
2024	J	`jnl`	Hardware-Aware Evolutionary Explainable Filter Pruning for Convolutional Neural Networks. Int. J. Parallel Program. Christian Heidorn, Muhammad Sabih, Nicolai Meyerhöfer, Christian Schinabeck, Jürgen Teich, Frank Hannig
2024	—	`conf`	Hardware/Software Co-Design of RISC-V Extensions for Accelerating Sparse DNNs on FPGAs. ICFPT Muhammad Sabih, Abrarul Karim, Jakob Wittmann, Frank Hannig, Jürgen Teich
2024	J	`jnl`	On-Device Training of Fully Quantized Deep Neural Networks on Cortex-M Microcontrollers. CoRR Mark Deutel, Frank Hannig, Christopher Mutschler, Jürgen Teich
2024	J	`jnl`	OpTC - A Toolchain for Deployment of Neural Networks on AURIX TC3xx Microcontrollers. CoRR Christian Heidorn, Frank Hannig, Dominik Riedelbauch, Christoph Strohmeyer, Jürgen Teich
2024	—	`conf`	SNN vs. CNN Implementations on FPGAs: An Empirical Evaluation. ARC Patrick Plagwitz, Frank Hannig, Jürgen Teich, Oliver Keszöcze
2023	—	`conf`	Robust and Tiny Binary Neural Networks using Gradient-based Explainability Methods. EuroMLSys@EuroSys Muhammad Sabih, Mikail Yayla, Frank Hannig, Jürgen Teich, Jian-Jia Chen
2023	J	`jnl`	To Spike or Not to Spike? A Quantitative Comparison of SNN and CNN FPGA Implementations. CoRR Patrick Plagwitz, Frank Hannig, Jürgen Teich, Oliver Keszöcze
2022	—	`conf`	DyFiP: explainable AI-based dynamic filter pruning of convolutional neural networks. EuroMLSys@EuroSys Muhammad Sabih, Frank Hannig, Jürgen Teich
2022	—	`conf`	Hardware-Aware Evolutionary Filter Pruning. SAMOS Christian Heidorn, Nicolai Meyerhöfer, Christian Schinabeck, Frank Hannig, Jürgen Teich
2022	—	`conf`	MOSP: Multi-Objective Sensitivity Pruning of Deep Neural Networks. IGSC Muhammad Sabih, Ashutosh Mishra, Frank Hannig, Jürgen Teich
2022	J	`jnl`	Precision- and Accuracy-Reconfigurable Processor Architectures - An Overview. IEEE Trans. Circuits Syst. II Express Briefs Marcel Brand, Frank Hannig, Oliver Keszöcze, Jürgen Teich
2022	J	`jnl`	Special Issue on Applied Reconfigurable Computing. J. Signal Process. Syst. Frank Hannig, Steven Derrien
2022	B	`conf`	TRAC: Compilation-Based Design of Transformer Accelerators for FPGAs. FPL Patrick Plagwitz, Frank Hannig, Jürgen Teich
2022	J	`jnl`	The HighPerMeshes framework for numerical algorithms on unstructured grids. Concurr. Comput. Pract. Exp. Samer Alhaddad, Jens Förstner, Stefan Groth, Daniel Grünewald, Yevgen Grynko, Frank Hannig, Tobias Kenter, Franz-Josef Pfreundt, Christian Plessl, Merlind Schotte, Thomas Steinke, Jürgen Teich, Martin Weiser, Florian Wende
2021	J	`jnl`	*-Predictable MPSoC execution of real-time control applications using invasive computing. Concurr. Comput. Pract. Exp. Marcel Brand, Michael Witterauf, Éricles Sousa, Alexandru Tanase, Frank Hannig, Jürgen Teich
2021	Misc	`conf`	A Safari through FPGA-based Neural Network Compilation and Design Automation Flows. FCCM Patrick Plagwitz, Frank Hannig, Martin Ströbel, Christoph Strohmeyer, Jürgen Teich
2021	—	`conf`	An Efficient Approach for Image Border Handling on GPUs via Iteration Space Partitioning. IPDPS Workshops Bo Qiao, Jürgen Teich, Frank Hannig
2021	—	`ed.`	Applied Reconfigurable Computing. Architectures, Tools, and Applications - 17th International Symposium, ARC 2021, Virtual Event, June 29-30, 2021, Proceedings ARC Steven Derrien, Frank Hannig, Pedro C. Diniz, Daniel Chillet
2021	C	`conf`	Efficient Application of Tensor Core Units for Convolving Images. SCOPES Stefan Groth, Jürgen Teich, Frank Hannig
2021	—	`conf`	Fault-Tolerant Low-Precision DNNs using Explainable AI. DSN Workshops Muhammad Sabih, Frank Hannig, Jürgen Teich
2021	B	`conf`	Hand Sign Recognition via Deep Learning on Tightly Coupled Processor Arrays. FPL Christian Heidorn, Dominik Walter, Yunus Emre Candir, Frank Hannig, Jürgen Teich
2021	J	`jnl`	HipaccVX: wedding of OpenVX and DSL-based code generation. J. Real Time Image Process. M. Akif Özkan, Burak Ok, Bo Qiao, Jürgen Teich, Frank Hannig
2021	J	`jnl`	Introduction to the Special Issue on Application-Specific Systems, Architectures and Processors. J. Signal Process. Syst. Frank Hannig, Dirk Koch
2021	J	`jnl`	Open Source Hardware. Computer Frank Hannig, Jürgen Teich
2021	J	`jnl`	Proceedings of the DATE Friday Workshop on System-level Design Methods for Deep Learning on Heterogeneous Architectures (SLOHA 2021). CoRR Frank Hannig, Paolo Meloni, Matteo Spallanzani, Matthias Ziegler
2021	J	`jnl`	Symbolic Loop Compilation for Tightly Coupled Processor Arrays. CoRR Michael Witterauf, Dominik Walter, Frank Hannig, Jürgen Teich
2021	J	`jnl`	Symbolic Loop Compilation for Tightly Coupled Processor Arrays. ACM Trans. Embed. Comput. Syst. Michael Witterauf, Dominik Walter, Frank Hannig, Jürgen Teich
2020	J	`jnl`	A bibliometric approach for detecting the gender gap in computer science. Commun. ACM Sandra Mattauch, Katja Lohmann, Frank Hannig, Daniel Lohmann, Jürgen Teich
2020	—	`conf`	A runtime system for finite element methods in a partitioned global address space. CF Stefan Groth, Daniel Grünewald, Jürgen Teich, Frank Hannig
2020	J	`jnl`	AnyHLS: High-Level Synthesis With Partial Evaluation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. M. Akif Özkan, Arsène Pérard-Gayot, Richard Membarth, Philipp Slusallek, Roland Leißa, Sebastian Hack, Jürgen Teich, Frank Hannig
2020	J	`jnl`	AnyHLS: High-Level Synthesis with Partial Evaluation. CoRR M. Akif Özkan, Arsène Pérard-Gayot, Richard Membarth, Philipp Slusallek, Roland Leißa, Sebastian Hack, Jürgen Teich, Frank Hannig
2020	C	`conf`	Design space exploration for layer-parallel execution of convolutional neural networks on CGRAs. SCOPES Christian Heidorn, Frank Hannig, Jürgen Teich
2020	C	`conf`	Efficient parallel reduction on GPUs with Hipacc. SCOPES Bo Qiao, Oliver Reiche, M. Akif Özkan, Jürgen Teich, Frank Hannig
2020	—	`ch.`	ExaStencils: Advanced Multigrid Solver Generation. Software for Exascale Computing Christian Lengauer, Sven Apel, Matthias Bolten, Shigeru Chiba, Ulrich Rüde, Jürgen Teich, Armin Größlinger, Frank Hannig, Harald Köstler, Lisa Claus, Alexander Grebhahn, Stefan Groth, Stefan Kronawitter, Sebastian Kuckuk, Hannah Rittich, Christian Schmitt, Jonas Schmitt
2020	—	`conf`	Hardware Implementation of Hyperbolic Tangent Activation Function for Floating Point Formats. VDAT Arvind Thumatti K. R., Marcel Brand, Christian Heidorn, Srinivas Boppu, Frank Hannig, Jürgen Teich
2020	—	`conf`	HighPerMeshes - A Domain-Specific Language for Numerical Algorithms on Unstructured Grids. Euro-Par Workshops Samer Alhaddad, Jens Förstner, Stefan Groth, Daniel Grünewald, Yevgen Grynko, Frank Hannig, Tobias Kenter, Franz-Josef Pfreundt, Christian Plessl, Merlind Schotte, Thomas Steinke, Jürgen Teich, Martin Weiser, Florian Wende
2020	J	`jnl`	HipaccVX: Wedding of OpenVX and DSL-based Code Generation. CoRR M. Akif Özkan, Burak Ok, Bo Qiao, Jürgen Teich, Frank Hannig
2020	—	`conf`	Message from the Conference Chairs - ASAP 2020. ASAP Dirk Koch, Frank Hannig, Javier Navaridas
2020	A*	`conf`	The Best of Both Worlds: Combining CUDA Graph with an Image Processing DSL. DAC Bo Qiao, M. Akif Özkan, Jürgen Teich, Frank Hannig
2020	—	`conf`	Unveiling kernel concurrency in multiresolution filters on GPUs with an image processing DSL. GPGPU@PPoPP Bo Qiao, Oliver Reiche, Jürgen Teich, Frank Hannig
2020	J	`jnl`	Utilizing Explainable AI for Quantization and Pruning of Deep Neural Networks. CoRR Muhammad Sabih, Frank Hannig, Jürgen Teich
2019	—	`conf`	Anytime instructions for programmable accuracy floating-point arithmetic. CF Marcel Brand, Michael Witterauf, Frank Hannig, Jürgen Teich
2019	—	`conf`	DSL-Based Acceleration of Automotive Environment Perception and Mapping Algorithms for Embedded CPUs, GPUs, and FPGAs. ARCS Jörg Fickenscher, Frank Hannig, Jürgen Teich
2019	J	`jnl`	Efficient Mapping of CNNs onto Tightly Coupled Processor Arrays. J. Comput. Christian Heidorn, Michael Witterauf, Frank Hannig, Jürgen Teich
2019	J	`jnl`	Efficient Mapping of Streaming Applications for Image Processing on Graphics Cards. Trans. High Perform. Embed. Archit. Compil. Richard Membarth, Hritam Dutta, Frank Hannig, Jürgen Teich
2019	A	`conf`	From Loop Fusion to Kernel Fusion: A Domain-Specific Approach to Locality Optimization. CGO Bo Qiao, Oliver Reiche, Frank Hannig, Jürgen Teich
2019	—	`book`	Modeling and Simulation of Invasive Applications and Architectures. Sascha Roloff, Frank Hannig, Jürgen Teich
2019	C	`conf`	Polyhedral fragments: an efficient representation for symbolically generating code for processor arrays. MEMOCODE Michael Witterauf, Frank Hannig, Jürgen Teich
2019	C	`conf`	SYCL Code Generation for Multigrid Methods. SCOPES Stefan Groth, Christian Schmitt, Jürgen Teich, Frank Hannig
2018	C	`conf`	Automatic Kernel Fusion for Image Processing DSLs. SCOPES Bo Qiao, Oliver Reiche, Frank Hannig, Jürgen Teich
2018	J	`jnl`	Automating the Development of High-Performance Multigrid Solvers. Proc. IEEE Christian Schmitt, Stefan Kronawitter, Frank Hannig, Jürgen Teich, Christian Lengauer
2018	C	`conf`	Base Algorithms of Environment Maps and Efficient Occupancy Grid Mapping on Embedded GPUs. VEHITS Jörg Fickenscher, Frank Hannig, Jürgen Teich, Mohamed Essayed Bouzouraa
2018	A	`conf`	Cell-based update algorithm for occupancy grid maps and hybrid map for ADAS on embedded GPUs. DATE Jörg Fickenscher, Jens Schlumberger, Frank Hannig, Jürgen Teich, Mohamed Essayed Bouzouraa
2018	—	`conf`	Invasive Computing for Predictability of Multiple Non-functional Properties: A Cyber-Physical System Case Study. ASAP Éricles Sousa, Michael Witterauf, Marcel Brand, Alexandru Tanase, Frank Hannig, Jürgen Teich
2018	J	`jnl`	Loop Parallelization Techniques for FPGA Accelerator Synthesis. J. Signal Process. Syst. Oliver Reiche, M. Akif Ozkan, Frank Hannig, Jürgen Teich, Moritz Schmid
2018	Misc	`conf`	OpenCL-Based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes. FCCM Tobias Kenter, Gopinath Mahale, Samer Alhaddad, Yevgen Grynko, Christian Schmitt, Ayesha Afzal, Frank Hannig, Jens Förstner, Christian Plessl
2018	J	`jnl`	Reconfigurable Hardware Generation of Multigrid Solvers with Conjugate Gradient Coarse-Grid Solution. Parallel Process. Lett. Christian Schmitt, Moritz Schmid, Sebastian Kuckuk, Harald Köstler, Jürgen Teich, Frank Hannig
2018	—	`conf`	Solving Maxwell's Equations with Modern C++ and SYCL: A Case Study. ASAP Ayesha Afzal, Christian Schmitt, Samer Alhaddad, Yevgen Grynko, Jürgen Teich, Jens Förstner, Frank Hannig
2018	J	`jnl`	Special issue on heterogeneous real-time image processing. J. Real Time Image Process. Dietmar Fey, Frank Hannig
2018	J	`jnl`	Symbolic Multi-Level Loop Mapping of Loop Programs for Massively Parallel Processor Arrays. ACM Trans. Embed. Comput. Syst. Alexandru Tanase, Michael Witterauf, Jürgen Teich, Frank Hannig
2018	—	`book`	Symbolic Parallelization of Nested Loop Programs Alexandru-Petru Tanase, Frank Hannig, Jürgen Teich
2017	J	`jnl`	A Novel Image Impulse Noise Removal Algorithm Optimized for Hardware Accelerators. J. Signal Process. Syst. Vivek Singh Bhadouria, Alexandru Tanase, Moritz Schmid, Frank Hannig, Jürgen Teich, Dibyendu Ghoshal
2017	J	`jnl`	A Scala prototype to generate multigrid solver implementations for different problems and target multi-core platforms. Int. J. Comput. Sci. Eng. Harald Köstler, Christian Schmitt, Sebastian Kuckuk, Stefan Kronawitter, Frank Hannig, Jürgen Teich, Ulrich Rüde, Christian Lengauer
2017	—	`conf`	A reconfigurable memory architecture for system integration of coarse-grained reconfigurable arrays. ReConFig Éricles Sousa, Alexandru Tanase, Frank Hannig, Jürgen Teich
2017	B	`conf`	Auto-vectorization for image processing DSLs. LCTES Oliver Reiche, Christof Kobylko, Frank Hannig, Jürgen Teich
2017	C	`conf`	Constructing fast and cycle-accurate simulators for configurable accelerators using C++ templates. RSP Michael Witterauf, Frank Hannig, Jürgen Teich
2017	B	`conf`	Convoy tracking for ADAS on embedded GPUs. Intelligent Vehicles Symposium Jörg Fickenscher, Sebastian Reinhart, Frank Hannig, Jürgen Teich, Mohamed Essayed Bouzouraa
2017	—	`conf`	Efficiency in ILP processing by using orthogonality. ASAP Marcel Brand, Frank Hannig, Alexandru Tanase, Jürgen Teich
2017	A	`conf`	Generating FPGA-based image processing accelerators with Hipacc: (Invited paper). ICCAD Oliver Reiche, M. Akif Ozkan, Richard Membarth, Jürgen Teich, Frank Hannig
2017	—	`conf`	Hardware design and analysis of efficient loop coarsening and border handling for image processing. ASAP M. Akif Ozkan, Oliver Reiche, Frank Hannig, Jürgen Teich
2017	—	`conf`	High performance network-on-chip simulation by interval-based timing predictions. ESTIMedia Sascha Roloff, Frank Hannig, Jürgen Teich
2017	J	`jnl`	Introduction to the special issue on architecture of computing systems. J. Syst. Archit. Frank Hannig, João M. P. Cardoso, Dietmar Fey
2017	—	`conf`	Orthogonal Instruction Processing: An Alternative to Lightweight VLIW Processors. MCSoC Marcel Brand, Frank Hannig, Alexandru Tanase, Jürgen Teich
2017	J	`jnl`	Power Density-Aware Resource Management for Heterogeneous Tiled Multicores. IEEE Trans. Computers Heba Khdr, Santiago Pagani, Éricles Sousa, Vahid Lari, Anuj Pathania, Frank Hannig, Muhammad Shafique, Jürgen Teich, Jörg Henkel
2017	—	`conf`	TCPA editor: A design automation environment for a class of coarse-grained reconfigurable arrays. ReConFig Éricles Sousa, Arindam Chakraborty, Alexandru Tanase, Frank Hannig, Jürgen Teich
2017	J	`jnl`	Trends in Data Locality Abstractions for HPC Systems. IEEE Trans. Parallel Distributed Syst. Didem Unat, Anshu Dubey, Torsten Hoefler, John Shalf, Mark James Abraham, Mauro Bianco, Bradford L. Chamberlain, Romain Cledat, H. Carter Edwards, Hal Finkel, Karl Fuerlinger, Frank Hannig, Emmanuel Jeannot, Amir Kamil, Jeff Keasler, Paul H. J. Kelly, Vitus J. Leung, Hatem Ltaief, Naoya Maruyama, Chris J. Newburn, Miquel Pericàs
2016	—	`ch.`	A Quick Tour of High-Level Synthesis Solutions for FPGAs. FPGAs for Software Programmers Frank Hannig
2016	—	`conf`	ActorX10: an actor library for X10. X10@PLDI Sascha Roloff, Alexander Pöppl, Tobias Schwarzer, Stefan Wildermann, Michael Bader, Michael Glaß, Frank Hannig, Jürgen Teich
2016	—	`ed.`	Architecture of Computing Systems - ARCS 2016 - 29th International Conference, Nuremberg, Germany, April 4-7, 2016, Proceedings ARCS Frank Hannig, João M. P. Cardoso, Thilo Pionteck, Dietmar Fey, Wolfgang Schröder-Preikschat, Jürgen Teich
2016	—	`ch.`	Big Data and HPC Acceleration with Vivado HLS. FPGAs for Software Programmers Moritz Schmid, Christian Schmitt, Frank Hannig, Gorker Alp Malazgirt, Nehir Sönmez, Arda Yurdakul, Adrián Cristal
2016	J	`jnl`	Dark silicon management: an integrated and coordinated cross-layer approach. it Inf. Technol. Santiago Pagani, Lars Bauer, Qingqing Chen, Elisabeth Glocker, Frank Hannig, Andreas Herkersdorf, Heba Khdr, Anuj Pathania, Ulf Schlichtmann, Doris Schmitt-Landsiedel, Mark Sagi, Éricles Sousa, Philipp Wagner, Volker Wenzel, Thomas Wild, Jörg Henkel
2016	—	`ch.`	FPGA Versus Software Programming: Why, When, and How? FPGAs for Software Programmers Dirk Koch, Daniel Ziener, Frank Hannig
2016	B	`conf`	FPGA-based accelerator design from a domain-specific language. FPL M. Akif Ozkan, Oliver Reiche, Frank Hannig, Jürgen Teich
2016	—	`book`	FPGAs for Software Programmers Dirk Koch, Frank Hannig, Daniel Ziener
2016	—	`ch.`	HIPA FPGAs for Software Programmers Moritz Schmid, Oliver Reiche, Frank Hannig, Jürgen Teich
2016	J	`jnl`	HIPA IEEE Trans. Parallel Distributed Syst. Richard Membarth, Oliver Reiche, Frank Hannig, Jürgen Teich, Mario Körner, Wieland Eckert
2016	—	`conf`	Hybrid code description for developing fast and resource efficient image processing architectures. SAMOS Konrad Häublein, Marc Reichenbach, Oliver Reiche, M. Akif Ozkan, Dietmar Fey, Frank Hannig, Jürgen Teich
2016	—	`conf`	Modeling, programming and performance analysis of automotive environment map representations on embedded GPUs. HLDVT Jörg Fickenscher, Oliver Reiche, Jens Schlumberger, Frank Hannig, Jürgen Teich
2016	—	`conf`	Modulo scheduling of symbolically tiled loops for tightly coupled processor arrays. ASAP Michael Witterauf, Alexandru Tanase, Frank Hannig, Jürgen Teich
2016	—	`ch.`	Systems of Partial Differential Equations in ExaSlang. Software for Exascale Computing Christian Schmitt, Sebastian Kuckuk, Frank Hannig, Jürgen Teich, Harald Köstler, Ulrich Rüde, Christian Lengauer
2015	—	`conf`	A co-design approach for fault-tolerant loop execution on Coarse-Grained Reconfigurable Arrays. AHS Vahid Lari, Alexandru Tanase, Jürgen Teich, Michael Witterauf, Faramarz Khosravi, Frank Hannig, Brett H. Meyer
2015	J	`jnl`	Automatic Optimization of Hardware Accelerators for Image Processing. CoRR Oliver Reiche, Konrad Häublein, Marc Reichenbach, Frank Hannig, Jürgen Teich, Dietmar Fey
2015	A*	`conf`	Execution-driven parallel simulation of PGAS applications on heterogeneous tiled architectures. DAC Sascha Roloff, David Schafhauser, Frank Hannig, Jürgen Teich
2015	J	`jnl`	Introduction to the Special Issue on Testing, prototyping, and debugging of multi-core architectures. J. Syst. Archit. Frank Hannig, Andreas Herkersdorf
2015	—	`conf`	Invasive computing for predictable stream processing: a simulation-based case study. ESTIMedia Sascha Roloff, Stefan Wildermann, Frank Hannig, Jürgen Teich
2015	—	`conf`	Loop coarsening in C-based High-Level Synthesis. ASAP Moritz Schmid, Oliver Reiche, Frank Hannig, Jürgen Teich
2015	—	`conf`	On-demand fault-tolerant loop processing on massively parallel processor arrays. ASAP Alexandru Tanase, Michael Witterauf, Jürgen Teich, Frank Hannig, Vahid Lari
2015	J	`jnl`	Proceedings of the DATE Friday Workshop on Heterogeneous Architectures and Design Methods for Embedded Image Systems (HIS 2015). CoRR Frank Hannig, Dietmar Fey, Anton Lokhmotov
2015	J	`jnl`	Proceedings of the Second International Workshop on FPGAs for Software Programmers (FSP 2015). CoRR Frank Hannig, Dirk Koch, Daniel Ziener
2015	—	`conf`	Reconfigurable Buffer Structures for Coarse-Grained Reconfigurable Arrays. IESS Éricles Sousa, Frank Hannig, Jürgen Teich
2015	J	`jnl`	Resource-awareness on heterogeneous MPSoCs for image processing. J. Syst. Archit. Johny Paul, Walter Stechele, Benjamin Oechslein, Christoph Erhardt, Jens Schedel, Daniel Lohmann, Wolfgang Schröder-Preikschat, Manfred Kröhnert, Tamim Asfour, Éricles Sousa, Vahid Lari, Frank Hannig, Jürgen Teich, Artjom Grudnitsky, Lars Bauer, Jörg Henkel
2015	C	`conf`	Runtime Adaptation of Application Execution under Thermal and Power Constraints in Massively Parallel Processor Arrays. SCOPES Éricles Sousa, Frank Hannig, Jürgen Teich, Qingqing Chen, Ulf Schlichtmann
2015	C	`conf`	Symbolic loop parallelization for balancing I/O and memory accesses on processor arrays. MEMOCODE Alexandru Tanase, Michael Witterauf, Jürgen Teich, Frank Hannig
2015	J	`jnl`	Synthesis and optimization of image processing accelerators using domain knowledge. J. Syst. Archit. Oliver Reiche, Konrad Häublein, Marc Reichenbach, Moritz Schmid, Frank Hannig, Jürgen Teich, Dietmar Fey
2014	J	`jnl`	A Scala Prototype to Generate Multigrid Solver Implementations for Different Problems and Target Multi-Core Platforms. CoRR Harald Köstler, Christian Schmitt, Sebastian Kuckuk, Frank Hannig, Jürgen Teich, Ulrich Rüde
2014	—	`conf`	An Evaluation of Domain-Specific Language Technologies for Code Generation. ICCSA (Workshops/Short Papers/Posters) Christian Schmitt, Sebastian Kuckuk, Harald Köstler, Frank Hannig, Jürgen Teich
2014	B	`conf`	An image processing library for C-based high-level synthesis. FPL Moritz Schmid, Nicolas Apelt, Frank Hannig, Jürgen Teich
2014	Misc	`conf`	Application-driven reconfiguration of shared resources for timing predictability of MPSoC platforms. ACSSC Deepak Gangadharan, Éricles Sousa, Vahid Lari, Frank Hannig, Jürgen Teich
2014	J	`jnl`	Code Generation for High-Level Synthesis of Multiresolution Applications on FPGAs. CoRR Moritz Schmid, Oliver Reiche, Christian Schmitt, Frank Hannig, Jürgen Teich
2014	A	`conf`	Code generation for embedded heterogeneous architectures on android. DATE Richard Membarth, Oliver Reiche, Frank Hannig, Jürgen Teich
2014	Misc	`conf`	Code generation from a domain-specific language for C-based HLS of hardware accelerators. CODES+ISSS Oliver Reiche, Moritz Schmid, Frank Hannig, Richard Membarth, Jürgen Teich
2014	J	`jnl`	Compact Code Generation for Tightly-Coupled Processor Arrays. J. Signal Process. Syst. Srinivas Boppu, Frank Hannig, Jürgen Teich
2014	—	`conf`	Domain-specific augmentations for High-Level Synthesis. ASAP Moritz Schmid, Alexandru Tanase, Frank Hannig, Jürgen Teich, Vivek Singh Bhadouria, Dibyendu Ghoshal
2014	—	`conf`	ExaSlang: a domain-specific language for highly scalable multigrid solvers. WOLFHPC@SC Christian Schmitt, Sebastian Kuckuk, Frank Hannig, Harald Köstler, Jürgen Teich
2014	—	`conf`	ExaStencils: Advanced Stencil-Code Engineering. Euro-Par Workshops (2) Christian Lengauer, Sven Apel, Matthias Bolten, Armin Größlinger, Frank Hannig, Harald Köstler, Ulrich Rüde, Jürgen Teich, Alexander Grebhahn, Stefan Kronawitter, Sebastian Kuckuk, Hannah Rittich, Christian Schmitt
2014	J	`jnl`	Experiments on Optimizing the Performance of Stencil Codes with SPL Conqueror. Parallel Process. Lett. Alexander Grebhahn, Sebastian Kuckuk, Christian Schmitt, Harald Köstler, Norbert Siegmund, Sven Apel, Frank Hannig, Jürgen Teich
2014	J	`jnl`	Invasive Tightly-Coupled Processor Arrays: A Domain-Specific Architecture/Compiler Co-Design Approach. ACM Trans. Embed. Comput. Syst. Frank Hannig, Vahid Lari, Srinivas Boppu, Alexandru Tanase, Oliver Reiche
2014	J	`jnl`	Massively Parallel Processor Architectures for Resource-aware Computing. CoRR Vahid Lari, Alexandru Tanase, Frank Hannig, Jürgen Teich
2014	J	`jnl`	Proceedings of the First International Workshop on FPGAs for Software Programmers (FSP 2014). CoRR Frank Hannig, Dirk Koch, Daniel Ziener
2014	J	`jnl`	Proceedings of the First Workshop on Resource Awareness and Adaptivity in Multi-Core Computing (Racing 2014). CoRR Frank Hannig, Jürgen Teich
2014	C	`conf`	Runtime Reconfigurable Bus Arbitration for Concurrent Applications on Heterogeneous MPSoC Architectures. DSD Éricles Sousa, Deepak Gangadharan, Frank Hannig, Jürgen Teich
2014	—	`conf`	Self-adaptive harris corner detector on heterogeneous many-core processor. DASIP Johny Paul, Walter Stechele, Éricles Sousa, Vahid Lari, Frank Hannig, Jürgen Teich, Manfred Kröhnert, Tamim Asfour
2014	J	`jnl`	Symbolic Mapping of Loop Programs onto Processor Arrays. J. Signal Process. Syst. Jürgen Teich, Alexandru Tanase, Frank Hannig
2014	C	`conf`	Symbolic inner loop parallelisation for massively parallel processor arrays. MEMOCODE Alexandru Tanase, Michael Witterauf, Jürgen Teich, Frank Hannig
2014	—	`conf`	Towards Actor-oriented Programming on PGAS-based Multicore Architectures. ARCS Workshops Sascha Roloff, Frank Hannig, Jürgen Teich
2014	J	`jnl`	Towards a performance-portable description of geometric multigrid algorithms using a domain-specific language. J. Parallel Distributed Comput. Richard Membarth, Oliver Reiche, Christian Schmitt, Frank Hannig, Jürgen Teich, Markus Stürmer, Harald Köstler
2013	—	`conf`	A prototype of an adaptive computer vision algorithm on MPSoC architecture. DASIP Éricles Rodrigues Sousa, Alexandru Tanase, Frank Hannig, Jürgen Teich
2013	—	`conf`	Accuracy and performance analysis of Harris Corner computation on tightly-coupled processor arrays. DASIP Éricles Rodrigues Sousa, Alexandru Tanase, Frank Hannig, Jürgen Teich
2013	—	`conf`	Exploitation of Quality/Throughput Tradeoffs in Image Processing through Invasive Computing. PARCO Alexandru Tanase, Vahid Lari, Frank Hannig, Jürgen Teich
2013	—	`conf`	High-Level Synthesis Revised - Generation of FPGA Accelerators from a Domain-Specific Language using the Polyhedron Model. PARCO Moritz Schmid, Frank Hannig, Alexandru Tanase, Jürgen Teich
2013	—	`conf`	Loop program mapping and compact code generation for programmable hardware accelerators. ASAP Srinivas Boppu, Frank Hannig, Jürgen Teich
2013	—	`conf`	NoC simulation in heterogeneous architectures for PGAS programming model. M-SCOPES Sascha Roloff, Andreas Weichslgartner, Jan Heißwolf, Frank Hannig, Jürgen Teich
2013	—	`conf`	Real-timerange image preprocessing on FPGAs. ReConFig Moritz Schmid, Markus Blocherer, Frank Hannig, Jürgen Teich
2013	—	`conf`	Symbolic parallelization of loop programs for massively parallel processor arrays. ASAP Jürgen Teich, Alexandru Tanase, Frank Hannig
2013	—	`conf`	System integration of tightly-coupled processor arrays using reconfigurable buffer structures. Conf. Computing Frontiers Frank Hannig, Moritz Schmid, Vahid Lari, Srinivas Boppu, Jürgen Teich
2012	—	`conf`	A prototype of an invasive tightly-coupled processor array. DASIP Shravan Muddasani, Srinivas Boppu, Frank Hannig, Boris Kuzmin, Vahid Lari, Jürgen Teich
2012	C	`conf`	An integrated simulation framework for invasive computing. FDL Michael Gerndt, Frank Hannig, Andreas Herkersdorf, Andreas Hollmann, Marcel Meyer, Sascha Roloff, Josef Weidendorfer, Thomas Wild, Aurang Zaib
2012	—	`conf`	Approximate time functional simulation of resource-aware programming concepts for heterogeneous MPSoCs. ASP-DAC Sascha Roloff, Frank Hannig, Jürgen Teich
2012	C	`conf`	Automatic Optimization of In-Flight Memory Transactions for GPU Accelerators Based on a Domain-Specific Language for Medical Imaging. ISPDC Richard Membarth, Frank Hannig, Jürgen Teich, Mario Körner, Wieland Eckert
2012	—	`conf`	Design of Low Power On-chip Processor Arrays. ASAP Vahid Lari, Shravan Muddasani, Srinivas Boppu, Frank Hannig, Jürgen Teich
2012	—	`conf`	Dynamic Task-Scheduling and Resource Management for GPU Accelerators in Medical Imaging. ARCS Richard Membarth, Jan-Hugo Lupp, Frank Hannig, Jürgen Teich, Mario Körner, Wieland Eckert
2012	—	`conf`	Fast architecture evaluation of heterogeneous MPSoCs by host-compiled simulation. Map2MPSoC/SCOPES Sascha Roloff, Frank Hannig, Jürgen Teich
2012	A	`conf`	Generating Device-specific GPU Code for Local Operators in Medical Imaging. IPDPS Richard Membarth, Frank Hannig, Jürgen Teich, Mario Körner, Wieland Eckert
2012	J	`jnl`	Hierarchical power management for adaptive tightly-coupled processor arrays. ACM Trans. Design Autom. Electr. Syst. Vahid Lari, Shravan Muddasani, Srinivas Boppu, Frank Hannig, Moritz Schmid, Jürgen Teich
2012	—	`conf`	Mastering Software Variant Explosion for GPU Accelerators. Euro-Par Workshops Richard Membarth, Frank Hannig, Jürgen Teich, Mario Körner, Wieland Eckert
2012	Misc	`conf`	Power Management Strategies for Serial RapidIO Endpoints in FPGAs. FCCM Moritz Schmid, Frank Hannig, Jürgen Teich
2012	—	`conf`	Towards Domain-Specific Computing for Stencil Codes in HPC. SC Companion Richard Membarth, Frank Hannig, Jürgen Teich, Harald Köstler
2011	—	`ed.`	22nd IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2011, Santa Monica, CA, USA, Sept. 11-14, 2011 ASAP Joseph R. Cavallaro, Milos D. Ercegovac, Frank Hannig, Paolo Ienne, Earl E. Swartzlander Jr., Alexandre F. Tenca
2011	—	`conf`	Decentralized dynamic resource management support for massively parallel processor arrays. ASAP Vahid Lari, Andriy Narovlyanskyy, Frank Hannig, Jürgen Teich
2011	B	`conf`	Detector defect correction of medical images on graphics processors. Image Processing Richard Membarth, Frank Hannig, Jürgen Teich, Gerhard Litz, Heinz Hornegger
2011	—	`conf`	Distributed Resource Reservation in Massively Parallel Processor Arrays. IPDPS Workshops Vahid Lari, Frank Hannig, Jürgen Teich
2011	J	`jnl`	Efficient Evaluation of Power/Area/Latency Design Trade-Offs for Coarse-Grained Reconfigurable Processor Arrays. J. Low Power Electron. Dmitrij Kissler, Frank Hannig, Jürgen Teich
2011	—	`conf`	Frameworks for GPU Accelerators: A comprehensive evaluation using 2D/3D image registration. SASP Richard Membarth, Frank Hannig, Jürgen Teich, Mario Körner, Wieland Eckert
2011	—	`conf`	Frameworks for Multi-core Architectures: A Comprehensive Evaluation Using 2D/3D Image Registration. ARCS Richard Membarth, Frank Hannig, Jürgen Teich, Mario Körner, Wieland Eckert
2011	C	`conf`	Resource-aware programming and simulation of MPSoC architectures through extension of X10. SCOPES Frank Hannig, Sascha Roloff, Gregor Snelting, Jürgen Teich, Andreas Zwinkau
2011	J	`jnl`	Scalable Many-Domain Power Gating in Coarse-Grained Reconfigurable Processor Arrays. IEEE Embed. Syst. Lett. Dmitrij Kissler, D. Gran, Zoran Salcic, Frank Hannig, Jürgen Teich
2011	—	`conf`	Towards Resource Aware Programming on Intel's Single-Chip Cloud Computer Processor. MARC Symposium Georgia Kouveli, Frank Hannig, Jan-Hugo Lupp, Jürgen Teich
2011	—	`conf`	Towards Symbolic Run-Time Reconfiguration in Tightly-Coupled Processor Arrays. ReConFig Srinivas Boppu, Frank Hannig, Jürgen Teich, Roberto Perez-Andrade
2010	—	`ed.`	21st IEEE International Conference on Application-specific Systems Architectures and Processors, ASAP 2010, Rennes, France, 7-9 July 2010 ASAP François Charot, Frank Hannig, Jürgen Teich, Christophe Wolinski
2010	—	`conf`	A deeply pipelined and parallel architecture for denoising medical images. FPT Frank Hannig, Moritz Schmid, Jürgen Teich, Heinz Hornegger
2010	Misc	`conf`	Compilation techniques for CGRAs: exploring all parallelization approaches. CODES+ISSS Tom Vander Aa, Praveen Raghavan, Scott A. Mahlke, Bjorn De Sutter, Aviral Shrivastava, Frank Hannig
2010	—	`conf`	Modeling and synthesis of communication subsystems for loop accelerator pipelines. ASAP Hritam Dutta, Frank Hannig, Moritz Schmid, Joachim Keinert
2009	J	`jnl`	A holistic approach for tightly coupled reconfigurable parallel processors. Microprocess. Microsystems Hritam Dutta, Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, Jürgen Teich, Bernard Pottier
2009	—	`conf`	Acceleration of Multiresolution Imaging Algorithms: A Comparative Study. ASAP Richard Membarth, Philipp Kutzer, Hritam Dutta, Frank Hannig, Jürgen Teich
2009	—	`conf`	Efficient Mapping of Multiresolution Image Filtering Algorithms on Graphics Processors. SAMOS Richard Membarth, Frank Hannig, Hritam Dutta, Jürgen Teich
2009	—	`conf`	FPGA implementation of an invasive computing architecture. FPT Abdulazim Amouri, Farhadur Arifin, Frank Hannig, Jürgen Teich
2009	—	`conf`	Impact of Loop Tiling on the Controller Logic of Acceleration Engines. ASAP Hritam Dutta, Jiali Zhai, Frank Hannig, Jürgen Teich
2009	A	`conf`	Model-based synthesis and optimization of static multi-rate image processing algorithms. DATE Joachim Keinert, Hritam Dutta, Frank Hannig, Christian Haubelt, Jürgen Teich
2009	—	`conf`	Parallelization Approaches for Hardware Accelerators - Loop Unrolling Versus Loop Partitioning. ARCS Frank Hannig, Hritam Dutta, Jürgen Teich
2009	—	`conf`	Performance Matching of Hardware Acceleration Engines for Heterogeneous MPSoC Using Modular Performance Analysis. ARCS Hritam Dutta, Frank Hannig, Jürgen Teich
2009	J	`jnl`	Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures. J. Low Power Electron. Dmitrij Kissler, Andreas Strawetz, Frank Hannig, Jürgen Teich
2009	—	`—`	Scheduling Techniques for High-Throughput Loop Accelerators. Frank Hannig
2009	—	`conf`	System Integration of Tightly-Coupled Reconfigurable Processor Arrays and Evaluation of Buffer Size Effects on Their Performance. ICPP Workshops Vahid Lari, Frank Hannig, Jürgen Teich
2008	B	`conf`	Area and reconfiguration time minimization of the communication network in regular 2D reconfigurable architectures. FPL Christophe Wolinski, Krzysztof Kuchcinski, Jürgen Teich, Frank Hannig
2008	B	`conf`	Coarse-grained reconfiguration. FPL Sven Eisenhardt, Thomas Schweizer, Julio A. de Oliveira Filho, Tobias Oppold, Wolfgang Rosenstiel, Alexander Thomas, Jürgen Becker, Frank Hannig, Dmitrij Kissler, Hritam Dutta, Jürgen Teich, Heiko Hinkelmann, Peter Zipf, Manfred Glesner
2008	C	`conf`	Communication Network Reconfiguration Overhead Optimization in Programmable Processor Array Architectures. DSD Christophe Wolinski, Krzysztof Kuchcinski, Jürgen Teich, Frank Hannig
2008	Misc	`conf`	Optimization of Routing and Reconfiguration Overhead in Programmable Processor Array Architectures. FCCM Christophe Wolinski, Krzysztof Kuchcinski, Jürgen Teich, Frank Hannig
2008	—	`conf`	PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive Applications. ARC Frank Hannig, Holger Ruckdeschel, Hritam Dutta, Jürgen Teich
2008	—	`conf`	Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures. PATMOS Dmitrij Kissler, Andreas Strawetz, Frank Hannig, Jürgen Teich
2008	—	`conf`	The PAULA Language for Designing Multi-Dimensional Dataflow-Intensive Applications. MBMV Frank Hannig, Holger Ruckdeschel, Jürgen Teich
2008	C	`conf`	Utilization of all Levels of Parallelism in a Processor Array with Subword Parallelism. DSD Rainer Schaffer, Renate Merker, Frank Hannig, Jürgen Teich
2007	—	`conf`	A Unified Retargetable Design Methodology for Dedicated and Re-Programmable Multiprocessor Arrays: Case Study and Quantitative Evaluation. ERSA Jürgen Teich, Frank Hannig, Holger Ruckdeschel, Hritam Dutta, Dmitrij Kissler, Andrej Stravet
2007	J	`jnl`	Efficient control generation for mapping nested loop programs onto processor arrays. J. Syst. Archit. Hritam Dutta, Frank Hannig, Holger Ruckdeschel, Jürgen Teich
2007	C	`conf`	Efficient event-driven simulation of parallel processor architectures. SCOPES Alexey Kupriyanov, Dmitrij Kissler, Frank Hannig, Jürgen Teich
2007	—	`conf`	Massively Parallel Processor Architectures: A Co-design Approach. ReCoSoC Hritam Dutta, Frank Hannig, Alexey Kupriyanov, Dmitrij Kissler, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Bernard Pottier
2007	—	`conf`	Modeling of Interconnection Networks in Massively Parallel Processor Architectures. ARCS Alexey Kupriyanov, Frank Hannig, Dmitrij Kissler, Jürgen Teich, Julien Lallet, Olivier Sentieys, Sébastien Pillement
2006	—	`conf`	A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing. ASAP Hritam Dutta, Frank Hannig, Jürgen Teich, Benno Heigl, Heinz Hornegger
2006	—	`conf`	A Dynamically Reconfigurable Weakly Programmable Processor Array Architecture Template. ReCoSoC Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, Jürgen Teich
2006	—	`conf`	A Generic Framework for Rapid Prototyping of System-on-Chip Designs. CDES Dmitrij Kissler, Alexey Kupriyanov, Frank Hannig, Dirk Koch, Jürgen Teich
2006	—	`conf`	A highly parameterizable parallel processor array architecture. FPT Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, Jürgen Teich
2006	—	`conf`	An Architecture Description Language for Massively Parallel Processor Architectures. MBMV Alexey Kupriyanov, Frank Hannig, Dmitrij Kissler, Jürgen Teich, Rainer Schaffer, Renate Merker
2006	—	`conf`	Controller Synthesis for Mapping Partitioned Programs on Array Architectures. ARCS Hritam Dutta, Frank Hannig, Jürgen Teich
2006	—	`conf`	Hardware Cost Analysis for Weakly Programmable Processor Arrays. SoC Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, Jürgen Teich
2006	—	`conf`	Hierarchical Partitioning for Piecewise Linear Algorithms. PARELEC Hritam Dutta, Frank Hannig, Jürgen Teich
2006	J	`jnl`	Mapping a class of dependence algorithms to coarse-grained reconfigurable arrays: architectural parameters and methodology. Int. J. Embed. Syst. Frank Hannig, Hritam Dutta, Jürgen Teich
2005	—	`conf`	Automatic FIR Filter Generation for FPGAs. SAMOS Holger Ruckdeschel, Hritam Dutta, Frank Hannig, Jürgen Teich
2005	—	`conf`	Co-Design of Massively Parallel Embedded Processor Architectures. ReCoSoC Frank Hannig, Hritam Dutta, Alexey Kupriyanov, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Ronan Keryell, Bernard Pottier, Daniel Chillet, Daniel Ménard, Olivier Sentieys
2005	J	`jnl`	Defragmenting the Module Layout of a Partially Reconfigurable Device CoRR Jan van der Veen, Sándor P. Fekete, Ali Ahmadinia, Christophe Bobda, Frank Hannig, Jürgen Teich
2005	—	`conf`	Defragmenting the Module Layout of a Partially Reconfigurable Device. ERSA Jan van der Veen, Sándor P. Fekete, Mateusz Majer, Ali Ahmadinia, Christophe Bobda, Frank Hannig, Jürgen Teich
2005	—	`conf`	Output Serialization for FPGA-based and Coarse-grained Processor Arrays. ERSA Frank Hannig, Jürgen Teich
2005	—	`conf`	Using Symbolic Feasibility Tests during Design Space Exploration of Heterogeneous Multi-Processor Systems. ASAP Thomas Schlichter, Christian Haubelt, Frank Hannig, Jürgen Teich
2004	—	`conf`	Dynamic Piecewise Linear/Regular Algorithms. PARELEC Frank Hannig, Jürgen Teich
2004	—	`conf`	High-Speed Event-Driven RTL Compiled Simulation. SAMOS Alexey Kupriyanov, Frank Hannig, Jürgen Teich
2004	A	`conf`	Mapping of Regular Nested Loop Programs to Coarse-Grained Reconfigurable Arrays - Constraints and Methodology. IPDPS Frank Hannig, Hritam Dutta, Jürgen Teich
2004	—	`conf`	Regular mapping for coarse-grained reconfigurable architectures. ICASSP (5) Frank Hannig, Hritam Dutta, Jürgen Teich
2004	—	`conf`	Resource Constrained and Speculative Scheduling of an Algorithm Class with Run-Time Dependent Conditionals. ASAP Frank Hannig, Jürgen Teich
2002	B	`conf`	Energy estimation of nested loop programs. SPAA Frank Hannig, Jürgen Teich
2002	—	`conf`	Generation of Distributed Loop Control. Embedded Processor Design Challenges Marcus Bednara, Frank Hannig, Jürgen Teich
2001	B	`conf`	Design Space Exploration for Massively Parallel Processor Arrays. PaCT Frank Hannig, Jürgen Teich