Francisco Veirano

17 papers C 1Journal 7Unranked 9
YearRankTypeTitle / Venue / Authors
2026 — conf
Efficient Hardware Architecture for Artifact Cancellation in Closed-Loop Neurostimulators.
LASCAS
César Azambuya, Mateo Guerrero, Gonzalo Hernández, German Fierro, Francisco Veirano
2025 C conf
A compact, programmable, 17 mV to 10 V compliant, current source for neural stimulation.
ISCAS
Santiago Martínez, Francisco Veirano, Timothy G. Constandinou, Fernando Silveira
2024 — conf
Low Output Voltage Closed-Loop Current Source for Neural Stimulation.
LASCAS
Santiago Martínez, Francisco Veirano, Timothy G. Constandinou, Fernando Silveira
2024 — conf
Low-Power Wireless Sensor Network for Real-Time Indoor Air Quality Monitoring with CO2 Sensors.
LASCAS
Leandro Díaz, Julia Azziz, Juan P. Oliver, Francisco Veirano
2023 J jnl
Trends in Volumetric-Energy Efficiency of Implantable Neurostimulators: A Review From a Circuits and Systems Perspective.
IEEE Trans. Biomed. Circuits Syst.
Santiago Martínez, Francisco Veirano, Timothy G. Constandinou, Fernando Silveira
2022 J jnl
A Compact Lithium-Ion Battery Charger for Low-Power Applications.
IEEE Trans. Circuits Syst. II Express Briefs
Pablo Perez-Nicoli, Francisco Veirano, Fernando Silveira
2022 — conf
Near threshold pulse transit time processor for central blood pressure estimation.
LASCAS
Francisco Veirano, Pablo Perez-Nicoli, Nicolás Gammarano, German Fierro, Fernando Silveira
2019 J jnl
Optimal asymmetrical back plane biasing for energy efficient digital circuits in 28 nm UTBB FD-SOI.
Integr.
Francisco Veirano, Lirida A. B. Naviner, Fernando Silveira
2018 — conf
Gate drive losses reduction in switched-capacitor DC-DC converters.
LASCAS
Francisco Veirano, Pablo Perez-Nicoli, Pablo Castro-Lisboa, Fernando Silveira
2017 J jnl
A Low Cost System for Self Measurements of Power Consumption in Field Programmable Gate Arrays.
J. Low Power Electron.
Juan P. Oliver, Francisco Veirano, Diego A. Bouvier, Eduardo I. Boemo
2017 — conf
Asymmetrical length biasing for energy efficient digital circuits.
LASCAS
Francisco Veirano, Fernando Silveira, Lirida A. B. Naviner
2017 J jnl
Optimum nMOS/pMOS Imbalance for Energy Efficient Digital Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap.
Francisco Veirano, Lirida A. B. Naviner, Fernando Silveira
2016 J jnl
General Top/Bottom-Plate Charge Recycling Technique for Integrated Switched Capacitor DC-DC Converters.
IEEE Trans. Circuits Syst. I Regul. Pap.
Pablo Castro-Lisboa, Pablo Perez-Nicoli, Francisco Veirano, Fernando Silveira
2016 J jnl
Minimum Operating Voltage Due to Intrinsic Noise in Subthreshold Digital Logic in Nanoscale CMOS.
J. Low Power Electron.
Francisco Veirano, Fernando Silveira, Lirida A. B. Naviner
2016 — conf
Pushing minimum energy limits by optimal asymmetrical back plane biasing in 28 nm UTBB FD-SOI.
PATMOS
Francisco Veirano, Lirida A. B. Naviner, Fernando Silveira
2015 — conf
High slew-rate OTA with low quiescent current based on non-linear current mirror.
LASCAS
Pablo Perez-Nicoli, Francisco Veirano, Pablo Castro-Lisboa, Fernando Silveira
2013 — conf
Ultra low power pulse generator based on a ring oscillator with direct path current avoidance.
LASCAS
Francisco Veirano, Pablo Perez-Nicoli, Sebastian Besio, Pablo Castro-Lisboa, Fernando Silveira