Francisco V. Fernández

143 papers A 16B 5C 14Journal 47Unranked 59
YearRankTypeTitle / Venue / Authors
2025 J jnl
A Comprehensive Approach to Improving the Thermal Reliability of RTN-Based PUFs.
IEEE Trans. Circuits Syst. I Regul. Pap.
F. de Los Santos-Prieto, F. J. Rubio-Barbero, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández
2025 J jnl
From Systematic to Intelligent: Assessing AI-Empowered Optimization Techniques for Analog Building Block Sizing.
IEEE Access
Yijia Hao, Miguel Gandara, Srinjoy Mitra, Maarten Strackx, Sandy Cochran, Francisco V. Fernández, Shaolan Li, Bo Liu
2025 — conf
Towards a Reliable PUF Using Organic Thin-Film Transistors.
SMACD
F. de Los Santos-Prieto, Deborah Eric, Marc Porti, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández, Montserrat Nafría
2025 — conf
When Variability Meets Security.
IRPS
Rafael Castro-López, Javier Diaz-Fortuny, Elisenda Roca, Francisco V. Fernández
2025 J jnl
Workload Compression Techniques to Scale Defect-Centric BTI Models to the Circuit Level.
IEEE Trans. Circuits Syst. I Regul. Pap.
Andrés Santana-Andreo, Victor M. van Santen, Rafael Castro-López, Elisenda Roca, Hussam Amrouch, Francisco V. Fernández
2024 — conf
Harvesting RTN for True Random Number Generators and Physical Unclonable Functions.
SMACD
F. J. Rubio-Barbero, F. de Los Santos-Prieto, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández
2024 — conf
Optimization-based bit selection technique to improve the reliability of PUFs.
SMACD
F. de Los Santos-Prieto, F. J. Rubio-Barbero, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández
2024 — conf
Streamlined design methodology for Cell-Based DCOs.
SMACD
Andrés Santana-Andreo, Jose M. Gata-Romero, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández
2024 — conf
Towards a Digital Twin of a Time-Dependent Variability Characterization Laboratory.
SMACD
Jose M. Gata-Romero, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández
2023 — conf
A Peak Detect & Hold circuit to measure and exploit RTN in a 65-nm CMOS PUF.
SMACD
F. J. Rubio-Barbero, Eros Camacho-Ruiz, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández
2023 — conf
A Test Module for Aging Characterization of Digital Circuits.
SMACD
Jose M. Gata-Romero, Andrés Santana-Andreo, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández
2023 — conf
A detailed, cell-by-cell look into the effects of aging on an SRAM PUF using a specialized test array.
SMACD
Andrés Santana-Andreo, Pablo Saraza-Canflanca, Héctor Carrasco-Lopez, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández
2023 — conf
Challenges and solutions to the defect-centric modeling and circuit simulation of time-dependent variability.
IRPS
Javier Martín-Martínez, Javier Diaz-Fortuny, Pablo Saraza-Canflanca, Rosana Rodríguez, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández, Montserrat Nafría
2023 — conf
Design considerations for a CMOS 65-nm RTN-based PUF.
SMACD
Eros Camacho-Ruiz, F. J. Rubio-Barbero, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández
2023 — conf
Reliability evaluation of IC Ring Oscillator PUFs.
SMACD
Jose M. Gata-Romero, Elisenda Roca, Juan Núñez, Rafael Castro-López, Francisco V. Fernández
2023 — conf
Strategies for parameter extraction of the time constant distribution of time-dependent variability models for nanometer-scale devices.
SMACD
Francisco V. Fernández, Elisenda Roca, Pablo Saraza-Canflanca, Javier Martín-Martínez, Rosana Rodríguez, Montserrat Nafría, Rafael Castro-López
2022 J jnl
A DRV-based bit selection method for SRAM PUF key generation and its impact on ECCs.
Integr.
Andrés Santana-Andreo, Pablo Saraza-Canflanca, Héctor Carrasco-Lopez, Piedad Brox, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández
2022 — conf
A Smart SRAM-Cell Array for the Experimental Study of Variability Phenomena in CMOS Technologies.
IRPS
Pablo Saraza-Canflanca, Héctor Carrasco-Lopez, Andrés Santana-Andreo, Javier Diaz-Fortuny, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández
2022 C conf
A novel Physical Unclonable Function using RTN.
ISCAS
Eros Camacho-Ruiz, Rafael Castro-López, Elisenda Roca, Piedad Brox, Francisco V. Fernández
2022 — conf
A systematic approach to RTN parameter fitting based on the Maximum Current Fluctuation.
SMACD
Pablo Saraza-Canflanca, Javier Martín-Martínez, Elisenda Roca, Rafael Castro-López, Rosana Rodríguez, Montserrat Nafría, Francisco V. Fernández
2022 — conf
Characterization and analysis of BTI and HCI effects in CMOS current mirrors.
SMACD
Andrés Santana-Andreo, Pablo Martín-Lloret, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández
2022 — conf
High-level design of a novel PUF based on RTN.
SMACD
Eros Camacho-Ruiz, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández
2022 — conf
Impact of BTI and HCI on the reliability of a Majority Voter.
SMACD
Andrés Santana-Andreo, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández
2022 — conf
Machine Learning Approaches for Transformer Modeling.
SMACD
Fábio Passos, Nuno C. Lourenço, Ricardo Martins, Elisenda Roca, Rafael Castro-López, Nuno Horta, Francisco V. Fernández
2022 J jnl
On the Impact of the Biasing History on the Characterization of Random Telegraph Noise.
IEEE Trans. Instrum. Meas.
Pablo Saraza-Canflanca, Rafael Castro-López, Elisenda Roca, Javier Martín-Martínez, Rosana Rodríguez, Montserrat Nafría, Francisco V. Fernández
2022 — conf
On the use of an RTN simulator to explore the quality trade-offs of a novel RTN-based PUF.
SMACD
Eros Camacho-Ruiz, Andrés Santana-Andreo, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández
2021 J jnl
Hierarchical Yield-Aware Synthesis Methodology Covering Device-, Circuit-, and System-Level for Radiofrequency ICs.
IEEE Access
António Canelas, Fábio Passos, Nuno Lourenço, Ricardo Martins, Elisenda Roca, Rafael Castro-López, Nuno Horta, Francisco V. Fernández
2020 J jnl
A Multilevel Bottom-Up Optimization Methodology for the Automated Synthesis of RF Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Fábio Passos, Elisenda Roca, Javier J. Sieiro, Rafaella Fiorelli, Rafael Castro-López, José María López-Villegas, Francisco V. Fernández
2020 J jnl
A robust and automated methodology for the analysis of Time-Dependent Variability at transistor level.
Integr.
Pablo Saraza-Canflanca, Javier Diaz-Fortuny, Rafael Castro-López, Elisenda Roca, Javier Martín-Martínez, Rosana Rodríguez, Montserrat Nafría, Francisco V. Fernández
2020 J jnl
Chaotic Image Encryption Using Hopfield and Hindmarsh-Rose Neurons Implemented on FPGA.
Sensors
Esteban Tlelo-Cuautle, Jonathan Daniel Díaz-Muñoz, Astrid Maritza González-Zapata, Rui Li, Walter Daniel Leon-Salas, Francisco V. Fernández, Omar Guillén-Fernández, Israel Cruz-Vega
2020 J jnl
Flexible Setup for the Measurement of CMOS Time-Dependent Variability With Array-Based Integrated Circuits.
IEEE Trans. Instrum. Meas.
Javier Diaz-Fortuny, Pablo Saraza-Canflanca, Rafael Castro-López, Elisenda Roca, Javier Martín-Martínez, Rosana Rodríguez, Francisco V. Fernández, Montserrat Nafría
2020 — conf
Improving the reliability of SRAM-based PUFs in the presence of aging.
DTIS
Pablo Saraza-Canflanca, Héctor Carrasco-Lopez, Piedad Brox, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández
2020 J jnl
Ready-to-Fabricate RF Circuit Synthesis Using a Layout- and Variability-Aware Optimization-Based Methodology.
IEEE Access
Fábio Passos, Elisenda Roca, Ricardo Martins, Nuno Lourenço, Saiyd Ahyoune, Javier J. Sieiro, Rafael Castro-López, Nuno Horta, Francisco V. Fernández
2020 J jnl
Synthesis of mm-Wave Wideband Receivers in 28-nm CMOS Technology for Automotive Radar Applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Fábio Passos, Miguel Chanca, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández
2020 J jnl
Yield-aware multi-objective optimization of a MEMS accelerometer system using QMC-based methodologies.
Microelectron. J.
Murat Pak, Francisco V. Fernández, Günhan Dündar
2019 — conf
A New Time Efficient Methodology for the Massive Characterization of RTN in CMOS Devices.
IRPS
G. Pedreira, Javier Martín-Martínez, Javier Diaz-Fortuny, Pablo Saraza-Canflanca, Rosana Rodríguez, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández, Montserrat Nafría
2019 J jnl
A Versatile CMOS Transistor Array IC for the Statistical Characterization of Time-Zero Variability, RTN, BTI, and HCI.
IEEE J. Solid State Circuits
Javier Diaz-Fortuny, Javier Martín-Martínez, Rosana Rodríguez, Rafael Castro-López, Elisenda Roca, Xavier Aragonès, Enrique Barajas, Diego Mateo, Francisco V. Fernández, Montserrat Nafría
2019 J jnl
A two-step surrogate modeling strategy for single-objective and multi-objective optimization of radiofrequency circuits.
Soft Comput.
Fábio Passos, Reinier Gonzalez-Echevarria, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández
2019 — conf
An IC Array for the Statistical Characterization of Time-Dependent Variability of Basic Circuit Blocks.
SMACD
Pablo Martín-Lloret, Juan Núñez, Elisenda Roca, Rafael Castro-López, Javier Martín-Martínez, Rosana Rodríguez, Montserrat Nafría, Francisco V. Fernández
2019 — conf
Experimental Characterization of Time-Dependent Variability in Ring Oscillators.
SMACD
Juan Núñez, Elisenda Roca, Rafael Castro-López, Javier Martín-Martínez, Rosana Rodríguez, Montserrat Nafría, Francisco V. Fernández
2019 A conf
Generation of Lifetime-Aware Pareto-Optimal Fronts Using a Stochastic Reliability Simulator.
DATE
Antonio Toro-Frías, Pablo Saraza-Canflanca, Fábio Passos, Pablo Martín-Lloret, Rafael Castro-López, Elisenda Roca, Javier Martín-Martínez, Rosana Rodríguez, Montserrat Nafría, Francisco V. Fernández
2019 A conf
New method for the automated massive characterization of Bias Temperature Instability in CMOS transistors.
DATE
Pablo Saraza-Canflanca, Javier Diaz-Fortuny, Rafael Castro-López, Elisenda Roca Moreno, Javier Martín-Martínez, Rosana Rodríguez, Montserrat Nafría, Francisco V. Fernández
2019 — conf
Synthesis of mm-Wave circuits using-EM-simulated passive structure libraries.
SMACD
Fábio Passos, Elisenda Roca, Rafael Castro-López, Nuno Horta, Francisco V. Fernández
2019 — conf
TiDeVa: A Toolbox for the Automated and Robust Analysis of Time-Dependent Variability at Transistor Level.
SMACD
Pablo Saraza-Canflanca, Javier Diaz-Fortuny, Rafael Castro-López, Elisenda Roca, Javier Martín-Martínez, Rosana Rodríguez, Montserrat Nafría, Francisco V. Fernández
2019 J jnl
Two-Step RF IC Block Synthesis With Preoptimized Inductors and Full Layout Generation In-the-Loop.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ricardo Martins, Nuno Lourenço, Fábio Passos, Ricardo Povoa, António Canelas, Elisenda Roca, Rafael Castro-López, Javier J. Sieiro, Francisco V. Fernández, Nuno Horta
2018 J jnl
A Comparison of Automated RF Circuit Design Methodologies: Online Versus Offline Passive Component Design.
IEEE Trans. Very Large Scale Integr. Syst.
Fábio Passos, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández
2018 — conf
A Model Parameter Extraction Methodology Including Time-Dependent Variability for Circuit Reliability Simulation.
SMACD
Javier Diaz-Fortuny, Pablo Saraza-Canflanca, Antonio Toro-Frías, Rafael Castro-López, Javier Martín-Martínez, Elisenda Roca, Rosana Rodríguez, Francisco V. Fernández, Montserrat Nafría
2018 J jnl
A novel design methodology for the mixed-domain optimization of a MEMS accelerometer.
Integr.
Murat Pak, Francisco V. Fernández, Günhan Dündar
2018 — conf
Analysis of Body Bias and RTN-Induced Frequency Shift of Low Voltage Ring Oscillators in FDSOI Technology.
PATMOS
Enrique Barajas, Xavier Aragonès, Diego Mateo, Francesc Moll, Antonio Rubio, Javier Martín-Martínez, Rosana Rodríguez, Marc Porti, Montserrat Nafría, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández
2018 — conf
Automated Massive RTN Characterization Using a Transistor Array Chip.
SMACD
Pablo Saraza-Canflanca, Javier Diaz-Fortuny, Antonio Toro-Frías, Rafael Castro-López, Elisenda Roca, Javier Martín-Martínez, Rosana Rodríguez, Montserrat Nafría, Francisco V. Fernández
2018 C conf
CMOS Characterization and Compact Modelling for Circuit Reliability Simulation.
IOLTS
Javier Diaz-Fortuny, Javier Martín-Martínez, Rosana Rodríguez, Montserrat Nafría, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández
2018 — conf
Design Considerations of an SRAM Array for the Statistical Validation of Time-Dependent Variability Models.
SMACD
Pablo Saraza-Canflanca, D. Malagon, Fábio Passos, A. Toro, Juan Núñez, Javier Diaz-Fortuny, Rafael Castro-López, Elisenda Roca, Javier Martín-Martínez, Rosana Rodríguez, Montserrat Nafría, Francisco V. Fernández
2018 J jnl
Enhanced systematic design of a voltage controlled oscillator using a two-step optimization methodology.
Integr.
Fábio Passos, Ricardo Martins, Nuno Lourenço, Elisenda Roca, Ricardo Povoa, António Canelas, Rafael Castro-López, Nuno Horta, Francisco V. Fernández
2018 J jnl
Guest Editorial Special Issue on Selected Papers from PRIME 2017 and SMACD 2017.
Integr.
Giulia Di Capua, Nuno Horta, Francisco V. Fernández, Günhan Dündar, Salvatore Pennisi, Gaetano Palumbo, Massimo Alioto, Gianluca Giustolisi
2018 — conf
Handling the Effects of Variability and Layout Parasitics in the Automatic Synthesis of LNAs.
SMACD
Fábio Passos, Ricardo Martins, Nuno C. Lourenço, Elisenda Roca, Rafael Castro-López, Ricardo Povoa, António Canelas, Nuno Horta, Francisco V. Fernández
2018 — conf
Lifetime Calculation Using a Stochastic Reliability Simulator for Analog ICs.
SMACD
Antonio Toro-Frías, Pablo Martín-Lloret, Javier Martín-Martínez, Rafael Castro-López, Elisenda Roca, Rosana Rodríguez, Montserrat Nafría, Francisco V. Fernández
2018 J jnl
Quasi-static PEEC planar solver using a weighted combination of 2D and 3D analytical Green's functions and a predictive meshing generator.
Integr.
Saiyd Ahyoune, Javier J. Sieiro, Tomás Carrasco Carrillo, Neus Vidal, José María López-Villegas, Elisenda Roca, Francisco V. Fernández
2018 — conf
Weighted time lag plot defect parameter extraction and GPU-based BTI modeling for BTI variability.
IRPS
Victor M. van Santen, Javier Diaz-Fortuny, Hussam Amrouch, Javier Martín-Martínez, Rosana Rodríguez, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández, Jörg Henkel, Montserrat Nafría
2017 C conf
A size-adaptive time-step algorithm for accurate simulation of aging in analog ICs.
ISCAS
Pablo Martín-Lloret, Antonio Toro-Frías, Javier Martín-Martínez, Rafael Castro-López, Elisenda Roca, Rosana Rodríguez, Montserrat Nafría, Francisco V. Fernández
2017 — conf
A transistor array chip for the statistical characterization of process variability, RTN and BTI/CHC aging.
SMACD
Javier Diaz-Fortuny, Javier Martín-Martínez, Rosana Rodríguez, Montserrat Nafría, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández, Enrique Barajas, Xavier Aragonès, Diego Mateo
2017 J jnl
An Automated Design Methodology of RF Circuits by Using Pareto-Optimal Fronts of EM-Simulated Inductors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Reinier Gonzalez-Echevarria, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández, Javier J. Sieiro, José María López-Villegas, Neus Vidal
2017 B conf
An algorithm for a class of real-life multi-objective optimization problems with a sweeping objective.
CEC
Fábio Passos, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández
2017 J jnl
An inductor modeling and optimization toolbox for RF circuit design.
Integr.
Fábio Passos, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández
2017 — conf
CASE: A reliability simulation tool for analog ICs.
SMACD
Pablo Martín-Lloret, Antonio Toro-Frías, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández, Javier Martín-Martínez, Rosana Rodríguez, Montserrat Nafría
2017 — conf
Extending the frequency range of quasi-static electromagnetic solvers.
SMACD
Saiyd Ahyoune, Javier J. Sieiro, Tomás Carrasco Carrillo, Neus Vidal, José María López-Villegas, Elisenda Roca, Francisco V. Fernández
2017 — conf
Including a stochastic model of aging in a reliability simulation flow.
SMACD
Antonio Toro-Frías, Pablo Martín-Lloret, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández, Javier Martín-Martínez, Rosana Rodríguez, Montserrat Nafría
2017 J jnl
Introduction to the special issue on PRIME 2016 and SMACD 2016.
Integr.
Nuno Horta, Andrea Baschirotto, Francisco V. Fernández, Günhan Dündar, João Goes, Jorge Fernandes
2017 — conf
Layout-aware challenges and a solution for the automatic synthesis of radio-frequency IC blocks.
SMACD
Ricardo Martins, Nuno C. Lourenço, Ricardo Povoa, António Canelas, Nuno Horta, Fábio Passos, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández
2017 — conf
New mapping strategies for pre-optimized inductor sets in bottom-up RF IC sizing optimization.
SMACD
Nuno C. Lourenço, Ricardo Martins, Ricardo Povoa, António Canelas, Nuno Horta, Fábio Passos, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández
2017 — conf
Optimization of a MEMS accelerometer using a multiobjective evolutionary algorithm.
SMACD
Murat Pak, Francisco V. Fernández, Günhan Dündar
2017 J jnl
Radio-frequency inductor synthesis using evolutionary computation and Gaussian-process surrogate modeling.
Appl. Soft Comput.
Fábio Passos, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández
2017 — conf
Systematic design of a voltage controlled oscillator using a layout-aware approach.
SMACD
Fábio Passos, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández, Ricardo Martins, Nuno C. Lourenço, Ricardo Povoa, António Canelas, Nuno C. G. Horta
2017 — conf
TARS: A toolbox for statistical reliability modeling of CMOS devices.
SMACD
Javier Diaz-Fortuny, Javier Martín-Martínez, Rosana Rodríguez, Montserrat Nafría, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández
2016 A conf
Accurate synthesis of integrated RF passive components using surrogate models.
DATE
Fábio Passos, Reinier Gonzalez-Echevarria, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández
2016 — ch.
Circuit Realization of the Synchronization of Two Chaotic Oscillators with Optimized Maximum Lyapunov Exponent.
Advances in Chaos Theory and Intelligent Control
Victor Hugo Carbajal-Gomez, Esteban Tlelo-Cuautle, Francisco V. Fernández
2016 J jnl
Comparison of QMC-based yield-aware pareto front techniques for multi-objective robust analog synthesis.
Integr.
Murat Pak, Francisco V. Fernández, Günhan Dündar
2016 — conf
Frequency-dependent parameterized macromodeling of integrated inductors.
SMACD
Fábio Passos, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández, Y. Ye, Domenico Spina, Tom Dhaene
2016 J jnl
Introduction to the special issue on SMACD 2015.
Integr.
Günhan Dündar, Nuno Horta, Francisco V. Fernández
2016 — conf
Optimization of LDO voltage regulators by NSGA-II.
SMACD
Jesus Lopez-Arredondo, Esteban Tlelo-Cuautle, Francisco V. Fernández
2016 J jnl
Reliability simulation for analog ICs: Goals, solutions, and challenges.
Integr.
Antonio Toro-Frías, Pablo Martín-Lloret, Javier Martín-Martínez, Rafael Castro-López, Elisenda Roca, Rosana Rodríguez, Montserrat Nafría, Francisco V. Fernández
2016 — conf
SIDe-O: A toolbox for surrogate inductor design and optimization.
SMACD
Fábio Passos, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández
2015 — conf
A two-step layout-in-the-loop design automation tool.
NEWCAS
Gönenç Berkol, Ahmet Unutulmaz, Engin Afacan, Günhan Dündar, Francisco V. Fernández, Ali Emre Pusane, I. Faik Baskaya
2015 C conf
Design space exploration using hierarchical composition of performance models.
ISCAS
Manuel Velasco-Jimenez, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández
2015 J jnl
On the convex formulation of area for slicing floorplans.
Integr.
Ahmet Unutulmaz, Günhan Dündar, Francisco V. Fernández
2015 C conf
Physical vs. surrogate models of passive RF devices.
ISCAS
Fábio Passos, Mouna Kotti, Reinier Gonzalez-Echevarria, M. Helena Fino, Mourad Fakhfakh, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández
2014 — book
Automated Design of Analog and High-frequency Circuits - A Computational Intelligence Approach
Bo Liu, Georges G. E. Gielen, Francisco V. Fernández
2014 J jnl
Automated Generation of the Optimal Performance Trade-Offs of Integrated Inductors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Reinier Gonzalez-Echevarria, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández, Javier J. Sieiro, Neus Vidal, José María López-Villegas
2014 A conf
Implementation issues in the hierarchical composition of performance models of analog circuits.
DATE
Manuel Velasco-Jimenez, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández
2014 A conf
Model based hierarchical optimization strategies for analog design automation.
DATE
Engin Afacan, Simge Ay, Francisco V. Fernández, Günhan Dündar, I. Faik Baskaya
2013 J jnl
An Efficient Evolutionary Algorithm for Chance-Constrained Bi-Objective Stochastic Optimization.
IEEE Trans. Evol. Comput.
Bo Liu, Qingfu Zhang, Francisco V. Fernández, Georges G. E. Gielen
2013 A conf
Area optimization on fixed analog floorplans using convex area functions.
DATE
Ahmet Unutulmaz, Günhan Dündar, Francisco V. Fernández
2013 J jnl
Optimizing the positive Lyapunov exponent in multi-scroll chaotic oscillators with differential evolution algorithm.
Appl. Math. Comput.
Victor Hugo Carbajal-Gomez, Esteban Tlelo-Cuautle, Francisco V. Fernández
2012 B conf
Self-adaptive lower confidence bound: A new general and effective prescreening method for Gaussian Process surrogate model assisted evolutionary algorithms.
IEEE Congress on Evolutionary Computation
Bo Liu, Qingfu Zhang, Francisco V. Fernández, Georges G. E. Gielen
2011 — conf
A template router.
ECCTD
Ahmet Unutulmaz, Günhan Dündar, Francisco V. Fernández
2011 J jnl
Efficient and Accurate Statistical Analog Yield Optimization and Variation-Aware Circuit Sizing Based on Computational Intelligence Techniques.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Bo Liu, Francisco V. Fernández, Georges G. E. Gielen
2011 — conf
LDS - A description script for layout templates.
ECCTD
Ahmet Unutulmaz, Günhan Dündar, Francisco V. Fernández
2011 — conf
Layout-aware Pareto fronts of electronic circuits.
ECCTD
Antonio Toro-Frías, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández
2011 J jnl
Pathological Element-Based Active Device Models and Their Application to Symbolic Analysis.
IEEE Trans. Circuits Syst. I Regul. Pap.
Carlos Sánchez-López, Francisco V. Fernández, Esteban Tlelo-Cuautle, Sheldon X.-D. Tan
2010 A conf
An accurate and efficient yield optimization method for analog circuits based on computing budget allocation and memetic search technique.
DATE
Bo Liu, Francisco V. Fernández, Georges G. E. Gielen
2010 B conf
An enhanced MOEA/D-DE and its application to multiobjective analog cell sizing.
IEEE Congress on Evolutionary Computation
Bo Liu, Francisco V. Fernández, Qingfu Zhang, Murat Pak, Suha Sipahi, Georges G. E. Gielen
2010 J jnl
Generalized admittance matrix models of OTRAs and COAs.
Microelectron. J.
Carlos Sánchez-López, Francisco V. Fernández, Esteban Tlelo-Cuautle
2010 B conf
Stopping criteria in evolutionary algorithms for multi-objective performance optimization of integrated inductors.
IEEE Congress on Evolutionary Computation
Francisco V. Fernández, Juan Esteban-Muller, Elisenda Roca, Rafael Castro-López
2009 — conf
A fuzzy selection based constraint handling method for multi-objective optimization of analog cells.
ECCTD
Bo Liu, Francisco V. Fernández, Peng Gao, Georges G. E. Gielen
2009 J jnl
A memetic approach to the automatic design of high-performance analog integrated circuits.
ACM Trans. Design Autom. Electr. Syst.
Bo Liu, Francisco V. Fernández, Georges G. E. Gielen, Rafael Castro-López, Elisenda Roca
2009 J jnl
AMS/RF-CMOS circuit design for wireless transceivers.
Integr.
Rafael Castro-López, Delia Rodríguez de Llera, Mohammed Ismail, Francisco V. Fernández
2009 J jnl
Adaptive CMOS analog circuits for 4G mobile terminals - Review and state-of-the-art survey.
Microelectron. J.
José M. de la Rosa, Rafael Castro-López, Alonso Morgado, Edwin C. Becerra-Alvarez, Rocío del Río, Francisco V. Fernández, Maria Belen Pérez-Verdú
2009 J jnl
Analog circuit optimization system based on hybrid evolutionary algorithms.
Integr.
Bo Liu, Yan Wang, Zhiping Yu, Leibo Liu, Miao Li, Zheng Wang, Jing Lu, Francisco V. Fernández
2009 A conf
Analog layout synthesis - Recent advances in topological approaches.
DATE
Helmut Gräb, Florin Balasa, Rafael Castro-López, Yu-Wei Chang, Francisco V. Fernández, Mark Po-Hung Lin, Martin Strasser
2009 — conf
Applications of evolutionary computation techniques to analog, mixed-signal and RF circuit design - an overview.
ICECS
Elisenda Roca, Mourad Fakhfakh, Rafael Castro-López, Francisco V. Fernández
2009 B conf
Fuzzy selection based differential evolution algorithm for analog cell sizing capturing imprecise human intentions.
IEEE Congress on Evolutionary Computation
Bo Liu, Francisco V. Fernández, Georges G. E. Gielen
2009 — conf
Hierarchical synthesis based on pareto-optimal fronts.
ECCTD
Elisenda Roca, Rafael Castro-López, Francisco V. Fernández
2009 — conf
Less expensive and high quality stopping criteria for MC-based analog IC yield optimization.
ICECS
Bo Liu, Francisco V. Fernández, Dimitri de Jonghe, Georges G. E. Gielen
2008 J jnl
An Integrated Layout-Synthesis Approach for Analog ICs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Rafael Castro-López, Oscar Guerra, Elisenda Roca, Francisco V. Fernández
2008 J jnl
Behavioral modeling, simulation and synthesis of multi-standard wireless receivers in MATLAB/SIMULINK.
Integr.
Alonso Morgado, V. J. Rivas, Rocío del Río, Rafael Castro-López, Francisco V. Fernández, José M. de la Rosa
2008 J jnl
Clock jitter error in multi-bit continuous-time sigma-delta modulators with non-return-to-zero feedback waveform.
Microelectron. J.
Ramon Tortosa Navas, José M. de la Rosa, Francisco V. Fernández, Ángel Rodríguez-Vázquez
2008 J jnl
Editorial.
Integr.
Francisco V. Fernández
2007 C conf
A 12-bit@40MS/s Gm-C Cascade 3-2 Continuous-Time Sigma-Delta Modulator.
ISCAS
Ramon Tortosa Navas, Antonio Aceituno, José M. de la Rosa, Ángel Rodríguez-Vázquez, Francisco V. Fernández
2006 J jnl
A New High-Level Synthesis Methodology of Cascaded Continuous-Time Sigma Delta Modulators.
IEEE Trans. Circuits Syst. II Express Briefs
Ramon Tortosa Navas, José M. de la Rosa, Francisco V. Fernández, Ángel Rodríguez-Vázquez
2006 C conf
Design of a 1.2-V 130nm CMOS 13-bit@40MS/s Cascade 2-2-1 Continuous-Time Sigma-Delta Modulator.
VLSI-SoC
Ramon Tortosa Navas, Antonio Aceituno, José M. de la Rosa, Francisco V. Fernández, Ángel Rodríguez-Vázquez
2006 C conf
Design of a 1.2-V cascade continuous-time Delta Sigma modulator for broadband telecommunications.
ISCAS
Ramon Tortosa Navas, José M. de la Rosa, Ángel Rodríguez-Vázquez, Francisco V. Fernández
2006 C conf
Reconfiguration of cascade Sigma Delta modulators for multistandard GSM/Bluetooth/UMTS/WLAN transceivers.
ISCAS
Alonso Morgado, Rocío del Río, José M. de la Rosa, Fernando Medeiro, Maria Belen Pérez-Verdú, Francisco V. Fernández, Ángel Rodríguez-Vázquez
2005 — conf
Analysis of clock jitter error in multibit continuous-time ΣΔ modulators with NRZ feedback waveform.
ISCAS (4)
Ramon Tortosa Navas, José M. de la Rosa, Ángel Rodríguez-Vázquez, Francisco V. Fernández
2005 J jnl
High-level synthesis of switched-capacitor, switched-current and continuous-time ΣΔ modulators using SIMULINK-based time-domain behavioral models.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jesús Ruiz-Amaya, José M. de la Rosa, Francisco V. Fernández, Fernando Medeiro, Rocío del Río, Maria Belen Pérez-Verdú, Ángel Rodríguez-Vázquez
2004 — conf
An optimization-based tool for the high-level synthesis of discrete-time and continuous-time ΣΔ modulators in the Matlab/Simulink environment.
ISCAS (5)
Jesús Ruiz-Amaya, José M. de la Rosa, Fernando Medeiro, Francisco V. Fernández, Rocío del Río, Maria Belen Pérez-Verdú, Ángel Rodríguez-Vázquez
2004 A conf
MATLAB/SIMULINK-Based High-Level Synthesis of Discrete-Time and Continuous-Time [Sigma, Delta] Modulators.
DATE
Jesús Ruiz-Amaya, Josep Lluís de la Rosa, Fernando Medeiro, Francisco V. Fernández, Rocío del Río, Maria Belen Pérez-Verdú, Ángel Rodríguez-Vázquez
2003 — conf
Accurate VHDL-based simulation of Sigma-Delta modulators.
ISCAS (4)
Rafael Castro-López, Francisco V. Fernández, Fernando Medeiro, Ángel Rodríguez-Vázquez
2003 J jnl
Analog and mixed-signal IC design and design methodologies.
Integr.
Francisco V. Fernández
2003 A conf
Behavioural Modelling and Simulation of SigmaDelta Modulators Using Hardware Description Languages.
DATE
Rafael Castro-López, Francisco V. Fernández, Fernando Medeiro, Ángel Rodríguez-Vázquez
2003 C conf
Description Languages and Tools for the Behavioural Simulation of SD Modulators: a Comparative Survey.
FDL
Rafael Castro-López, José M. de la Rosa, R. Romay, Rocío del Río, Fernando Medeiro, Francisco V. Fernández
2001 A conf
Retargeting of mixed-signal blocks for SoCs.
DATE
Rafael Castro-López, Francisco V. Fernández, Manuel Delgado-Restituto, Ángel Rodríguez-Vázquez
2000 A conf
A Hierarchical Approach for the Symbolic Analysis of Large Analog Integrated Circuits.
DATE
Oscar Guerra, Elisenda Roca, Francisco V. Fernández, Ángel Rodríguez-Vázquez
2000 C conf
An error-controlled methodology for approximate hierarchical symbolic analysis.
ISCAS
Oscar Guerra, Juan D. Rodríguez-García, Elisenda Roca, Francisco V. Fernández, Ángel Rodríguez-Vázquez
2000 A conf
XFridge: A SPICE-Based, Portable, User-Friendly Cell-Level Sizing Tool.
DATE
F. M. Pérez-Montes, Fernando Medeiro, Rafael Domínguez-Castro, Francisco V. Fernández, Ángel Rodríguez-Vázquez
1999 A conf
An Accurate Error Control Mechanism for Simplification Before Generation Algorihms.
DATE
Oscar Guerra, Juan D. Rodríguez-García, Elisenda Roca, Francisco V. Fernández, Ángel Rodríguez-Vázquez
1999 — conf
RAPID-retargetability for reusability of application-driven quadrature D/A interface block design.
ICECS
José E. Franca, Nuno Horta, M. Pereira, João C. Vital, Rafael Castro-López, Manuel Delgado-Restituto, Francisco V. Fernández, Ángel Rodríguez-Vázquez, J. Ramos, P. Santos
1998 — conf
A simplification before and during generation methodology for symbolic large-circuit analysis.
ICECS
Oscar Guerra, Juan D. Rodríguez-García, Elisenda Roca, Francisco V. Fernández, Ángel Rodríguez-Vázquez
1997 — conf
An algorithm for numerical reference generation in symbolic analysis of large analog circuits.
ED&TC
Ignacio Garcia-Vargas, Mariano Galan, Francisco V. Fernández, Ángel Rodríguez-Vázquez
1995 C conf
A Tool for Fast Mismatch Analysis of Analog Circuits.
ISCAS
R. Rodriguez-Macias, Francisco V. Fernández, Ángel Rodríguez-Vázquez, José L. Huertas
1995 J jnl
Efficient symbolic computation of approximated small-signal characteristics of analog integrated circuits.
IEEE J. Solid State Circuits
Piet Wambacq, Francisco V. Fernández, Georges G. E. Gielen, Willy Sansen, Ángel Rodríguez-Vázquez
1994 A conf
A statistical optimization-based approach for automated sizing of analog cells.
ICCAD
Fernando Medeiro, Francisco V. Fernández, Rafael Domínguez-Castro, Ángel Rodríguez-Vázquez
1994 C conf
Pleasures, Perils and Pitfalls of Symbolic Analysis.
ISCAS
Francisco V. Fernández, Georges G. E. Gielen, Lawrence Huelsman, Agnieszka Konczykowska, Stefano Manetti, Willy M. C. Sansen, Jirí Vlach
1994 C conf
Symbolic Analysis of Large Analog Integrated Circuits by Approximation During Expression Generation.
ISCAS
Francisco V. Fernández, Piet Wambacq, Georges G. E. Gielen, Ángel Rodríguez-Vázquez, Willy M. C. Sansen
1992 A conf
Accuate simplification of large symbolic formulae.
ICCAD
Francisco V. Fernández, Ángel Rodríguez-Vázquez, J. D. Martín, José L. Huertas