Francisco José Ballester-Merelo

11 papers B 2Journal 5Unranked 4

Year	Rank	Type	Title / Venue / Authors
2021	J	`jnl`	Design, Implementation, and Configuration of Laser Systems for Vehicle Detection and Classification in Real Time. Sensors Nieves Gallego Ripoll, Luís Enrique Gómez Aguilera, Ferran Mocholí Belenguer, Antonio Mocholí Salcedo, Francisco José Ballester-Merelo
2021	J	`jnl`	The Event Detection System in the NEXT-White Detector. Sensors Raúl Esteve Bosch, José F. Toledo Alarcón, Vicente Herrero-Bosch, Ander Simón Estévez, Francesc Monrabal Capilla, Vicente Álvarez Puerta, Javier Rodríguez Samaniego, Marc Querol Segura, Francisco José Ballester-Merelo
2018	J	`jnl`	Real-Time Early Warning System Design for Pluvial Flash Floods - A Review. Sensors Melisa Acosta-Coll, Francisco José Ballester-Merelo, Marcos Martínez Peiró, Emiro De la Hoz-Franco
2008	J	`jnl`	Integer-pixel motion estimation H.264/AVC accelerator architecture with optimal memory management. Microprocess. Microsystems Armando Mora Campos, Francisco José Ballester-Merelo, Marcos Martínez Peiró, José A. Canals Esteve
2004	—	`conf`	2D-DCT on FPGA by polynomial transformation in two-dimensions. ISCAS (3) Arturo Méndez Patiño, Marcos Martínez Peiró, Francisco José Ballester-Merelo, Guillermo Payá Vayá
2004	—	`conf`	Architectures for ICT on FPGA. FPT Arturo Méndez Patiño, Marcos Martínez Peiró, Francisco José Ballester-Merelo, Guillermo Payá Vayá
2004	B	`conf`	FPGA Custom DSP for ECG Signal Analysis and Compression. FPL Marcos Martínez Peiró, Francisco José Ballester-Merelo, Guillermo Payá Vayá, Ricardo José Colom-Palero, Rafael Gadea Gironés, José Belenguer
2004	J	`jnl`	Flexible architecture for the implementation of the two-dimensional discrete wavelet transform (2D-DWT) oriented to FPGA devices. Microprocess. Microsystems Ricardo José Colom-Palero, Rafael Gadea Gironés, Francisco José Ballester-Merelo, Marcos Martínez Peiró
2003	—	`conf`	A new inverse discrete wavelet packet transform architecture. ISSPA (2) Guillermo Payá Vayá, Marcos Martínez Peiró, Francisco José Ballester-Merelo, Vicente Herrero-Bosch, Joaquín Cerdá
2003	B	`conf`	Fully Parameterized Discrete Wavelet Packet Transform Architecture Oriented to FPGA. FPL Guillermo Payá Vayá, Marcos Martínez Peiró, Francisco José Ballester-Merelo, Francisco José Mora Mas
2000	—	`conf`	Artificial Neural Network Implementation on a Single FPGA of a Pipelined On-Line Backpropagation. ISSS Rafael Gadea Gironés, Joaquín Cerdá, Francisco José Ballester-Merelo, Antonio Mocholí Salcedo