Francisco Garcia-Herrero

47 papers C 1Misc 3Journal 36Unranked 7
YearRankTypeTitle / Venue / Authors
2025 J jnl
Implementing Quantum Polar Codes in a Superconducting Processor: From State Preparation to Decoding [Focus: Quantum Software and Its Engineering].
IEEE Softw.
Handy Kurniawan, Valentin Savin, Carmen G. Almudéver, Francisco Garcia-Herrero
2025 J jnl
Predicting the Temporal Variability of Error Rates in Superconducting Quantum Processors: Mitigating Error Accuracy Loss in Queue-Based Quantum Computing Platforms [Focus: Quantum Software and its Engineering].
IEEE Softw.
Laura Rodríguez-Soriano, Francisco Garcia-Herrero, Carmen G. Almudéver
2025 J jnl
Protecting the CCSDS 123.0-B-2 Compression Algorithm Against Single-Event Upsets for Space Applications.
IEEE Trans. Computers
Daniel Báscones, Francisco Garcia-Herrero, Oscar Ruano, Carlos González, Daniel Mozos, Juan Antonio Maestro
2024 J jnl
Check-Agnosia based Post-Processor for Message-Passing Decoding of Quantum LDPC Codes.
Quantum
Julien du Crest, Francisco Garcia-Herrero, Mehdi Mhalla, Valentin Savin, Javier Valls
2024 J jnl
Efficient Low-Latency Multiplication Architecture for NIST Trinomials With RISC-V Integration.
IEEE Trans. Circuits Syst. II Express Briefs
José Luis Imaña, Luis Piñuel, Yao-Ming Kuo, Oscar Ruano, Francisco Garcia-Herrero
2024 — conf
Low-Complexity Linear Programming Based Decoding of Quantum LDPC Codes.
ICC
Sana Javed, Francisco Garcia-Herrero, Bane Vasic, Mark F. Flanagan
2024 Misc conf
Noise-Aware Compilation Techniques for Enhanced Fault-Tolerant Preparation of Polar Code States.
QCE
Handy Kurniawan, Valentin Savin, Carmen G. Almudéver, Francisco Garcia-Herrero
2024 Misc conf
On the Use of Calibration Data in Error-Aware Compilation Techniques for NISQ Devices.
QCE
Handy Kurniawan, Laura Rodríguez-Soriano, Daniele Cuomo, Carmen G. Almudéver, Francisco Garcia-Herrero
2023 J jnl
Integration of a Real-Time CCSDS 410.0-B-32 Error-Correction Decoder on FPGA-Based RISC-V SoCs Using RISC-V Vector Extension.
IEEE Trans. Aerosp. Electron. Syst.
Yao-Ming Kuo, Mark F. Flanagan, Francisco Garcia-Herrero, Oscar Ruano, Juan Antonio Maestro
2023 — conf
Layered Decoding of Quantum LDPC Codes.
ISTC
Julien du Crest, Francisco Garcia-Herrero, Mehdi Mhalla, Valentin Savin, Javier Valls
2023 J jnl
Low-Complexity Linear Programming Based Decoding of Quantum LDPC codes.
CoRR
Sana Javed, Francisco Garcia-Herrero, Bane Vasic, Mark F. Flanagan
2023 J jnl
RISC-V Galois Field ISA Extension for Non-Binary Error-Correction Codes and Classical and Post-Quantum Cryptography.
IEEE Trans. Computers
Yao-Ming Kuo, Francisco Garcia-Herrero, Oscar Ruano, Juan Antonio Maestro
2022 J jnl
ACME-2: Improving the Extraction of Essential Bits in Xilinx SRAM-Based FPGAs.
IEEE Trans. Circuits Syst. II Express Briefs
Luis Alberto Aranda, Oscar Ruano, Francisco Garcia-Herrero, Juan Antonio Maestro
2022 J jnl
Design and implementation of efficient QCA full-adders using fault-tolerant majority gates.
J. Supercomput.
Jefferson Andres Bravo-Montes, Alonso Martín-Toledano, Alfonso Sánchez-Macián, Oscar Ruano, Francisco Garcia-Herrero
2022 J jnl
Flexible and area-efficient Galois field Arithmetic Logic Unit for soft-core processors.
Comput. Electr. Eng.
Yao-Ming Kuo, Francisco Garcia-Herrero, Oscar Ruano, Juan Antonio Maestro
2022 J jnl
Reducing the Impact of Defects in Quantum-Dot Cellular Automata (QCA) Approximate Adders at Nano Scale.
IEEE Trans. Emerg. Top. Comput.
Alfonso Sánchez-Macián, Alonso Martín-Toledano, Jefferson Andres Bravo-Montes, Francisco Garcia-Herrero, Juan Antonio Maestro
2021 J jnl
Combined Symbol Error Correction and Spare Through-Silicon Vias for 3D Memories.
IEEE Trans. Emerg. Top. Comput.
Francisco Garcia-Herrero, Alfonso Sánchez-Macián, Juan Antonio Maestro
2021 J jnl
Decoding Algorithm for Quadruple-Error-Correcting Reed-Solomon Codes and Its Derived Architectures.
IEEE Trans. Circuits Syst. II Express Briefs
Francisco Garcia-Herrero, Gary McGuire, Mark F. Flanagan, Alfonso Sánchez-Macián, Juan Antonio Maestro
2021 J jnl
Fault Injection Emulation for Systems in FPGAs: Tools, Techniques and Methodology, a Tutorial.
Sensors
Oscar Ruano, Francisco Garcia-Herrero, Luis Alberto Aranda, Alfonso Sánchez-Macián, Laura Rodriguez, Juan Antonio Maestro
2021 J jnl
Low delay non-binary error correction codes based on Orthogonal Latin Squares.
Integr.
Francisco Garcia-Herrero, Alfonso Sánchez-Macián, Juan Antonio Maestro
2021 — conf
Project-Based Learning with historic buildings: immersion in real training environments for the Degree in Technical Architecture.
CINAIC
David Villanueva Valentín-Gamazo, Neslon Tuesta Durango, Francisco Garcia-Herrero, M. Isabel Mansilla Blanco, M. Cruz Rey de las Moras
2021 J jnl
Reliability Analysis of ASIC Designs With Xilinx SRAM-Based FPGAs.
IEEE Access
Luis Alberto Aranda, Oscar Ruano, Francisco Garcia-Herrero, Juan Antonio Maestro
2021 J jnl
Syndrome-Based Min-Sum vs OSD-0 Decoders: FPGA Implementation and Analysis for Quantum LDPC Codes.
IEEE Access
Javier Valls, Francisco Garcia-Herrero, Nithin Raveendran, Bane Vasic
2020 J jnl
Low-Latency and Low-Power Test-Vector Selector for Reed-Solomon's Low-Complexity Chase.
IEEE Trans. Circuits Syst.
Francisco Garcia-Herrero, Alfonso Sánchez-Macián, Juan Antonio Maestro
2020 J jnl
Radiation Hardened Digital Direct Synthesizer With CORDIC for Spaceborne Applications.
IEEE Access
Luis Alberto Aranda, Francisco Garcia-Herrero, Luis Esteban, Alfonso Sánchez-Macián, Juan Antonio Maestro
2020 J jnl
Two Behavioural Error Detection Techniques for the Cascaded Integrator-Comb Interpolation Filter Implemented on FPGA.
Circuits Syst. Signal Process.
Kyle W. Gear, Alfonso Sánchez-Macián, Francisco Garcia-Herrero, Juan Antonio Maestro
2019 J jnl
Reed-Solomon Decoder Based on a Modified ePIBMA for Low-Latency 100 Gbps Communication Systems.
Circuits Syst. Signal Process.
Gabriele Perrone, Javier Valls, Vicente Torres, Francisco Garcia-Herrero
2019 J jnl
Second Minimum Approximation for Min-Sum Decoders Suitable for High-Rate LDPC Codes.
Circuits Syst. Signal Process.
J. M. Català-Pérez, Jesus Omar Lacruz, Francisco Garcia-Herrero, Javier Valls, David Declercq
2018 — conf
Soft-decision LCC Decoder Architecture with n=4 for RS(255, 239).
NEWCAS
Vicente Torres, Javier Valls, María José Canet, Francisco Garcia-Herrero
2016 J jnl
High-Performance NB-LDPC Decoder With Reduction of Message Exchange.
IEEE Trans. Very Large Scale Integr. Syst.
Jesus Omar Lacruz, Francisco Garcia-Herrero, María José Canet, Javier Valls
2016 J jnl
Reduced-Complexity Nonbinary LDPC Decoder for High-Order Galois Fields Based on Trellis Min-Max Algorithm.
IEEE Trans. Very Large Scale Integr. Syst.
Jesus Omar Lacruz, Francisco Garcia-Herrero, María José Canet, Javier Valls
2015 C conf
A 630 Mbps non-binary LDPC decoder for FPGA.
ISCAS
Jesus Omar Lacruz, Francisco Garcia-Herrero, Ma José Canet, Javier Valls, Asuncion Perez-Pascual
2015 J jnl
One Minimum Only Trellis Decoder for Non-Binary Low-Density Parity-Check Codes.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jesus Omar Lacruz, Francisco Garcia-Herrero, Javier Valls-Coquillat, David Declercq
2015 J jnl
Reduction of Complexity for Nonbinary LDPC Decoders With Compressed Messages.
IEEE Trans. Very Large Scale Integr. Syst.
Jesus Omar Lacruz, Francisco Garcia-Herrero, Javier Valls
2015 J jnl
Simplified Trellis Min-Max Decoder Architecture for Nonbinary Low-Density Parity-Check Codes.
IEEE Trans. Very Large Scale Integr. Syst.
Jesus Omar Lacruz, Francisco Garcia-Herrero, David Declercq, Javier Valls
2014 — conf
A symbol flipping decoder for NB-LDPC relying on multiple votes.
ISTC
Francisco Garcia-Herrero, David Declercq, Javier Valls
2014 J jnl
Multiple-Vote Symbol-Flipping Decoder for Nonbinary LDPC Codes.
IEEE Trans. Very Large Scale Integr. Syst.
Francisco Garcia-Herrero, Erbao Li, David Declercq, Javier Valls
2014 J jnl
Non-Binary LDPC Decoder Based on Symbol Flipping with Multiple Votes.
IEEE Commun. Lett.
Francisco Garcia-Herrero, David Declercq, Javier Valls
2014 J jnl
Nonbinary LDPC Decoder Based on Simplified Enhanced Generalized Bit-Flipping Algorithm.
IEEE Trans. Very Large Scale Integr. Syst.
Francisco Garcia-Herrero, María José Canet, Javier Valls
2014 J jnl
Reliability-Based Iterative Decoding Algorithm for LDPC Codes With Low Variable-Node Degree.
IEEE Commun. Lett.
J. M. Català-Pérez, Francisco Garcia-Herrero, Javier Valls, K. Liu, Shu Lin
2013 J jnl
Architecture of Generalized Bit-Flipping Decoding for High-Rate Non-binary LDPC Codes.
Circuits Syst. Signal Process.
Francisco Garcia-Herrero, María José Canet, Javier Valls
2013 — conf
High-speed NB-LDPC decoder for wireless applications.
ISPACS
Francisco Garcia-Herrero, Ma José Canet, Javier Valls
2013 Misc conf
Low latency T-EMS decoder for non-binary LDPC codes.
ACSSC
Erbao Li, Francisco Garcia-Herrero, David Declercq, Kiran K. Gunnam, Jesus Omar Lacruz, Javier Valls
2012 — conf
Decoder for an enhanced serial generalized bit flipping algorithm.
ICECS
Francisco Garcia-Herrero, María José Canet, Javier Valls
2012 J jnl
High-Throughput Interpolator Architecture for Low-Complexity Chase Decoding of RS Codes.
IEEE Trans. Very Large Scale Integr. Syst.
Francisco Garcia-Herrero, María José Canet, Javier Valls, Pramod Kumar Meher
2012 J jnl
Serial Symbol-Reliability Based Algorithm for Decoding Non-Binary LDPC Codes.
IEEE Commun. Lett.
Francisco Garcia-Herrero, María José Canet, Javier Valls, Mark F. Flanagan
2011 J jnl
High-Speed RS(255, 239) Decoder Based on LCC Decoding.
Circuits Syst. Signal Process.
Francisco Garcia-Herrero, Javier Valls, Pramod Kumar Meher