Francesco Restuccia

34 papers A* 2A 5B 1C 1Misc 2Journal 22Unranked 1
YearRankTypeTitle / Venue / Authors
2026 J jnl
FireBridge: Cycle-Accurate Hardware + Firmware Co-Verification for Modern Accelerators.
CoRR
G. Abarajithan, Zhenghua Ma, Francesco Restuccia, Ryan Kastner
2025 J jnl
A Reliable, Time-Predictable Heterogeneous SoC for AI-Enhanced Mixed-Criticality Edge Applications.
CoRR
Angelo Garofalo, Alessandro Ottaviano, Matteo Perotti, Thomas Benz, Yvan Tortorella, Robert Balas, Michael Rogenmoser, Chi Zhang, Luca Bertaccini, Nils Wistoff, Maicol Ciani, Cyril Koenig, Mattia Sinigaglia, Luca Valente, Paul Scheffler, Manuel Eggimann, Matheus A. Cavalcante, Francesco Restuccia, Alessandro Biondi, Francesco Conti, Frank K. Gürkaynak, Davide Rossi, Luca Benini
2025 J jnl
A Reliable, Time-Predictable Heterogeneous SoC for AI-Enhanced Mixed-Criticality Edge Applications.
IEEE Trans. Circuits Syst. II Express Briefs
Angelo Garofalo, Alessandro Ottaviano, Matteo Perotti, Thomas Benz, Yvan Tortorella, Robert Balas, Michael Rogenmoser, Chi Zhang, Luca Bertaccini, Nils Wistoff, Maicol Ciani, Cyril Koenig, Mattia Sinigaglia, Luca Valente, Paul Scheffler, Manuel Eggimann, Matheus A. Cavalcante, Francesco Restuccia, Alessandro Biondi, Francesco Conti, Frank K. Gürkaynak, Davide Rossi, Luca Benini
2025 J jnl
AXI-REALM: Safe, Modular and Lightweight Traffic Monitoring and Regulation for Heterogeneous Mixed-Criticality Systems.
CoRR
Thomas Benz, Alessandro Ottaviano, Chaoqun Liang, Robert Balas, Angelo Garofalo, Francesco Restuccia, Alessandro Biondi, Davide Rossi, Luca Benini
2025 J jnl
AXI-REALM: Safe, Modular and Lightweight Traffic Monitoring and Regulation for Heterogeneous Mixed-Criticality Systems.
IEEE Trans. Computers
Thomas Benz, Alessandro Ottaviano, Chaoqun Liang, Robert Balas, Angelo Garofalo, Francesco Restuccia, Alessandro Biondi, Davide Rossi, Luca Benini
2025 J jnl
BASTION: A Framework for Secure Third-Party IP Integration in NoC-based SoC Platforms.
IACR Trans. Cryptogr. Hardw. Embed. Syst.
Francesco Restuccia, Zhenghua Ma, Joseph Zuckerman, Andres Meza, Biruk B. Seyoum, Luca P. Carloni, Ryan Kastner
2024 A conf
AXI-REALM: A Lightweight and Modular Interconnect Extension for Traffic Regulation and Monitoring of Heterogeneous Real-Time SoCs.
DATE
Thomas Benz, Alessandro Ottaviano, Robert Balas, Angelo Garofalo, Francesco Restuccia, Alessandro Biondi, Luca Benini
2024 J jnl
CGRA4ML: A Framework to Implement Modern Neural Networks for Scientific Edge Computing.
CoRR
G. Abarajithan, Zhenghua Ma, Zepeng Li, Shrideep Koparkar, Ravidu Munasinghe, Francesco Restuccia, Ryan Kastner
2024 J jnl
TOP: Towards Open & Predictable Heterogeneous SoCs.
CoRR
Luca Valente, Francesco Restuccia, Davide Rossi, Ryan Kastner, Luca Benini
2024 J jnl
TOP: Towards Open & Predictable Heterogeneous SoCs.
IEEE Trans. Computers
Luca Valente, Francesco Restuccia, Davide Rossi, Ryan Kastner, Luca Benini
2024 A conf
eXpect: On the Security Implications of Violations in AXI Implementations.
ICCAD
Melisande Zonta-Roudes, Andres Meza, Nora Hinderling, Lucas Deutschmann, Francesco Restuccia, Ryan Kastner, Shweta Shinde
2023 J jnl
A Framework for Design, Verification, and Management of SoC Access Control Systems.
IEEE Trans. Computers
Francesco Restuccia, Andres Meza, Ryan Kastner, Jason Oberg
2023 J jnl
AXI-REALM: A Lightweight and Modular Interconnect Extension for Traffic Regulation and Monitoring of Heterogeneous Real-Time SoCs.
CoRR
Thomas Benz, Alessandro Ottaviano, Robert Balas, Angelo Garofalo, Francesco Restuccia, Alessandro Biondi, Luca Benini
2023 J jnl
Bounding Memory Access Times in Multi-Accelerator Architectures on FPGA SoCs.
IEEE Trans. Computers
Francesco Restuccia, Marco Pagani, Alessandro Biondi, Mauro Marinoni, Giorgio C. Buttazzo
2023 J jnl
Isadora: automated information-flow property generation for hardware security verification.
J. Cryptogr. Eng.
Calvin Deutschbein, Andres Meza, Francesco Restuccia, Ryan Kastner, Cynthia Sturton
2023 J jnl
Security Verification of the OpenTitan Hardware Root of Trust.
IEEE Secur. Priv.
Andres Meza, Francesco Restuccia, Jason Oberg, Dominic Rizzo, Ryan Kastner
2023 Misc conf
Special Session: CAD for Hardware Security - Promising Directions for Automation of Security Assurance.
VTS
Sohrab Aftabjahani, Mark Tehranipoor, Farimah Farahmandi, Bulbul Ahmed, Ryan Kastner, Francesco Restuccia, Andres Meza, Kaki Ryan, Nicole Fern, Jasper Van Woudenberg, Rajesh Velegalati, Cees-Bart Breunesse, Cynthia Sturton, Calvin Deutschbein
2022 J jnl
A Remote Control System for Emergency Ventilators During SARS-CoV-2.
IEEE Embed. Syst. Lett.
Michael Barrow, Francesco Restuccia, Mustafa S. Gobulukoglu, Enrico Rossi, Ryan Kastner
2022 J jnl
ARTe: Providing real-time multitasking to Arduino.
J. Syst. Softw.
Francesco Restuccia, Marco Pagani, Agostino Mascitti, Michael Barrow, Mauro Marinoni, Alessandro Biondi, Giorgio C. Buttazzo, Ryan Kastner
2022 A* conf
Automating hardware security property generation: invited.
DAC
Ryan Kastner, Francesco Restuccia, Andres Meza, Sayak Ray, Jason M. Fung, Cynthia Sturton
2022 J jnl
Cut and Forward: Safe and Secure Communication for FPGA System on Chips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Francesco Restuccia, Ryan Kastner
2022 C conf
Hardware Acceleration of Deep Neural Networks for Autonomous Driving on FPGA-based SoC.
DSD
Gerlando Sciangula, Francesco Restuccia, Alessandro Biondi, Giorgio C. Buttazzo
2022 A conf
PAC-PL: Enabling Control-Flow Integrity with Pointer Authentication in FPGA SoC Platforms.
RTAS
Gabriele Serra, Pietro Fara, Giorgiomaria Cicero, Francesco Restuccia, Alessandro Biondi
2022 J jnl
Toward Hardware Security Property Generation at Scale.
IEEE Secur. Priv.
Calvin Deutschbein, Andres Meza, Francesco Restuccia, Matthew Gregoire, Ryan Kastner, Cynthia Sturton
2021 J jnl
A Methodology For Creating Information Flow Specifications of Hardware Designs.
CoRR
Calvin Deutschbein, Andres Meza, Francesco Restuccia, Ryan Kastner, Cynthia Sturton
2021 J jnl
AKER: A Design and Verification Framework for Safe andSecure SoC Access Control.
CoRR
Francesco Restuccia, Andres Meza, Ryan Kastner
2021 A conf
Aker: A Design and Verification Framework for Safe and Secure SoC Access Control.
ICCAD
Francesco Restuccia, Andres Meza, Ryan Kastner
2021 — conf
Isadora: Automated Information Flow Property Generation for Hardware Designs.
ASHES@CCS
Calvin Deutschbein, Andres Meza, Francesco Restuccia, Ryan Kastner, Cynthia Sturton
2021 A conf
Time-Predictable Acceleration of Deep Neural Networks on FPGA SoC Platforms.
RTSS
Francesco Restuccia, Alessandro Biondi
2020 A* conf
AXI HyperConnect: A Predictable, Hypervisor-level Interconnect for Hardware Accelerators in FPGA SoC.
DAC
Francesco Restuccia, Alessandro Biondi, Mauro Marinoni, Giorgiomaria Cicero, Giorgio C. Buttazzo
2020 J jnl
Modeling and Analysis of Bus Contention for Hardware Accelerators in FPGA SoCs (Artifact).
Dagstuhl Artifacts Ser.
Francesco Restuccia, Marco Pagani, Alessandro Biondi, Mauro Marinoni, Giorgio C. Buttazzo
2020 B conf
Modeling and Analysis of Bus Contention for Hardware Accelerators in FPGA SoCs.
ECRTS
Francesco Restuccia, Marco Pagani, Alessandro Biondi, Mauro Marinoni, Giorgio C. Buttazzo
2020 Misc conf
Safely Preventing Unbounded Delays During Bus Transactions in FPGA-based SoC.
FCCM
Francesco Restuccia, Alessandro Biondi, Mauro Marinoni, Giorgio C. Buttazzo
2019 J jnl
Is Your Bus Arbiter Really Fair? Restoring Fairness in AXI Interconnects for FPGA SoCs.
ACM Trans. Embed. Comput. Syst.
Francesco Restuccia, Marco Pagani, Alessandro Biondi, Mauro Marinoni, Giorgio C. Buttazzo