Francesco Pappalardo

13 papers A 1C 1Journal 5Unranked 6
YearRankTypeTitle / Venue / Authors
2023 A conf
Using High-Level Synthesis to model System Verilog procedural timing controls.
DATE
Luca Ezio Pozzoni, Fabrizio Ferrandi, Loris Mendola, Alfio Antonino Palazzo, Francesco Pappalardo
2013 J jnl
Auto-Tuning and Fractional Order Controller Implementation on Hardware in the Loop System.
J. Optim. Theory Appl.
Riccardo Caponetto, Giovanni Dongola, Francesco Pappalardo, V. Tomasello
2012 J jnl
Fractional-order simulation tool for the brainstem vestibulo-ocular reflex (VOR).
Signal Image Video Process.
Riccardo Caponetto, Giovanni Dongola, Francesco Pappalardo
2011 — conf
A 10 pJ/cycle ultra-low-voltage 32-bit microprocessor system-on-chip.
ESSCIRC
Nathan Ickes, Yildiz Sinangil, Francesco Pappalardo, Elio Guidetti, Anantha P. Chandrakasan
2007 J jnl
A Low Power, Scalable and Runtime Customizable Microprocessor Architecture for Image Processing.
J. Low Power Electron.
Giuseppe Notarangelo, Francesco Pappalardo, Elena Salurso, Elio Guidetti
2007 J jnl
Analysis and Implementation of a Novel Leading Zero Anticipation Algorithm for Floating-Point Arithmetic Units.
IEEE Trans. Circuits Syst. II Express Briefs
Mauro Olivieri, Francesco Pappalardo, Simone Smorfa, Giuseppe Visalli
2005 — conf
Design issues for bus switch systems in deep sub-micro metric CMOS technologies.
Circuits, Signals, and Systems
Mauro Olivieri, Francesco Pappalardo, Giuseppe Visalli
2005 — conf
Encoding circuits for low power optical on-chip communications.
ISCAS (5)
Mauro Olivieri, Francesco Pappalardo, Giuseppe Visalli
2005 — conf
statistical analysis, for reducing the energy dissipation in a bus-switch encoder.
Circuits, Signals, and Systems
Mauro Olivieri, Francesco Pappalardo, Giuseppe Visalli
2004 — conf
An application-oriented analysis of power/precision trade-off in fixed and floating-point arithmetic units for VLSI processors.
Circuits, Signals, and Systems
Francesco Pappalardo, Giuseppe Visalli, Mirko Scarana
2004 J jnl
Bus-switch coding for reducing power dissipation in off-chip buses.
IEEE Trans. Very Large Scale Integr. Syst.
Mauro Olivieri, Francesco Pappalardo, Giuseppe Visalli
2002 — conf
Evaluation on power reduction applying gated clock approaches.
ISCAS (4)
Gaetano Palumbo, Francesco Pappalardo, S. Sannella
2002 C conf
Low Power Strategy for a TFT Controller.
DSD
Giuseppe Notarangelo, Marco Gibilaro, Francesco Pappalardo, Agatino Pennisi, Gaetano Palumbo