Francesco Menichelli

57 papers A 1B 1C 4Misc 1Journal 20Unranked 29
YearRankTypeTitle / Venue / Authors
2026 J jnl
HD-CB: The First Exploration of Hyperdimensional Computing for Contextual Bandits Problems.
IEEE Open J. Comput. Soc.
Marco Angioli, Antonello Rosato, Marcello Barbirotta, Rocco Martino, Francesco Menichelli, Mauro Olivieri
2025 J jnl
Efficient Implementation of LinearUCB through Algorithmic Improvements and Vector Computing Acceleration for Embedded Learning Systems.
CoRR
Marco Angioli, Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri
2025 J jnl
Efficient Implementation of LinearUCB through Algorithmic Improvements and Vector Computing Acceleration for Embedded Learning Systems.
ACM Trans. Embed. Comput. Syst.
Marco Angioli, Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri
2025 J jnl
HD-CB: The First Exploration of Hyperdimensional Computing for Contextual Bandits Problems.
CoRR
Marco Angioli, Antonello Rosato, Marcello Barbirotta, Rocco Martino, Francesco Menichelli, Mauro Olivieri
2025 — conf
Re-Architecting RISC-V: A 64-Bit Take on Interleaved Multi-threading.
ApplePies
Andrea Marcelli, Marco Pisani, Rocco Martino, Abdallah Cheikh, Francesco Menichelli, Mauro Olivieri
2024 J jnl
A RISC-V Fault-Tolerant Soft-Processor Based on Full/Partial Heterogeneous Dual-Core Protection.
IEEE Access
Francesco Vigli, Marcello Barbirotta, Abdallah Cheikh, Francesco Menichelli, Antonio Mastrandrea, Mauro Olivieri
2024 B conf
AeneasHDC: An Automatic Framework for Deploying Hyperdimensional Computing Models on FPGAs.
IJCNN
Marco Angioli, Saeid Jamili, Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Antonello Rosato, Mauro Olivieri
2024 — conf
Alternative Implementations of Error Correcting Codes in Register Files of a RISC-V Safety Critical Processor.
ApplePies
Marcello Barbirotta, Marco Angioli, Antonio Mastrandrea, Abdallah Cheikh, Francesco Menichelli, Mauro Olivieri
2024 J jnl
Design, Implementation and Evaluation of a New Variable Latency Integer Division Scheme.
IEEE Trans. Computers
Marco Angioli, Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Saeid Jamili, Mauro Olivieri
2024 — conf
Dual-Modular-Redundancy Voting Circuits for Single-Event-Transient Mitigation.
DFT
Marcello Barbirotta, Marco Angioli, Antonio Mastrandrea, Francesco Menichelli, Abdallah Cheikh, Mauro Olivieri
2024 J jnl
Dynamic Triple Modular Redundancy in Interleaved Hardware Threads: An Alternative Solution to Lockstep Multi-Cores for Fault-Tolerant Systems.
IEEE Access
Marcello Barbirotta, Francesco Menichelli, Abdallah Cheikh, Antonio Mastrandrea, Marco Angioli, Mauro Olivieri
2024 — conf
Special Session: SE-UVM, an Integrated Simulation Environment for Single Event Induced Failures Characterization and its Application to the CV32E40P Processor.
DFT
Marcello Barbirotta, Marco Angioli, Antonio Mastrandrea, Francesco Menichelli, Abdallah Cheikh, Mauro Olivieri
2023 — conf
A Universal Hardware Emulator for Verification IPs on FPGA: A Novel and Low-Cost Approach.
ApplePies
Saeid Jamili, Antonio Mastrandrea, Abdallah Cheikh, Marcello Barbirotta, Francesco Menichelli, Marco Angioli, Mauro Olivieri
2023 — conf
Heterogeneous Tightly-Coupled Dual Core Architecture Against Single Event Effects.
ApplePies
Marcello Barbirotta, Francesco Menichelli, Antonio Mastrandrea, Abdallah Cheikh, Marco Angioli, Saeid Jamili, Mauro Olivieri
2023 — conf
Single Event Transient Reliability Analysis on a Fault-Tolerant RISC-V Microprocessor Design.
ApplePies
Marcello Barbirotta, Marco Angioli, Antonio Mastrandrea, Abdallah Cheikh, Saeid Jamili, Francesco Menichelli, Mauro Olivieri
2022 — conf
Analysis of a Fault Tolerant Edge-Computing Microarchitecture Exploiting Vector Acceleration.
PRIME
Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri
2022 — conf
Contextual Bandits Algorithms for Reconfigurable Hardware Accelerators.
ApplePies
Marco Angioli, Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Saeid Jamili, Mauro Olivieri
2022 J jnl
Design and Evaluation of Buffered Triple Modular Redundancy in Interleaved-Multi-Threading Processors.
IEEE Access
Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri
2022 — conf
Implementation of Dynamic Acceleration Unit Exchange on a RISC-V Soft-Processor.
ApplePies
Saeid Jamili, Abdallah Cheikh, Antonio Mastrandrea, Marcello Barbirotta, Francesco Menichelli, Marco Angioli, Mauro Olivieri
2021 — conf
A Fault Tolerant soft-core obtained from an Interleaved-Multi- Threading RISC- V microprocessor design.
DFT
Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Francesco Vigli, Mauro Olivieri
2021 C conf
Efficient Machine Learning Algorithm for Embedded Tactile Data Processing.
ISCAS
Moustafa Saleh, Ali Ibrahim, Francesco Menichelli, Yasser Mohanna, Maurizio Valle
2021 J jnl
Klessydra-T: Designing Vector Coprocessors for Multithreaded Edge-Computing Cores.
IEEE Micro
Abdallah Cheikh, Stefano Sordillo, Antonio Mastrandrea, Francesco Menichelli, Giuseppe Scotti, Mauro Olivieri
2020 — conf
Fault resilience analysis of a RISC-V microprocessor design through a dedicated UVM environment.
DFT
Marcello Barbirotta, Antonio Mastrandrea, Francesco Menichelli, Francesco Vigli, Luigi Blasi, Abdallah Cheikh, Stefano Sordillo, Fabio Di Gennaro, Mauro Olivieri
2020 J jnl
Klessydra-T: Designing Vector Coprocessors for Multi-Threaded Edge-Computing Cores.
CoRR
Abdallah Cheikh, Stefano Sordillo, Antonio Mastrandrea, Francesco Menichelli, Giuseppe Scotti, Mauro Olivieri
2019 — conf
A RISC-V Fault-Tolerant Microcontroller Core Architecture Based on a Hardware Thread Full/Partial Protection and a Thread-Controlled Watch-Dog Timer.
ApplePies
Luigi Blasi, Francesco Vigli, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri
2019 — conf
Efficient Mathematical Accelerator Design Coupled with an Interleaved Multi-threading RISC-V Microprocessor.
ApplePies
Abdallah Cheikh, Stefano Sordillo, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri
2019 J jnl
Full System Emulation of Approximate Memory Platforms with AppropinQuo.
J. Low Power Electron.
Giulia Stazi, Antonio Mastrandrea, Mauro Olivieri, Francesco Menichelli
2019 — conf
Quality Aware Approximate Memory in RISC-V Linux Kernel.
PRIME
Giulia Stazi, Antonio Mastrandrea, Mauro Olivieri, Francesco Menichelli
2019 — conf
Quality Aware Selective ECC for Approximate DRAM.
ApplePies
Giulia Stazi, Antonio Mastrandrea, Mauro Olivieri, Francesco Menichelli
2018 — conf
AppropinQuo: A Platform Emulator for Exploring the Approximate Memory Design Space.
NGCAS
Giulia Stazi, Antonio Mastrandrea, Mauro Olivieri, Francesco Menichelli
2018 — conf
Approximate Memory Support for Linux Early Allocators in ARM Architectures.
ApplePies
Giulia Stazi, Antonio Mastrandrea, Mauro Olivieri, Francesco Menichelli
2018 C conf
Characterizing noise pulse effects on the power consumption of idle digital cells.
ISCAS
Mauro Olivieri, Usman Khalid, Antonio Mastrandrea, Francesco Menichelli
2018 — conf
Impact of Approximate Memory Data Allocation on a H.264 Software Video Encoder.
ISC Workshops
Giulia Stazi, Lorenzo Adani, Antonio Mastrandrea, Mauro Olivieri, Francesco Menichelli
2018 — conf
Synthesis Time Reconfigurable Floating Point Unit for Transprecision Computing.
ApplePies
Giulia Stazi, Federica Silvestri, Antonio Mastrandrea, Mauro Olivieri, Francesco Menichelli
2017 — conf
Investigation on the Optimal Pipeline Organization in RISC-V Multi-threaded Soft Processor Cores.
NGCAS
Mauro Olivieri, Abdallah Cheikh, Gianmarco Cerutti, Antonio Mastrandrea, Francesco Menichelli
2017 — conf
The Microarchitecture of a Multi-threaded RISC-V Compliant Processing Core Family for IoT End-Nodes.
ApplePies
Abdallah Cheikh, Gianmarco Cerutti, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri
2017 J jnl
The microarchitecture of a multi-threaded RISC-V compliant processing core family for IoT end-nodes.
CoRR
Abdallah Cheikh, Gianmarco Cerutti, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri
2016 — conf
An Emulator for Approximate Memory Platforms Based on QEmu.
ApplePies
Francesco Menichelli, Giulia Stazi, Antonio Mastrandrea, Mauro Olivieri
2015 — conf
Narrowband Delay Tolerant Protocols for WSN Applications: Characterization and Selection Guide.
ApplePies
Claudio Santo Malavenda, Francesco Menichelli, Mauro Olivieri
2014 — conf
A Model-Based Methodology to Generate Code for Timer Units.
ApplePies
Marco Marazza, Francesco Menichelli, Mauro Olivieri, Orlando Ferrante, Alberto Ferrari
2014 — conf
A Platform-Based Emulator for Mass-Storage Flash Cards Evaluation in Embedded Systems.
ApplePies
Francesco Menichelli, Mauro Olivieri
2014 J jnl
A Regulation-Based Security Evaluation Method for Data Link in Wireless Sensor Network.
J. Comput. Networks Commun.
Claudio Santo Malavenda, Francesco Menichelli, Mauro Olivieri
2013 — conf
Wireless and Ad Hoc Sensor Networks: An Industrial Example Using Delay Tolerant, Low Power Protocols for Security-Critical Applications.
ApplePies
Claudio Santo Malavenda, Francesco Menichelli, Mauro Olivieri
2012 J jnl
Delay-Tolerant, Low-Power Protocols for Large Security-Critical Wireless Sensor Networks.
J. Comput. Networks Commun.
Claudio Santo Malavenda, Francesco Menichelli, Mauro Olivieri
2012 — conf
Scalable virtual prototyping of distributed embedded control in a modern elevator system.
SIES
Alberto Ferrari, Marco Carloni, Alessandro Mignogna, Francesco Menichelli, David Ginsberg, Eelco Scholte, Dang Nguyen
2011 C conf
Performance evaluation of Jpeg2000 implementation on VLIW cores, SIMD cores and multi-cores.
ISCAS
Francesco Menichelli, Mauro Olivieri, Simone Smorfa
2010 J jnl
TikTak: A Scalable Simulator of Wireless Sensor Networks Including Hardware/Software Interaction.
Wirel. Sens. Netw.
Francesco Menichelli, Mauro Olivieri
2009 J jnl
Static Minimization of Total Energy Consumption in Memory Subsystem for Scratchpad-Based Systems-on-Chips.
IEEE Trans. Very Large Scale Integr. Syst.
Francesco Menichelli, Mauro Olivieri
2008 J jnl
High-Level Side-Channel Attack Modeling and Simulation for Security-Critical Systems on Chips.
IEEE Trans. Dependable Secur. Comput.
Francesco Menichelli, Renato Menicocci, Mauro Olivieri, Alessandro Trifiletti
2007 J jnl
Testing power-analysis attack susceptibility in register-transfer level designs.
IET Inf. Secur.
Marco Bucci, Raimondo Luzzi, Francesco Menichelli, Renato Menicocci, Mauro Olivieri, Alessandro Trifiletti
2006 C conf
Side channel analysis resistant design flow.
ISCAS
Manfred Josef Aigner, Stefan Mangard, Francesco Menichelli, Renato Menicocci, Mauro Olivieri, Thomas Popp, Giuseppe Scotti, Alessandro Trifiletti
2005 J jnl
MPARM: Exploring the Multi-Processor SoC Design Space with SystemC.
J. VLSI Signal Process.
Luca Benini, Davide Bertozzi, Alessandro Bogliolo, Francesco Menichelli, Mauro Olivieri
2005 — conf
Software optimization of the JPEG2000 algorithm on a VLIW CPU core for system-on-chip implementation.
Circuits, Signals, and Systems
Francesco Menichelli, Mauro Olivieri, Simone Smorfa, Irene Zaccardini
2005 — —
Tecniche di analisi e progetto di architetture di sistemi a microprocessore integrati su singolo chip caratterizzati da criticità nei consumi di potenza.
Francesco Menichelli
2004 J jnl
A Class of Code Compression Schemes for Reducing Power Consumption in Embedded Microprocessor Systems.
IEEE Trans. Computers
Luca Benini, Francesco Menichelli, Mauro Olivieri
2004 A conf
A Simulation-Based Power-Aware Architecture Exploration of a Multiprocessor System-on-Chip Design.
DATE
Francesco Menichelli, Mauro Olivieri, Luca Benini, Monica Donno, Labros Bisdounis
2004 Misc conf
A post-compiler approach to scratchpad mapping of code.
CASES
Federico Angiolini, Francesco Menichelli, Alberto Ferrero, Luca Benini, Mauro Olivieri