Francesco Conti

193 papers A* 4A 13B 2C 8Misc 4Journal 110Unranked 51

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Multimodal On-Device Learning for Monocular Depth Estimation on Ultralow-Power MCUs. IEEE Internet Things J. Davide Nadalini, Manuele Rusci, Elia Cereda, Luca Benini, Francesco Conti, Daniele Palossi
2026	J	`jnl`	Tiny-DroNeRF: Tiny Neural Radiance Fields aboard Federated Learning-enabled Nano-drones. CoRR Ilenia Carboni, Elia Cereda, Lorenzo Lamberti, Daniele Malpetti, Francesco Conti, Daniele Palossi
2026	J	`jnl`	TrainDeeploy: Hardware-Accelerated Parameter-Efficient Fine-Tuning of Small Transformer Models at the Extreme Edge. CoRR Run Wang, Victor J. B. Jung, Philip Wiese, Francesco Conti, Alessio Burrello, Luca Benini
2025	J	`jnl`	A Flexible Template for Edge Generative AI With High-Accuracy Accelerated Softmax and GELU. IEEE J. Emerg. Sel. Topics Circuits Syst. Andrea Belano, Yvan Tortorella, Angelo Garofalo, Luca Benini, Davide Rossi, Francesco Conti
2025	J	`jnl`	A Reliable, Time-Predictable Heterogeneous SoC for AI-Enhanced Mixed-Criticality Edge Applications. CoRR Angelo Garofalo, Alessandro Ottaviano, Matteo Perotti, Thomas Benz, Yvan Tortorella, Robert Balas, Michael Rogenmoser, Chi Zhang, Luca Bertaccini, Nils Wistoff, Maicol Ciani, Cyril Koenig, Mattia Sinigaglia, Luca Valente, Paul Scheffler, Manuel Eggimann, Matheus A. Cavalcante, Francesco Restuccia, Alessandro Biondi, Francesco Conti, Frank K. Gürkaynak, Davide Rossi, Luca Benini
2025	J	`jnl`	A Reliable, Time-Predictable Heterogeneous SoC for AI-Enhanced Mixed-Criticality Edge Applications. IEEE Trans. Circuits Syst. II Express Briefs Angelo Garofalo, Alessandro Ottaviano, Matteo Perotti, Thomas Benz, Yvan Tortorella, Robert Balas, Michael Rogenmoser, Chi Zhang, Luca Bertaccini, Nils Wistoff, Maicol Ciani, Cyril Koenig, Mattia Sinigaglia, Luca Valente, Paul Scheffler, Manuel Eggimann, Matheus A. Cavalcante, Francesco Restuccia, Alessandro Biondi, Francesco Conti, Frank K. Gürkaynak, Davide Rossi, Luca Benini
2025	J	`jnl`	A Survey on Deep Learning Hardware Accelerators for Heterogeneous HPC Platforms. ACM Comput. Surv. Cristina Silvano, Daniele Ielmini, Fabrizio Ferrandi, Leandro Fiorin, Serena Curzel, Luca Benini, Francesco Conti, Angelo Garofalo, Cristian Zambelli, Enrico Calore, Sebastiano Fabio Schifano, Maurizio Palesi, Giuseppe Ascia, Davide Patti, Nicola Petra, Davide De Caro, Luciano Lavagno, Teodoro Urso, Valeria Cardellini, Gian Carlo Cardarilli, Robert Birke, Stefania Perri
2025	—	`conf`	Architecture, Simulation and Software Stack to Support Post-CMOS Accelerators: The ARCHYTAS Project. ISVLSI Giovanni Agosta, Stefano Cherubin, Derek Christ, Francesco Conti, Asbjørn Djupdal, Matthias Jung, Georgios Keramidas, Roberto Passerone, Paolo Rech, Elisa Ricci, Philippe Velha, Flavio Vella, Kasim Sinan Yildirim, Nils Wilbert
2025	J	`jnl`	Architecture, Simulation and Software Stack to Support Post-CMOS Accelerators: The ARCHYTAS Project. CoRR Giovanni Agosta, Stefano Cherubin, Derek Christ, Francesco Conti, Asbjørn Djupdal, Matthias Jung, Georgios Keramidas, Roberto Passerone, Paolo Rech, Elisa Ricci, Philippe Velha, Flavio Vella, Kasim Sinan Yildirim, Nils Wilbert
2025	A	`conf`	Distributed Inference with Minimal Off-Chip Traffic for Transformers on Low-Power MCUs. DATE Severin Bochem, Victor J. B. Jung, Arpan Suravi Prasad, Francesco Conti, Luca Benini
2025	C	`conf`	Exploring MRAM for On-Chip Texture Storage in Rendering Applications. VLSI-SoC Nicolás Villegas, Stefano Romanini, Moritz Scherer, Warren Hunt, Syed Shakib Sarwar, Barbara De Salvo, Chiao Liu, Francesco Conti, Davide Rossi, Luca Benini, Jorge Gomez
2025	—	`conf`	FlatAttention: Dataflow and Fabric Collectives Co-Optimization for Efficient Multi-Head Attention on Tile-Based Many-PE Accelerators. ISVLSI Chi Zhang, Luca Colagrande, Renzo Andri, Thomas Benz, Gamze Islamoglu, Alessandro Nadalini, Francesco Conti, Yawei Li, Luca Benini
2025	J	`jnl`	FlatAttention: Dataflow and Fabric Collectives Co-Optimization for Efficient Multi-Head Attention on Tile-Based Many-PE Accelerators. CoRR Chi Zhang, Luca Colagrande, Renzo Andri, Thomas Benz, Gamze Islamoglu, Alessandro Nadalini, Francesco Conti, Yawei Li, Luca Benini
2025	—	`conf`	FractalSync: Lightweight Scalable Global Synchronization of Massive Bulk Synchronous Parallel AI Accelerators. CF Victor Isachi, Alessandro Nadalini, Riccardo Fiorani Gallotta, Angelo Garofalo, Francesco Conti, Davide Rossi
2025	J	`jnl`	FractalSync: Lightweight Scalable Global Synchronization of Massive Bulk Synchronous Parallel AI Accelerators. CoRR Victor Isachi, Alessandro Nadalini, Riccardo Fiorani Gallotta, Angelo Garofalo, Francesco Conti, Davide Rossi
2025	J	`jnl`	Fused-Tiled Layers: Minimizing Data Movement on RISC-V SoCs with Software-Managed Caches. CoRR Victor J. B. Jung, Alessio Burrello, Francesco Conti, Luca Benini
2025	—	`conf`	HMR-NEureka: Hybrid Modular Redundancy DNN Acceleration in Heterogeneous RISC-V SoCs. ISVLSI Luigi Ghionda, Riccardo Tedeschi, Yvan Tortorella, Arpan Suravi Prasad, Davide Rossi, Luca Benini, Francesco Conti
2025	J	`jnl`	Hybrid Modular Redundancy: Exploring Modular Redundancy Approaches in RISC-V Multi-core Computing Clusters for Reliable Processing in Space. ACM Trans. Cyber Phys. Syst. Michael Rogenmoser, Yvan Tortorella, Davide Rossi, Francesco Conti, Luca Benini
2025	—	`conf`	Lightweight Software Kernels and Hardware Extensions for Efficient Sparse Deep Neural Networks on Microcontrollers. MLSys Francesco Daghero, Daniele Jahier Pagliari, Francesco Conti, Luca Benini, Massimo Poncino, Alessio Burrello
2025	J	`jnl`	Lightweight Software Kernels and Hardware Extensions for Efficient Sparse Deep Neural Networks on Microcontrollers. CoRR Francesco Daghero, Daniele Jahier Pagliari, Francesco Conti, Luca Benini, Massimo Poncino, Alessio Burrello
2025	—	`conf`	MXDOTP: A RISC-V ISA Extension for Enabling Microscaling (MX) Floating-Point Dot Products. ASAP Gamze Islamoglu, Luca Bertaccini, Arpan Suravi Prasad, Francesco Conti, Angelo Garofalo, Luca Benini
2025	J	`jnl`	MXDOTP: A RISC-V ISA Extension for Enabling Microscaling (MX) Floating-Point Dot Products. CoRR Gamze Islamoglu, Luca Bertaccini, Arpan Suravi Prasad, Francesco Conti, Angelo Garofalo, Luca Benini
2025	J	`jnl`	Maestro: A 302 GFLOPS/W and 19.8GFLOPS RISC-V Vector-Tensor Architecture for Wearable Ultrasound Edge Computing. CoRR Mattia Sinigaglia, Amirhossein Kiamarzi, Marco Bertuletti, Luigi Ghionda, Mattia Orlandi, Riccardo Tedeschi, Aurora Di Giampietro, Yvan Tortorella, Luca Bertaccini, Simone Benatti, Giuseppe Tagliavini, Luca Benini, Francesco Conti, Davide Rossi
2025	J	`jnl`	Maestro: A 302 GFLOPS/W and 19.8GFLOPS RISC-V Vector-Tensor Architecture for Wearable Ultrasound Edge Computing. IEEE Trans. Circuits Syst. I Regul. Pap. Mattia Sinigaglia, Amirhossein Kiamarzi, Marco Bertuletti, Luigi Ghionda, Mattia Orlandi, Riccardo Tedeschi, Aurora Di Giampietro, Yvan Tortorella, Luca Bertaccini, Simone Benatti, Giuseppe Tagliavini, Luca Benini, Francesco Conti, Davide Rossi
2025	A	`conf`	Multi-Mode Borderguard Controllers for Efficient On-Chip Communication in Heterogeneous Digital/Analog Neural Processing Units. DATE Hong Pang, Carmine Cappetta, Riccardo Massa, Athanasios Vasilopoulos, Elena Ferro, Gamze Islamoglu, Angelo Garofalo, Francesco Conti, Luca Benini, Irem Boybat, Thomas Boesch
2025	A	`conf`	Multi-Partner Project: Architectures and Design Methodologies to Accelerate AI Workloads. The ICSC Flagship 2 Project. DATE Cristina Silvano, Fabrizio Ferrandi, Serena Curzel, Daniele Ielmini, Stefania Perri, Fanny Spagnolo, Pasquale Corsonello, Sebastiano Fabio Schifano, Cristian Zambelli, Angelo Garofalo, Francesco Conti, Luca Benini
2025	J	`jnl`	Multi-modal On-Device Learning for Monocular Depth Estimation on Ultra-low-power MCUs. CoRR Davide Nadalini, Manuele Rusci, Elia Cereda, Luca Benini, Francesco Conti, Daniele Palossi
2025	J	`jnl`	Optimizing the Deployment of Tiny Transformers on Low-Power MCUs. IEEE Trans. Computers Victor Jean-Baptiste Jung, Alessio Burrello, Moritz Scherer, Francesco Conti, Luca Benini
2025	C	`conf`	PACE-Lite: Compact and Efficient Piecewise Polynomial Approximation for Transformer Nonlinearity Acceleration. ICCD Arpan Suravi Prasad, Gamze Islamoglu, Luca Bertaccini, Davide Rossi, Francesco Conti, Luca Benini
2025	—	`conf`	PACE: An Optimal Piecewise Polynomial Approximation Unit for Flexible and Efficient Transformer Non-linearity Acceleration. ISVLSI Arpan Suravi Prasad, Gamze Islamoglu, Luca Bertaccini, Davide Rossi, Francesco Conti, Luca Benini
2025	A	`conf`	SoftEx: A Low Power and Flexible Softmax Accelerator with Fast Approximate Exponentiation. DATE Andrea Belano, Yvan Tortorella, Angelo Garofalo, Luca Benini, Davide Rossi, Francesco Conti
2025	J	`jnl`	Toward Attention-Based TinyML: A Heterogeneous Accelerated Architecture and Automated Deployment Flow. IEEE Des. Test Philip Wiese, Gamze Islamoglu, Moritz Scherer, Luka Macan, Victor Jean-Baptiste Jung, Alessio Burrello, Francesco Conti, Luca Benini
2025	C	`conf`	VEXP: A Low-Cost RISC-V ISA Extension for Accelerated Softmax Computation in Transformers. ARITH Run Wang, Gamze Islamoglu, Andrea Belano, Viviane Potocnik, Francesco Conti, Angelo Garofalo, Luca Benini
2025	J	`jnl`	VEXP: A Low-Cost RISC-V ISA Extension for Accelerated Softmax Computation in Transformers. CoRR Run Wang, Gamze Islamoglu, Andrea Belano, Viviane Potocnik, Francesco Conti, Angelo Garofalo, Luca Benini
2024	J	`jnl`	A Flexible Template for Edge Generative AI with High-Accuracy Accelerated Softmax & GELU. CoRR Andrea Belano, Yvan Tortorella, Angelo Garofalo, Luca Benini, Davide Rossi, Francesco Conti
2024	J	`jnl`	A Sim-to-Real Deep Learning-Based Framework for Autonomous Nano-Drone Racing. IEEE Robotics Autom. Lett. Lorenzo Lamberti, Elia Cereda, Gabriele Abbate, Lorenzo Bellone, Victor Javier Kartsch Morinigo, Michal Barcis, Agata Barcis, Alessandro Giusti, Francesco Conti, Daniele Palossi
2024	J	`jnl`	An Extreme-Edge TCN-Based Low-Latency Collision-Avoidance Safety System for Industrial Machinery. IEEE Access Marcello Zanghieri, Fabrizio Indirli, Antonio Latella, Giacomo Michele Puglia, Felice Tecce, Francesco Papariello, Giulio Urlini, Luca Benini, Francesco Conti
2024	J	`jnl`	Circuits and Systems for Embodied AI: Exploring uJ Multi-Modal Perception for Nano-UAVs on the Kraken Shield. CoRR Viviane Potocnik, Alfio Di Mauro, Lorenzo Lamberti, Victor Javier Kartsch, Moritz Scherer, Francesco Conti, Luca Benini
2024	—	`conf`	Combining Local and Global Perception for Autonomous Navigation on Nano-UAVs. ERF (1) Lorenzo Lamberti, Georg Rutishauser, Francesco Conti, Luca Benini
2024	J	`jnl`	Combining Local and Global Perception for Autonomous Navigation on Nano-UAVs. CoRR Lorenzo Lamberti, Georg Rutishauser, Francesco Conti, Luca Benini
2024	—	`conf`	Compressed Latent Replays for Lightweight Continual Learning on Spiking Neural Networks. ISVLSI Alberto Dequino, Alessio Carpegna, Davide Nadalini, Alessandro Savino, Luca Benini, Stefano Di Carlo, Francesco Conti
2024	J	`jnl`	Compressed Latent Replays for Lightweight Continual Learning on Spiking Neural Networks. CoRR Alberto Dequino, Alessio Carpegna, Davide Nadalini, Alessandro Savino, Luca Benini, Stefano Di Carlo, Francesco Conti
2024	J	`jnl`	Corrections to "a Sim-to-Real Deep Learning-Based Framework for Autonomous Nano-Drone Racing". IEEE Robotics Autom. Lett. Lorenzo Lamberti, Elia Cereda, Gabriele Abbate, Lorenzo Bellone, Victor Javier Kartsch Morinigo, Michal Barcis, Agata Barcis, Alessandro Giusti, Francesco Conti, Daniele Palossi
2024	J	`jnl`	Deeploy: Enabling Energy-Efficient Deployment of Small Language Models On Heterogeneous Microcontrollers. CoRR Moritz Scherer, Luka Macan, Victor J. B. Jung, Philip Wiese, Luca Bompani, Alessio Burrello, Francesco Conti, Luca Benini
2024	J	`jnl`	Deeploy: Enabling Energy-Efficient Deployment of Small Language Models on Heterogeneous Microcontrollers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Moritz Scherer, Luka Macan, Victor J. B. Jung, Philip Wiese, Luca Bompani, Alessio Burrello, Francesco Conti, Luca Benini
2024	J	`jnl`	Distilling Tiny and Ultra-fast Deep Neural Networks for Autonomous Navigation on Nano-UAVs. CoRR Lorenzo Lamberti, Lorenzo Bellone, Luka Macan, Enrico Natalizio, Francesco Conti, Daniele Palossi, Luca Benini
2024	J	`jnl`	Distilling Tiny and Ultrafast Deep Neural Networks for Autonomous Navigation on Nano-UAVs. IEEE Internet Things J. Lorenzo Lamberti, Lorenzo Bellone, Luka Macan, Enrico Natalizio, Francesco Conti, Daniele Palossi, Luca Benini
2024	J	`jnl`	Distributed Inference with Minimal Off-Chip Traffic for Transformers on Low-Power MCUs. CoRR Severin Bochem, Victor J. B. Jung, Arpan Suravi Prasad, Francesco Conti, Luca Benini
2024	J	`jnl`	HTVM: Efficient Neural Network Deployment On Heterogeneous TinyML Platforms. CoRR Josse Van Delm, Maarten Vandersteegen, Alessio Burrello, Giuseppe Maria Sarda, Francesco Conti, Daniele Jahier Pagliari, Luca Benini, Marian Verhelst
2024	J	`jnl`	Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC With 2-8 b DNN Acceleration and 30%-Boost Adaptive Body Biasing. IEEE J. Solid State Circuits Francesco Conti, Gianna Paulin, Angelo Garofalo, Davide Rossi, Alfio Di Mauro, Georg Rutishauser, Gianmarco Ottavi, Manuel Eggimann, Hayate Okuhara, Luca Benini
2024	—	`conf`	Multi-resolution Rescored ByteTrack for Video Object Detection on Ultra-low-power Embedded Systems. CVPR Workshops Luca Bompani, Manuele Rusci, Daniele Palossi, Francesco Conti, Luca Benini
2024	J	`jnl`	Multi-resolution Rescored ByteTrack for Video Object Detection on Ultra-low-power Embedded Systems. CoRR Luca Bompani, Manuele Rusci, Daniele Palossi, Francesco Conti, Luca Benini
2024	J	`jnl`	Open-Source Heterogeneous SoCs for AI: The PULP Platform Experience. CoRR Francesco Conti, Angelo Garofalo, Davide Rossi, Giuseppe Tagliavini, Luca Benini
2024	J	`jnl`	Optimizing the Deployment of Tiny Transformers on Low-Power MCUs. CoRR Victor J. B. Jung, Alessio Burrello, Moritz Scherer, Francesco Conti, Luca Benini
2024	J	`jnl`	Siracusa: A 16 nm Heterogenous RISC-V SoC for Extended Reality With At-MRAM Neural Engine. IEEE J. Solid State Circuits Arpan Suravi Prasad, Moritz Scherer, Francesco Conti, Davide Rossi, Alfio Di Mauro, Manuel Eggimann, Jorge Tomás Gómez, Ziyun Li, Syed Shakib Sarwar, Zhao Wang, Barbara De Salvo, Luca Benini
2024	—	`conf`	Structured Sparse Back-propagation for Lightweight On-Device Continual Learning on Microcontroller Units. CVPR Workshops Francesco Paissan, Davide Nadalini, Manuele Rusci, Alberto Ancilotto, Francesco Conti, Luca Benini, Elisabetta Farella
2024	J	`jnl`	Toward Attention-based TinyML: A Heterogeneous Accelerated Architecture and Automated Deployment Flow. CoRR Philip Wiese, Gamze Islamoglu, Moritz Scherer, Luka Macan, Victor J. B. Jung, Alessio Burrello, Francesco Conti, Luca Benini
2023	—	`conf`	A 12.4TOPS/W @ 136GOPS AI-IoT System-on-Chip with 16 RISC-V, 2-to-8b Precision-Scalable DNN Acceleration and 30%-Boost Adaptive Body Biasing. ISSCC Francesco Conti, Davide Rossi, Gianna Paulin, Angelo Garofalo, Alfio Di Mauro, Georg Rutishauser, Gianmarco Ottavi, Manuel Eggimann, Hayate Okuhara, Vincent Huard, Olivier Montfort, Lionel Jure, Nils Exibard, Pascal Gouedo, Mathieu Louvat, Emmanuel Botte, Luca Benini
2023	—	`conf`	A 3 TOPS/W RISC-V Parallel Cluster for Inference of Fine-Grain Mixed-Precision Quantized Neural Networks. ISVLSI Alessandro Nadalini, Georg Rutishauser, Alessio Burrello, Nazareno Bruschi, Angelo Garofalo, Luca Benini, Francesco Conti, Davide Rossi
2023	J	`jnl`	A 3 TOPS/W RISC-V Parallel Cluster for Inference of Fine-Grain Mixed-Precision Quantized Neural Networks. CoRR Alessandro Nadalini, Georg Rutishauser, Alessio Burrello, Nazareno Bruschi, Angelo Garofalo, Luca Benini, Francesco Conti, Davide Rossi
2023	J	`jnl`	A Sim-to-Real Deep Learning-based Framework for Autonomous Nano-drone Racing. CoRR Lorenzo Lamberti, Elia Cereda, Gabriele Abbate, Lorenzo Bellone, Victor Javier Kartsch Morinigo, Michal Barcis, Agata Barcis, Alessandro Giusti, Francesco Conti, Daniele Palossi
2023	J	`jnl`	A Survey on Deep Learning Hardware Accelerators for Heterogeneous HPC Platforms. CoRR Cristina Silvano, Daniele Ielmini, Fabrizio Ferrandi, Leandro Fiorin, Serena Curzel, Luca Benini, Francesco Conti, Angelo Garofalo, Cristian Zambelli, Enrico Calore, Sebastiano Fabio Schifano, Maurizio Palesi, Giuseppe Ascia, Davide Patti, Stefania Perri, Nicola Petra, Davide De Caro, Luciano Lavagno, Teodoro Urso, Valeria Cardellini, Gian Carlo Cardarilli, Robert Birke
2023	J	`jnl`	A Survey on Design Methodologies for Accelerating Deep Learning on Heterogeneous Architectures. CoRR Fabrizio Ferrandi, Serena Curzel, Leandro Fiorin, Daniele Ielmini, Cristina Silvano, Francesco Conti, Alessio Burrello, Francesco Barchi, Luca Benini, Luciano Lavagno, Teodoro Urso, Enrico Calore, Sebastiano Fabio Schifano, Cristian Zambelli, Maurizio Palesi, Giuseppe Ascia, Enrico Russo, Nicola Petra, Davide De Caro, Gennaro Di Meo, Valeria Cardellini, Salvatore Filippone, Francesco Lo Presti, Francesco Silvestri, Paolo Palazzari, Stefania Perri
2023	J	`jnl`	DARKSIDE: A Heterogeneous RISC-V Compute Cluster for Extreme-Edge On-Chip DNN Inference and Training. CoRR Angelo Garofalo, Yvan Tortorella, Matteo Perotti, Luca Valente, Alessandro Nadalini, Luca Benini, Davide Rossi, Francesco Conti
2023	J	`jnl`	Dustin: A 16-Cores Parallel Ultra-Low-Power Cluster With 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode. IEEE Trans. Circuits Syst. I Regul. Pap. Gianmarco Ottavi, Angelo Garofalo, Giuseppe Tagliavini, Francesco Conti, Alfio Di Mauro, Luca Benini, Davide Rossi
2023	C	`conf`	ECHOES: a 200 GOPS/W Frequency Domain SoC with FFT Processor and I ISCAS Mattia Sinigaglia, Luca Bertaccini, Luca Valente, Angelo Garofalo, Simone Benatti, Luca Benini, Francesco Conti, Davide Rossi
2023	J	`jnl`	Echoes: a 200 GOPS/W Frequency Domain SoC with FFT Processor and I2S DSP for Flexible Data Acquisition from Microphone Arrays. CoRR Mattia Sinigaglia, Luca Bertaccini, Luca Valente, Angelo Garofalo, Simone Benatti, Luca Benini, Francesco Conti, Davide Rossi
2023	A	`conf`	End-to-End DNN Inference on a Massively Parallel Analog In Memory Computing Architecture. DATE Nazareno Bruschi, Giuseppe Tagliavini, Angelo Garofalo, Francesco Conti, Irem Boybat, Luca Benini, Davide Rossi
2023	—	`conf`	Free Bits: Latency Optimization of Mixed-Precision Quantized Neural Networks on the Edge. AICAS Georg Rutishauser, Francesco Conti, Luca Benini
2023	J	`jnl`	Free Bits: Latency Optimization of Mixed-Precision Quantized Neural Networks on the Edge. CoRR Georg Rutishauser, Francesco Conti, Luca Benini
2023	J	`jnl`	Graphene-Based Wireless Agile Interconnects for Massive Heterogeneous Multi-Chip Processors. IEEE Wirel. Commun. Sergi Abadal, Robert Guirado, Hamidreza Taghvaee, Akshay Jain, Elana Pereira de Santana, Peter Haring Bolívar, Mohamed Saeed, Renato Negra, Zhenxing Wang, Kun-Ta Wang, Max Christian Lemme, Joshua Alexander Harrison Klein, Marina Zapater, Alexandre Levisse, David Atienza, Davide Rossi, Francesco Conti, Martino Dazzi, Geethan Karunaratne, Irem Boybat, Abu Sebastian
2023	A*	`conf`	HTVM: Efficient Neural Network Deployment On Heterogeneous TinyML Platforms. DAC Josse Van Delm, Maarten Vandersteegen, Alessio Burrello, Giuseppe Maria Sarda, Francesco Conti, Daniele Jahier Pagliari, Luca Benini, Marian Verhelst
2023	J	`jnl`	Hybrid Modular Redundancy: Exploring Modular Redundancy Approaches in RISC-V Multi-Core Computing Clusters for Reliable Processing in Space. CoRR Michael Rogenmoser, Yvan Tortorella, Davide Rossi, Francesco Conti, Luca Benini
2023	J	`jnl`	Lightweight Neural Architecture Search for Temporal Convolutional Networks at the Edge. CoRR Matteo Risso, Alessio Burrello, Francesco Conti, Lorenzo Lamberti, Yukai Chen, Luca Benini, Enrico Macii, Massimo Poncino, Daniele Jahier Pagliari
2023	J	`jnl`	Lightweight Neural Architecture Search for Temporal Convolutional Networks at the Edge. IEEE Trans. Computers Matteo Risso, Alessio Burrello, Francesco Conti, Lorenzo Lamberti, Yukai Chen, Luca Benini, Enrico Macii, Massimo Poncino, Daniele Jahier Pagliari
2023	J	`jnl`	Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC with 2-to-8b DNN Acceleration and 30%-Boost Adaptive Body Biasing. CoRR Francesco Conti, Gianna Paulin, Davide Rossi, Alfio Di Mauro, Georg Rutishauser, Gianmarco Ottavi, Manuel Eggimann, Hayate Okuhara, Luca Benini
2023	B	`conf`	PULP Fiction No More - Dependable PULP Systems for Space. ETS Markus Ulbricht, Yvan Tortorella, Michael Rogenmoser, Li Lu, Junchao Chen, Francesco Conti, Milos Krstic, Luca Benini
2023	—	`conf`	RISC-V Processor Technologies for Aerospace Applications in the ISOLDE Project. SAMOS William Fornaciari, Federico Reghenzani, Giovanni Agosta, Davide Zoni, Andrea Galimberti, Francesco Conti, Yvan Tortorella, Emanuele Parisi, Francesco Barchi, Andrea Bartolini, Andrea Acquaviva, Daniele Gregori, Salvatore Cognetta, Carlo Ciancarelli, Antonio Leboffe, Paolo Serri, Alessio Burrello, Daniele Jahier Pagliari, Gianvito Urgese, Maurizio Martina, Guido Masera, Rosario Di Carlo, Antonio Sciarappa
2023	J	`jnl`	RedMule: A Mixed-Precision Matrix-Matrix Operation Engine for Flexible and Energy-Efficient On-Chip Linear Algebra and TinyML Training Acceleration. CoRR Yvan Tortorella, Luca Bertaccini, Luca Benini, Davide Rossi, Francesco Conti
2023	J	`jnl`	RedMule: A mixed-precision matrix-matrix operation engine for flexible and energy-efficient on-chip linear algebra and TinyML training acceleration. Future Gener. Comput. Syst. Yvan Tortorella, Luca Bertaccini, Luca Benini, Davide Rossi, Francesco Conti
2023	J	`jnl`	Reduced Precision Floating-Point Optimization for Deep Neural Network On-Device Learning on MicroControllers. CoRR Davide Nadalini, Manuele Rusci, Luca Benini, Francesco Conti
2023	J	`jnl`	Reduced precision floating-point optimization for Deep Neural Network On-Device Learning on microcontrollers. Future Gener. Comput. Syst. Davide Nadalini, Manuele Rusci, Luca Benini, Francesco Conti
2023	J	`jnl`	Siracusa: A 16 nm Heterogenous RISC-V SoC for Extended Reality with At-MRAM Neural Engine. CoRR Arpan Suravi Prasad, Moritz Scherer, Francesco Conti, Davide Rossi, Alfio Di Mauro, Manuel Eggimann, Jorge Tomás Gómez, Ziyun Li, Syed Shakib Sarwar, Zhao Wang, Barbara De Salvo, Luca Benini
2023	—	`conf`	Siracusa: A Low-Power On-Sensor RISC-V SoC for Extended Reality Visual Processing in 16nm CMOS. ESSCIRC Moritz Scherer, Manuel Eggimann, Alfio Di Mauro, Arpan Suravi Prasad, Francesco Conti, Davide Rossi, Jorge Tomás Gómez, Ziyun Li, Syed Shakib Sarwar, Zhao Wang, Barbara De Salvo, Luca Benini
2023	A*	`conf`	Specialization meets Flexibility: a Heterogeneous Architecture for High-Efficiency, High-flexibility AR/VR Processing. DAC Arpan Suravi Prasad, Luca Benini, Francesco Conti
2023	Misc	`conf`	WIP: Automatic DNN Deployment on Heterogeneous Platforms: the GAP9 Case Study. CASES Luka Macan, Alessio Burrello, Luca Benini, Francesco Conti
2022	J	`jnl`	A Heterogeneous In-Memory Computing Cluster For Flexible End-to-End Inference of Real-World Deep Neural Networks. CoRR Angelo Garofalo, Gianmarco Ottavi, Francesco Conti, Geethan Karunaratne, Irem Boybat, Luca Benini, Davide Rossi
2022	J	`jnl`	A Heterogeneous In-Memory Computing Cluster for Flexible End-to-End Inference of Real-World Deep Neural Networks. IEEE J. Emerg. Sel. Topics Circuits Syst. Angelo Garofalo, Gianmarco Ottavi, Francesco Conti, Geethan Karunaratne, Irem Boybat, Luca Benini, Davide Rossi
2022	—	`conf`	Darkside: 2.6GFLOPS, 8.7mW Heterogeneous RISC-V Cluster for Extreme-Edge On-Chip DNN Inference and Training. ESSCIRC Angelo Garofalo, Matteo Perotti, Luca Valente, Yvan Tortorella, Alessandro Nadalini, Luca Benini, Davide Rossi, Francesco Conti
2022	J	`jnl`	Dustin: A 16-Cores Parallel Ultra-Low-Power Cluster with 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode. CoRR Gianmarco Ottavi, Angelo Garofalo, Giuseppe Tagliavini, Francesco Conti, Alfio Di Mauro, Luca Benini, Davide Rossi
2022	J	`jnl`	End-to-End DNN Inference on a Massively Parallel Analog In Memory Computing Architecture. CoRR Nazareno Bruschi, Giuseppe Tagliavini, Angelo Garofalo, Francesco Conti, Irem Boybat, Luca Benini, Davide Rossi
2022	J	`jnl`	Fully Onboard AI-Powered Human-Drone Pose Estimation on Ultralow-Power Autonomous Flying Nano-UAVs. IEEE Internet Things J. Daniele Palossi, Nicky Zimmerman, Alessio Burrello, Francesco Conti, Hanna Müller, Luca Maria Gambardella, Luca Benini, Alessandro Giusti, Jérôme Guzzi
2022	J	`jnl`	GVSoC: A Highly Configurable, Fast and Accurate Full-Platform Simulator for RISC-V based IoT Processors. CoRR Nazareno Bruschi, Germain Haugou, Giuseppe Tagliavini, Francesco Conti, Luca Benini, Davide Rossi
2022	—	`conf`	Motor-Unit Ordering of Blindly-Separated Surface-EMG Signals for Gesture Recognition. SYSINT Mattia Orlandi, Marcello Zanghieri, Pasquale Davide Schiavone, Elisa Donati, Francesco Conti, Simone Benatti
2022	—	`conf`	PULP-TrainLib: Enabling On-Device Training for RISC-V Multi-core MCUs Through Performance-Driven Autotuning. SAMOS Davide Nadalini, Manuele Rusci, Giuseppe Tagliavini, Leonardo Ravaglia, Luca Benini, Francesco Conti
2022	J	`jnl`	Pruning In Time (PIT): A Lightweight Network Architecture Optimizer for Temporal Convolutional Networks. CoRR Matteo Risso, Alessio Burrello, Daniele Jahier Pagliari, Francesco Conti, Lorenzo Lamberti, Enrico Macii, Luca Benini, Massimo Poncino
2022	A	`conf`	RedMulE: A Compact FP16 Matrix-Multiplication Accelerator for Adaptive Deep Learning on RISC-V-Based Ultra-Low-Power SoCs. DATE Yvan Tortorella, Luca Bertaccini, Davide Rossi, Luca Benini, Francesco Conti
2022	J	`jnl`	RedMulE: A Compact FP16 Matrix-Multiplication Accelerator for Adaptive Deep Learning on RISC-V-Based Ultra-Low-Power SoCs. CoRR Yvan Tortorella, Luca Bertaccini, Davide Rossi, Luca Benini, Francesco Conti
2022	A	`conf`	SNE: an Energy-Proportional Digital Accelerator for Sparse Event-Based Convolutions. DATE Alfio Di Mauro, Arpan Suravi Prasad, Zhikai Huang, Matteo Spallanzani, Francesco Conti, Luca Benini
2022	J	`jnl`	SNE: an Energy-Proportional Digital Accelerator for Sparse Event-Based Convolutions. CoRR Alfio Di Mauro, Arpan Suravi Prasad, Zhikai Huang, Matteo Spallanzani, Francesco Conti, Luca Benini
2022	—	`conf`	Scale up your In-Memory Accelerator: Leveraging Wireless-on-Chip Communication for AIMC-based CNN Inference. AICAS Nazareno Bruschi, Giuseppe Tagliavini, Francesco Conti, Sergi Abadal, Albert Cabellos-Aparicio, Eduard Alarcón, Geethan Karunaratne, Irem Boybat, Luca Benini, Davide Rossi
2022	J	`jnl`	Scale up your In-Memory Accelerator: Leveraging Wireless-on-Chip Communication for AIMC-based CNN Inference. CoRR Nazareno Bruschi, Giuseppe Tagliavini, Francesco Conti, Sergi Abadal, Albert Cabellos-Aparicio, Eduard Alarcón, Geethan Karunaratne, Irem Boybat, Luca Benini, Davide Rossi
2022	J	`jnl`	TCN Mapping Optimization for Ultra-Low Power Time-Series Edge Inference. CoRR Alessio Burrello, Alberto Dequino, Daniele Jahier Pagliari, Francesco Conti, Marcello Zanghieri, Enrico Macii, Luca Benini, Massimo Poncino
2022	J	`jnl`	Vau Da Muntanialas: Energy-Efficient Multi-Die Scalable Acceleration of RNN Inference. IEEE Trans. Circuits Syst. I Regul. Pap. Gianna Paulin, Francesco Conti, Lukas Cavigelli, Luca Benini
2022	J	`jnl`	Vau da muntanialas: Energy-efficient multi-die scalable acceleration of RNN inference. CoRR Gianna Paulin, Francesco Conti, Lukas Cavigelli, Luca Benini
2022	J	`jnl`	Vega: A Ten-Core SoC for IoT Endnodes With DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode. IEEE J. Solid State Circuits Davide Rossi, Francesco Conti, Manuel Eggimann, Alfio Di Mauro, Giuseppe Tagliavini, Stefan Mach, Marco Guermandi, Antonio Pullini, Igor Loi, Jie Chen, Eric Flamand, Luca Benini
2022	—	`conf`	ViT-LR: Pushing the Envelope for Transformer-Based on-Device Embedded Continual Learning. IGSC Alberto Dequino, Francesco Conti, Luca Benini
2022	—	`conf`	sEMG Neural Spikes Reconstruction for Gesture Recognition on a Low-Power Multicore Processor. BioCAS Mattia Orlandi, Marcello Zanghieri, Victor Javier Kartsch Morinigo, Francesco Conti, Pasquale Davide Schiavone, Luca Benini, Simone Benatti
2021	—	`conf`	4.4 A 1.3TOPS/W @ 32GOPS Fully Integrated 10-Core SoC for IoT End-Nodes with 1.7μW Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode. ISSCC Davide Rossi, Francesco Conti, Manuel Eggimann, Stefan Mach, Alfio Di Mauro, Marco Guermandi, Giuseppe Tagliavini, Antonio Pullini, Igor Loi, Jie Chen, Eric Flamand, Luca Benini
2021	—	`conf`	A 1.15 TOPS/W, 16-Cores Parallel Ultra-Low Power Cluster with 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode. ESSCIRC Angelo Garofalo, Gianmarco Ottavi, Alfio Di Mauro, Francesco Conti, Giuseppe Tagliavini, Luca Benini, Davide Rossi
2021	—	`conf`	A Microcontroller is All You Need: Enabling Transformer Execution on Low-Power IoT Endnodes. COINS Alessio Burrello, Moritz Scherer, Marcello Zanghieri, Francesco Conti, Luca Benini
2021	—	`conf`	A Multi-Precision Bit-Serial Hardware Accelerator IP for Deep Learning Enabled Internet-of-Things. MWSCAS Maurizio Capra, Francesco Conti, Maurizio Martina
2021	C	`conf`	A RISC-V-based FPGA Overlay to Simplify Embedded Accelerator Deployment. DSD Gianluca Bellocchi, Alessandro Capotondi, Francesco Conti, Andrea Marongiu
2021	J	`jnl`	A TinyML Platform for On-Device Continual Learning With Quantized Latent Replays. IEEE J. Emerg. Sel. Topics Circuits Syst. Leonardo Ravaglia, Manuele Rusci, Davide Nadalini, Alessandro Capotondi, Francesco Conti, Luca Benini
2021	J	`jnl`	A TinyML Platform for On-Device Continual Learning with Quantized Latent Replays. CoRR Leonardo Ravaglia, Manuele Rusci, Davide Nadalini, Alessandro Capotondi, Francesco Conti, Luca Benini
2021	—	`conf`	Architecting more than Moore: wireless plasticity for massive heterogeneous computer architectures (WiPLASH). CF Joshua Alexander Harrison Klein, Alexandre Levisse, Giovanni Ansaloni, David Atienza, Marina Zapater, Martino Dazzi, Geethan Karunaratne, Irem Boybat, Abu Sebastian, Davide Rossi, Francesco Conti, Elana Pereira de Santana, Peter Haring Bolívar, Mohamed Saeed, Renato Negra, Zhenxing Wang, Kun-Ta Wang, Max Christian Lemme, Akshay Jain, Robert Guirado, Hamidreza Taghvaee, Sergi Abadal
2021	J	`jnl`	DORY: Automatic End-to-End Deployment of Real-World DNNs on Low-Cost IoT MCUs. IEEE Trans. Computers Alessio Burrello, Angelo Garofalo, Nazareno Bruschi, Giuseppe Tagliavini, Davide Rossi, Francesco Conti
2021	—	`conf`	End-to-end 100-TOPS/W Inference With Analog In-Memory Computing: Are We There Yet? AICAS Gianmarco Ottavi, Geethan Karunaratne, Francesco Conti, Irem Boybat, Luca Benini, Davide Rossi
2021	J	`jnl`	End-to-end 100-TOPS/W Inference With Analog In-Memory Computing: Are We There Yet? CoRR Gianmarco Ottavi, Geethan Karunaratne, Francesco Conti, Irem Boybat, Luca Benini, Davide Rossi
2021	J	`jnl`	Fully Onboard AI-powered Human-Drone Pose Estimation on Ultra-low Power Autonomous Flying Nano-UAVs. CoRR Daniele Palossi, Nicky Zimmerman, Alessio Burrello, Francesco Conti, Hanna Müller, Luca Maria Gambardella, Luca Benini, Alessandro Giusti, Jérôme Guzzi
2021	A	`conf`	Fünfiiber-Drone: A Modular Open-Platform 18-grams Autonomous Nano-Drone. DATE Hanna Müller, Daniele Palossi, Stefan Mach, Francesco Conti, Luca Benini
2021	C	`conf`	GVSoC: A Highly Configurable, Fast and Accurate Full-Platform Simulator for RISC-V based IoT Processors. ICCD Nazareno Bruschi, Germain Haugou, Giuseppe Tagliavini, Francesco Conti, Luca Benini, Davide Rossi
2021	J	`jnl`	Improving Autonomous Nano-Drones Performance via Automated End-to-End Optimization and Deployment of DNNs. IEEE J. Emerg. Sel. Topics Circuits Syst. Vlad Niculescu, Lorenzo Lamberti, Francesco Conti, Luca Benini, Daniele Palossi
2021	A*	`conf`	Pruning In Time (PIT): A Lightweight Network Architecture Optimizer for Temporal Convolutional Networks. DAC Matteo Risso, Alessio Burrello, Daniele Jahier Pagliari, Francesco Conti, Lorenzo Lamberti, Enrico Macii, Luca Benini, Massimo Poncino
2021	J	`jnl`	RNN-Based Radio Resource Management on Multicore RISC-V Accelerator Architectures. IEEE Trans. Very Large Scale Integr. Syst. Gianna Paulin, Renzo Andri, Francesco Conti, Luca Benini
2021	A	`conf`	TCN Mapping Optimization for Ultra-Low Power Time-Series Edge Inference. ISLPED Alessio Burrello, Alberto Dequino, Daniele Jahier Pagliari, Francesco Conti, Marcello Zanghieri, Enrico Macii, Luca Benini, Massimo Poncino
2021	—	`conf`	To Buffer, or Not to Buffer? A Case Study on FFT Accelerators for Ultra-Low-Power Multicore Clusters. ASAP Luca Bertaccini, Luca Benini, Francesco Conti
2021	J	`jnl`	Vega: A 10-Core SoC for IoT End-Nodes with DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode. CoRR Davide Rossi, Francesco Conti, Manuel Eggimann, Alfio Di Mauro, Giuseppe Tagliavini, Stefan Mach, Marco Guermandi, Antonio Pullini, Igor Loi, Jie Chen, Eric Flamand, Luca Benini
2021	J	`jnl`	XpulpNN: Enabling Energy Efficient and Flexible Inference of Quantized Neural Networks on RISC-V Based IoT End Nodes. IEEE Trans. Emerg. Top. Comput. Angelo Garofalo, Giuseppe Tagliavini, Francesco Conti, Luca Benini, Davide Rossi
2021	C	`conf`	XpulpNN: Enabling Energy Efficient and Flexible Inference of Quantized Neural Networks on RISC-V based IoT End Nodes. ARITH Angelo Garofalo, Giuseppe Tagliavini, Francesco Conti, Luca Benini, Davide Rossi
2020	—	`conf`	A Mixed-Precision RISC-V Processor for Extreme-Edge DNN Inference. ISVLSI Gianmarco Ottavi, Angelo Garofalo, Giuseppe Tagliavini, Francesco Conti, Luca Benini, Davide Rossi
2020	J	`jnl`	A Mixed-Precision RISC-V Processor for Extreme-Edge DNN Inference. CoRR Gianmarco Ottavi, Angelo Garofalo, Giuseppe Tagliavini, Francesco Conti, Luca Benini, Davide Rossi
2020	J	`jnl`	Always-On 674uW @ 4GOP/s Error Resilient Binary Neural Networks with Aggressive SRAM Voltage Scaling on a 22nm IoT End-Node. CoRR Alfio Di Mauro, Francesco Conti, Pasquale Davide Schiavone, Davide Rossi, Luca Benini
2020	J	`jnl`	Always-On 674μ W@4GOP/s Error Resilient Binary Neural Networks With Aggressive SRAM Voltage Scaling on a 22-nm IoT End-Node. IEEE Trans. Circuits Syst. Alfio Di Mauro, Francesco Conti, Pasquale Davide Schiavone, Davide Rossi, Luca Benini
2020	J	`jnl`	DORY: Automatic End-to-End Deployment of Real-World DNNs on Low-Cost IoT MCUs. CoRR Alessio Burrello, Angelo Garofalo, Nazareno Bruschi, Giuseppe Tagliavini, Davide Rossi, Francesco Conti
2020	J	`jnl`	Enabling Mixed-Precision Quantized Neural Networks in Extreme-Edge Devices. CoRR Nazareno Bruschi, Angelo Garofalo, Francesco Conti, Giuseppe Tagliavini, Davide Rossi
2020	—	`conf`	Enabling mixed-precision quantized neural networks in extreme-edge devices. CF Nazareno Bruschi, Angelo Garofalo, Francesco Conti, Giuseppe Tagliavini, Davide Rossi
2020	J	`jnl`	Exploring NEURAghe: A Customizable Template for APSoC-Based CNN Inference at the Edge. IEEE Embed. Syst. Lett. Paolo Meloni, Daniela Loi, Gianfranco Deriu, Marco Carreras, Francesco Conti, Alessandro Capotondi, Davide Rossi
2020	J	`jnl`	Graphene-based Wireless Agile Interconnects for Massive Heterogeneous Multi-chip Processors. CoRR Sergi Abadal, Robert Guirado, Hamidreza Taghvaee, Akshay Jain, Elana Pereira de Santana, Peter Haring Bolívar, Mohamed Saeed Elsayed, Renato Negra, Zhenxing Wang, Kun-Ta Wang, Max Christian Lemme, Joshua Alexander Harrison Klein, Marina Zapater, Alexandre Levisse, David Atienza, Davide Rossi, Francesco Conti, Martino Dazzi, Geethan Karunaratne, Irem Boybat, Abu Sebastian
2020	J	`jnl`	Introduction to the Special Issue on the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS 2020). IEEE J. Emerg. Sel. Topics Circuits Syst. Teresa Serrano-Gotarredona, Maurizio Valle, Francesco Conti, Hai Li
2020	—	`conf`	Memory-Latency-Accuracy Trade-Offs for Continual Learning on a RISC-V Extreme-Edge Node. SiPS Leonardo Ravaglia, Manuele Rusci, Alessandro Capotondi, Francesco Conti, Lorenzo Pellegrini, Vincenzo Lomonaco, Davide Maltoni, Luca Benini
2020	J	`jnl`	Memory-Latency-Accuracy Trade-offs for Continual Learning on a RISC-V Extreme-Edge Node. CoRR Leonardo Ravaglia, Manuele Rusci, Alessandro Capotondi, Francesco Conti, Lorenzo Pellegrini, Vincenzo Lomonaco, Davide Maltoni, Luca Benini
2020	J	`jnl`	Robust Real-Time Embedded EMG Recognition Framework Using Temporal Convolutional Networks on a Multicore IoT Processor. IEEE Trans. Biomed. Circuits Syst. Marcello Zanghieri, Simone Benatti, Alessio Burrello, Victor Javier Kartsch, Francesco Conti, Luca Benini
2020	J	`jnl`	Technical Report: NEMO DNN Quantization for Deployment Model. CoRR Francesco Conti
2020	—	`conf`	Temporal Variability Analysis in sEMG Hand Grasp Recognition using Temporal Convolutional Networks. AICAS Marcello Zanghieri, Simone Benatti, Francesco Conti, Alessio Burrello, Luca Benini
2020	A	`conf`	XpulpNN: Accelerating Quantized Neural Networks on RISC-V Processors Through ISA Extensions. DATE Angelo Garofalo, Giuseppe Tagliavini, Francesco Conti, Davide Rossi, Luca Benini
2020	J	`jnl`	XpulpNN: Enabling Energy Efficient and Flexible Inference of Quantized Neural Network on RISC-V based IoT End Nodes. CoRR Angelo Garofalo, Giuseppe Tagliavini, Francesco Conti, Luca Benini, Davide Rossi
2019	J	`jnl`	A 64-mW DNN-Based Visual Navigation Engine for Autonomous Nano-Drones. IEEE Internet Things J. Daniele Palossi, Antonio Loquercio, Francesco Conti, Eric Flamand, Davide Scaramuzza, Luca Benini
2019	B	`conf`	An Open Source and Open Hardware Deep Learning-Powered Visual Navigation Engine for Autonomous Nano-UAVs. DCOSS Daniele Palossi, Francesco Conti, Luca Benini
2019	J	`jnl`	An Open Source and Open Hardware Deep Learning-powered Visual Navigation Engine for Autonomous Nano-UAVs. CoRR Daniele Palossi, Francesco Conti, Luca Benini
2019	Misc	`conf`	DORY: Lightweight memory hierarchy management for deep NN inference on IoT endnodes: work-in-progress. CODES+ISSS Alessio Burrello, Francesco Conti, Angelo Garofalo, Davide Rossi, Luca Benini
2019	J	`jnl`	Optimally Scheduling CNN Convolutions for Efficient Memory Access. CoRR Arthur Stoutchinin, Francesco Conti, Luca Benini
2019	—	`conf`	Optimization and deployment of CNNs at the edge: the ALOHA experience. CF Paolo Meloni, Daniela Loi, Paola Busia, Gianfranco Deriu, Andy D. Pimentel, Dolly Sapra, Todor P. Stefanov, Svetlana Minakova, Francesco Conti, Luca Benini, Maura Pintor, Battista Biggio, Bernhard Moser, Natalia Shepeleva, Nikos Fragoulis, Ilias Theodorakopoulos, Michael Masin, Francesca Palumbo
2019	—	`conf`	PULP-NN: A Computing Library for Quantized Neural Network inference at the edge on RISC-V Based Parallel Ultra Low Power Clusters. ICECS Angelo Garofalo, Manuele Rusci, Francesco Conti, Davide Rossi, Luca Benini
2019	J	`jnl`	PULP-NN: Accelerating Quantized Neural Networks on Parallel Ultra-Low-Power RISC-V Processors. CoRR Angelo Garofalo, Manuele Rusci, Francesco Conti, Davide Rossi, Luca Benini
2018	J	`jnl`	A Heterogeneous Multicore System on Chip for Energy Efficient Brain Inspired Computing. IEEE Trans. Circuits Syst. II Express Briefs Antonio Pullini, Francesco Conti, Davide Rossi, Igor Loi, Michael Gautschi, Luca Benini
2018	—	`conf`	ALOHA: an architectural-aware framework for deep learning at the edge. INTESA@ESWEEK Paolo Meloni, Daniela Loi, Gianfranco Deriu, Andy D. Pimentel, Dolly Sapra, Bernhard Moser, Natalia Shepeleva, Francesco Conti, Luca Benini, Oscar Ripolles, David Solans, Maura Pintor, Battista Biggio, Todor P. Stefanov, Svetlana Minakova, Nikolaos Fragoulis, Ilias Theodorakopoulos, Michael Masin, Francesca Palumbo
2018	—	`conf`	Architecture-aware design and implementation of CNN algorithms for embedded inference: the ALOHA project. ICM Paolo Meloni, Daniela Loi, Gianfranco Deriu, Andy D. Pimentel, Dolly Sapra, Maura Pintor, Battista Biggio, Oscar Ripolles, David Solans, Francesco Conti, Luca Benini, Todor P. Stefanov, Svetlana Minakova, Bernhard Moser, Natalia Shepeleva, Michael Masin, Francesca Palumbo, Nikos Fragoulis, Ilias Theodorakopoulos
2018	—	`conf`	Chipmunk: A systolically scalable 0.9 mm CICC Francesco Conti, Lukas Cavigelli, Gianna Paulin, Igor Susmelj, Luca Benini
2018	—	`conf`	GAP-8: A RISC-V SoC for AI at the Edge of the IoT. ASAP Eric Flamand, Davide Rossi, Francesco Conti, Igor Loi, Antonio Pullini, Florent Rotenberg, Luca Benini
2018	J	`jnl`	NEURAghe: Exploiting CPU-FPGA Synergies for Efficient and Flexible CNN Inference Acceleration on Zynq SoCs. ACM Trans. Reconfigurable Technol. Syst. Paolo Meloni, Alessandro Capotondi, Gianfranco Deriu, Michele Brian, Francesco Conti, Davide Rossi, Luigi Raffo, Luca Benini
2018	Misc	`conf`	Quantized NNs as the definitive solution for inference on low-power ARM MCUs?: work-in-progress. CODES+ISSS Manuele Rusci, Alessandro Capotondi, Francesco Conti, Luca Benini
2018	—	`conf`	Thermal image-based CNN's for ultra-low power people recognition. CF Andres Gomez, Francesco Conti, Luca Benini
2018	J	`jnl`	Ultra Low Power Deep-Learning-powered Autonomous Nano Drones. CoRR Daniele Palossi, Antonio Loquercio, Francesco Conti, Eric Flamand, Davide Scaramuzza, Luca Benini
2018	J	`jnl`	XNOR Neural Engine: A Hardware Accelerator IP for 21.6-fJ/op Binary Neural Network Inference. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Francesco Conti, Pasquale Davide Schiavone, Luca Benini
2018	J	`jnl`	XNOR Neural Engine: a Hardware Accelerator IP for 21.6 fJ/op Binary Neural Network Inference. CoRR Francesco Conti, Pasquale Davide Schiavone, Luca Benini
2017	J	`jnl`	A Self-Aware Architecture for PVT Compensation and Power Nap in Near Threshold Processors. IEEE Des. Test Davide Rossi, Igor Loi, Antonio Pullini, Thomas Christoph Müller, Andreas Burg, Francesco Conti, Luca Benini, Philippe Flatresse
2017	J	`jnl`	Accelerated Visual Context Classification on a Low-Power Smartwatch. IEEE Trans. Hum. Mach. Syst. Francesco Conti, Daniele Palossi, Renzo Andri, Michele Magno, Luca Benini
2017	J	`jnl`	An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics. IEEE Trans. Circuits Syst. I Regul. Pap. Francesco Conti, Robert Schilling, Pasquale Davide Schiavone, Antonio Pullini, Davide Rossi, Frank Kagan Gürkaynak, Michael Muehlberghuber, Michael Gautschi, Igor Loi, Germain Haugou, Stefan Mangard, Luca Benini
2017	A*	`conf`	An Ultra-Low Power Address-Event Sensor Interface for Energy-Proportional Time-to-Information Extraction. DAC Alfio Di Mauro, Francesco Conti, Luca Benini
2017	J	`jnl`	Chipmunk: A Systolically Scalable 0.9 mm CoRR Francesco Conti, Lukas Cavigelli, Gianna Paulin, Igor Susmelj, Luca Benini
2017	—	`conf`	Multi-core data analytics SoC with a flexible 1.76 Gbit/s AES-XTS cryptographic accelerator in 65 nm CMOS. CS2@HiPEAC Frank K. Gürkaynak, Robert Schilling, Michael Muehlberghuber, Francesco Conti, Stefan Mangard, Luca Benini
2017	J	`jnl`	NEURAghe: Exploiting CPU-FPGA Synergies for Efficient and Flexible CNN Inference Acceleration on Zynq SoCs. CoRR Paolo Meloni, Alessandro Capotondi, Gianfranco Deriu, Michele Brian, Francesco Conti, Davide Rossi, Luigi Raffo, Luca Benini
2017	—	`conf`	Slow and steady wins the race? A comparison of ultra-low-power RISC-V cores for Internet-of-Things applications. PATMOS Pasquale Davide Schiavone, Francesco Conti, Davide Rossi, Michael Gautschi, Antonio Pullini, Eric Flamand, Luca Benini
2016	C	`conf`	A heterogeneous multi-core system-on-chip for energy efficient brain inspired vision. ISCAS Antonio Pullini, Francesco Conti, Davide Rossi, Igor Loi, Michael Gautschi, Luca Benini
2016	—	`conf`	A high-efficiency runtime reconfigurable IP for CNN acceleration on a mid-range all-programmable SoC. ReConFig Paolo Meloni, Gianfranco Deriu, Francesco Conti, Igor Loi, Luigi Raffo, Luca Benini
2016	J	`jnl`	An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics. CoRR Francesco Conti, Robert Schilling, Pasquale Davide Schiavone, Antonio Pullini, Davide Rossi, Frank Kagan Gürkaynak, Michael Muehlberghuber, Michael Gautschi, Igor Loi, Germain Haugou, Stefan Mangard, Luca Benini
2016	—	`conf`	Curbing the roofline: a scalable and flexible architecture for CNNs on FPGA. Conf. Computing Frontiers Paolo Meloni, Gianfranco Deriu, Francesco Conti, Igor Loi, Luigi Raffo, Luca Benini
2016	A	`conf`	Enabling the heterogeneous accelerator model on ultra-low power microcontroller platforms. DATE Francesco Conti, Daniele Palossi, Andrea Marongiu, Davide Rossi, Luca Benini
2016	J	`jnl`	He-P2012: Performance and Energy Exploration of Architecturally Heterogeneous Many-Cores. J. Signal Process. Syst. Francesco Conti, Andrea Marongiu, Chuck Pilkington, Luca Benini
2016	—	`—`	Heterogeneous Architectures For Parallel Acceleration. Francesco Conti
2016	J	`jnl`	On-the-fly adaptivity for process networks over shared-memory platforms. Microprocess. Microsystems Giuseppe Tuveri, Paolo Meloni, Francesca Palumbo, Giovanni Pietro Seu, Igor Loi, Francesco Conti, Luigi Raffo
2016	J	`jnl`	PULP: A Ultra-Low Power Parallel Accelerator for Energy-Efficient and Flexible Embedded Vision. J. Signal Process. Syst. Francesco Conti, Davide Rossi, Antonio Pullini, Igor Loi, Luca Benini
2015	A	`conf`	A ultra-low-energy convolution engine for fast brain-inspired vision in multicore clusters. DATE Francesco Conti, Luca Benini
2015	—	`conf`	PULP: A parallel ultra low power platform for next generation IoT applications. Hot Chips Symposium Davide Rossi, Francesco Conti, Andrea Marongiu, Antonio Pullini, Igor Loi, Michael Gautschi, Giuseppe Tagliavini, Alessandro Capotondi, Philippe Flatresse, Luca Benini
2014	—	`conf`	A Stream Buffer Mechanism for Pervasive Splitting Transformations on Polyhedral Process Networks. MES Paolo Meloni, Giuseppe Tuveri, Luigi Raffo, Igor Loi, Francesco Conti
2014	—	`conf`	Brain-Inspired Classroom Occupancy Monitoring on a Low-Power Mobile Platform. CVPR Workshops Francesco Conti, Antonio Pullini, Luca Benini
2014	—	`conf`	Energy-efficient vision on the PULP platform for ultra-low power parallel computing. SiPS Francesco Conti, Davide Rossi, Antonio Pullini, Igor Loi, Luca Benini
2014	—	`conf`	He-P2012: Architectural heterogeneity exploration on a scalable many-core platform. ASAP Francesco Conti, Chuck Pilkington, Andrea Marongiu, Luca Benini
2014	—	`conf`	He-P2012: architectural heterogeneity exploration on a scalable many-core platform. ACM Great Lakes Symposium on VLSI Francesco Conti, Chuck Pilkington, Andrea Marongiu, Luca Benini
2014	—	`conf`	Online process transformation for polyhedral process networks in shared-memory MPSoCs. MECO Paolo Meloni, Giuseppe Tuveri, Luigi Raffo, Igor Loi, Francesco Conti
2014	A	`conf`	Tightly-coupled hardware support to dynamic parallelism acceleration in embedded shared memory clusters. DATE Paolo Burgio, Giuseppe Tagliavini, Francesco Conti, Andrea Marongiu, Luca Benini
2013	Misc	`conf`	Synthesis-friendly techniques for tightly-coupled integration of hardware accelerators into shared-memory multi-core clusters. CODES+ISSS Francesco Conti, Andrea Marongiu, Luca Benini