Francesco Centurelli

80 papers A 1C 6Journal 40Unranked 33

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	0.5 V Digitally-Tunable Filters for Biomedical Applications Exploiting Segmented Duty-Cycled Resistors. IEEE Access Alessandro Fava, Francesco Centurelli, Giuseppe Scotti
2025	C	`conf`	A Novel Ultra-Low-Power, Tunable, LPF and BPF Biquad Based on New Fully Differential Folded-Gain-Boosting. ISCAS Matteo Lombardo, Francesco Centurelli, Pietro Monsurrò, Alessandro Trifiletti
2025	J	`jnl`	Exploiting Body-Driven Feedbacks in Physical Unclonable Functions for Ultra Low Voltage, Ultra Low Power Applications: A 0.3 V Weak-PUF. IEEE Trans. Circuits Syst. I Regul. Pap. Riccardo Della Sala, Davide Bellizia, Francesco Centurelli, Giuseppe Scotti, Alessandro Trifiletti
2024	—	`conf`	A 150 MS/s, 10 bit SAR ADC Featuring a Modified Quasi-Monotonic Switching Scheme. PRIME Valerio Spinogatti, Cristian Bocciarelli, Lorenzo Eusebio, Francesco Centurelli, Giuseppe Scotti, Alessandro Trifiletti
2024	J	`jnl`	A Novel High Performance Standard-Cell Based ULV OTA Exploiting an Improved Basic Amplifier. IEEE Access Riccardo Della Sala, Francesco Centurelli, Giuseppe Scotti
2024	—	`conf`	A Novel Technique to Design Ultra-Low Voltage and Ultra-Low Power Inverter-Based OTAs. PRIME Riccardo Della Sala, Francesco Centurelli, Giuseppe Scotti
2024	—	`conf`	Enhancing Performance of Ultra-Low Voltage Body-Driven Comparators Through Clocked Supply Voltage. PRIME Riccardo Della Sala, Cristian Bocciarelli, Valerio Spinogatti, Francesco Centurelli, Alessandro Trifiletti
2024	J	`jnl`	On the Feasibility of Cascode and Regulated Cascode Amplifier Stages in ULV Circuits Exploiting MOS Transistors in Deep Subthreshold Operation. IEEE Access Riccardo Della Sala, Francesco Centurelli, Pietro Monsurrò, Giuseppe Scotti
2024	J	`jnl`	Rail to Rail ICMR and High Performance ULV Standard-Cell-Based Comparator for Biomedical and IoT Applications. IEEE Access Riccardo Della Sala, Francesco Centurelli, Giuseppe Scotti, Gaetano Palumbo
2023	J	`jnl`	A 0.3V Rail-to-Rail Three-Stage OTA With High DC Gain and Improved Robustness to PVT Variations. IEEE Access Riccardo Della Sala, Francesco Centurelli, Pietro Monsurrò, Giuseppe Scotti, Alessandro Trifiletti
2023	J	`jnl`	A 17 GHz inductorless low-pass filter based on a quasi-Sallen-Key approach. Int. J. Circuit Theory Appl. Cristian Bocciarelli, Francesco Centurelli, Pietro Monsurrò, Valerio Spinogatti, Alessandro Trifiletti
2023	—	`conf`	A 2.5 GHz, 0.6 V Body Driven Dynamic Comparator Exploiting Charge Pump Based Dynamic Biasing. PRIME Cristian Bocciarelli, Francesco Centurelli, Riccardo Della Sala, Valerio Spinogatti, Alessandro Trifiletti
2023	J	`jnl`	A Detailed Model of Cyclostationary Noise in Switched-Resistor Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. Alessandro Fava, Francesco Centurelli, Giuseppe Scotti
2023	J	`jnl`	A Novel Parallel Digitizer With a Pulseless Mixing-Filtering-Processing Architecture and Its Implementation in a SiGe HBT Technology at 40GS/s. IEEE Access Francesco Centurelli, Pietro Monsurrò, Pasquale Tommasino, Alessandro Trifiletti
2023	—	`conf`	A Novel Ultra-Low Voltage Fully Synthesizable Comparator exploiting NAND Gates. PRIME Riccardo Della Sala, Cristian Bocciarelli, Francesco Centurelli, Valerio Spinogatti, Alessandro Trifiletti
2023	J	`jnl`	A body-driven rail-to-rail 0.3 V operational transconductance amplifier exploiting current gain stages. Int. J. Circuit Theory Appl. Riccardo Della Sala, Francesco Centurelli, Pietro Monsurrò, Giuseppe Scotti, Alessandro Trifiletti
2023	J	`jnl`	An Improved Strong Arm Comparator With Integrated Static Preamplifier. IEEE Access Valerio Spinogatti, Riccardo Della Sala, Cristian Bocciarelli, Francesco Centurelli, Alessandro Trifiletti
2023	—	`conf`	CMOS Adaptive Biased Second Generation Voltage Conveyor. BATS Gianluca Barile, Vincenzo Stornelli, Leonardo Pantoli, Davide Colaiuda, Francesco Centurelli, Pasquale Tommasino, Alessandro Trifiletti, Giuseppe Ferri
2023	J	`jnl`	High-Accuracy Low-Cost Generalized Complex Pruned Volterra Models for Nonlinear Calibration. IEEE Trans. Circuits Syst. I Regul. Pap. Cristian Bocciarelli, Francesco Centurelli, Pietro Monsurrò, Giuseppe Scotti, Valerio Spinogatti, Pasquale Tommasino, Alessandro Trifiletti
2023	—	`conf`	Robust Body Biasing Techniques for Dynamic Comparators. PRIME Valerio Spinogatti, Cristian Bocciarelli, Francesco Centurelli, Riccardo Della Sala, Alessandro Trifiletti
2023	—	`conf`	Wide-Band Shared LNA for Large Scale Neural Recording Applications. SMACD Alessandro Fava, Francesco Centurelli, Andrea Vittimberga, Giuseppe Scotti
2022	J	`jnl`	A Biasing Approach to Design Ultra-Low-Power Standard-Cell-Based Analog Building Blocks for Nanometer SoCs. IEEE Access Francesco Centurelli, Gianluca Giustolisi, Salvatore Pennisi, Giuseppe Scotti
2022	J	`jnl`	A Novel Differential to Single-Ended Converter for Ultra-Low-Voltage Inverter-Based OTAs. IEEE Access Riccardo Della Sala, Francesco Centurelli, Giuseppe Scotti
2022	J	`jnl`	A SiGe HBT 6th-Order 10 GHz Inductor-Less Anti-Aliasing Low-Pass Filter for High-Speed ATI Digitizers. IEEE Trans. Circuits Syst. I Regul. Pap. Francesco Centurelli, Pietro Monsurrò, Giuseppe Scotti, Pasquale Tommasino, Alessandro Trifiletti
2022	J	`jnl`	Enabling ULV Fully Synthesizable Analog Circuits: The BA Cell, a Standard-Cell-Based Building Block for Analog Design. IEEE Trans. Circuits Syst. II Express Briefs Riccardo Della Sala, Francesco Centurelli, Giuseppe Scotti
2022	J	`jnl`	General Approach to the Calibration of Innovative MFP Multichannel Digitizers. IEEE Trans. Instrum. Meas. Francesco Centurelli, Pietro Monsurrò, Alessandro Trifiletti, Mauro D'Arco, Leopoldo Angrisani
2022	—	`conf`	High-efficiency 0.3V OTA in CMOS 130nm technology using current mirrors with gain. PRIME Riccardo Della Sala, Francesco Centurelli, Pietro Monsurrò, Giuseppe Scotti
2022	—	`conf`	Sub-μW Front-End Low Noise Amplifier for Neural Recording Applications. PRIME Riccardo Della Sala, Francesco Centurelli, Pietro Monsurrò, Giuseppe Scotti
2021	J	`jnl`	A Detailed Model of the Switched-Resistor Technique. IEEE Open J. Circuits Syst. Francesco Centurelli, Alessandro Fava, Giuseppe Scotti, Alessandro Trifiletti
2021	C	`conf`	A Low-Voltage High-Performance Frequency Divider exploiting Folded MCML. ISCAS Francesco Centurelli, Giuseppe Scotti, Alessandro Trifiletti, Gaetano Palumbo
2021	J	`jnl`	A Very-Low-Voltage Frequency Divider in Folded MOS Current Mode Logic With Complementary n- and p-type Flip-Flops. IEEE Trans. Very Large Scale Integr. Syst. Francesco Centurelli, Giuseppe Scotti, Gaetano Palumbo
2021	J	`jnl`	Compact E-Band I/Q Receiver in SiGe BiCMOS for 5G Backhauling Applications. IEEE Trans. Circuits Syst. II Express Briefs Giandomenico Amendola, Luigi Boccia, Francesco Centurelli, Pascal Chevalier, Alessandro Fonte, Carmine Mustacchio, Andrea Pallotta, Pasquale Tommasino, Antonio Traversa, Alessandro Trifiletti
2021	J	`jnl`	Design of Low-Voltage Power Efficient Frequency Dividers in Folded MOS Current Mode Logic. IEEE Trans. Circuits Syst. I Regul. Pap. Francesco Centurelli, Giuseppe Scotti, Alessandro Trifiletti, Gaetano Palumbo
2020	J	`jnl`	0.6-V CMOS cascode OTA with complementary gate-driven gain-boosting and forward body bias. Int. J. Circuit Theory Appl. Danilo Cellucci, Francesco Centurelli, Valerio Di Stefano, Pietro Monsurrò, Salvatore Pennisi, Giuseppe Scotti, Alessandro Trifiletti
2020	J	`jnl`	An improved reversed miller compensation technique for three-stage CMOS OTAs with double pole-zero cancellation and almost single-pole frequency response. Int. J. Circuit Theory Appl. Francesco Centurelli, Pietro Monsurrò, Giuseppe Scotti, Pasquale Tommasino, Alessandro Trifiletti
2020	J	`jnl`	Delay models and design guidelines for MCML gates with resistor or PMOS load. Microelectron. J. Francesco Centurelli, Giuseppe Scotti, Alessandro Trifiletti, Gaetano Palumbo
2020	J	`jnl`	Low-power class-AB 4th-order low-pass filter based on current conveyors with dynamic mismatch compensation of biasing errors. Int. J. Circuit Theory Appl. Francesco Centurelli, Pietro Monsurrò, Vincenzo Stornelli, Gianluca Barile, Alessandro Trifiletti
2019	—	`conf`	A low-power class-AB Gm-C biquad stage in CMOS 40nm technology. ICECS Francesco Centurelli, Pietro Monsurrò, Alessandro Trifiletti
2019	J	`jnl`	High-gain, high-CMRR class AB operational transconductance amplifier based on the flipped voltage follower. Int. J. Circuit Theory Appl. Francesco Centurelli, Pietro Monsurrò, Alessandro Trifiletti
2018	J	`jnl`	A Topology of Fully Differential Class-AB Symmetrical OTA With Improved CMRR. IEEE Trans. Circuits Syst. II Express Briefs Francesco Centurelli, Pietro Monsurrò, Gaetano Parisi, Pasquale Tommasino, Alessandro Trifiletti
2017	—	`conf`	A fully-differential class-AB OTA with CMRR improved by local feedback. ECCTD Francesco Centurelli, Pietro Monsurrò, Gaetano Parisi, Pasquale Tommasino, Alessandro Trifiletti
2017	—	`conf`	Class-AB current conveyors based on the FVF. ECCTD Francesco Centurelli, Pietro Monsurrò, Alessandro Trifiletti, Gianluca Barile, Giuseppe Ferri, Leonardo Pantoli, Vincenzo Stornelli
2017	J	`jnl`	Fully Differential Class-AB OTA with Improved CMRR. J. Circuits Syst. Comput. Francesco Centurelli, Pietro Monsurrò, Gaetano Parisi, Pasquale Tommasino, Alessandro Trifiletti
2017	—	`conf`	On the use of voltage conveyors for the synthesis of biquad filters and arbitrary networks. ECCTD Francesco Centurelli, Pietro Monsurrò, Pasquale Tommasino, Alessandro Trifiletti
2017	—	`conf`	Power-efficient dynamic-biased CCII. ECCTD Gianluca Barile, L. Liberati, Giuseppe Ferri, Leonardo Pantoli, Vincenzo Stornelli, Francesco Centurelli, Pietro Monsurrò, Alessandro Trifiletti
2016	—	`conf`	A new class-AB Flipped Voltage Follower using a common-gate auxiliary amplifier. MIXDES Francesco Centurelli, Pietro Monsurrò, Danilo Ruscio, Alessandro Trifiletti
2016	J	`jnl`	Comparative performance analysis and complementary triode based CMFB circuits for fully differential class AB symmetrical OTAs with low power consumption. Int. J. Circuit Theory Appl. Francesco Centurelli, Pietro Monsurrò, Alessandro Trifiletti
2015	J	`jnl`	Design and validation through a frequency-based metric of a new countermeasure to protect nanometer ICs from side-channel attacks. J. Cryptogr. Eng. Simone Bongiovanni, Francesco Centurelli, Giuseppe Scotti, Alessandro Trifiletti
2014	J	`jnl`	A wideband amplifier topology based on positive capacitive feedback. Microelectron. J. Francesco Centurelli, Roberto Antonio Gualano, Alessandro Trifiletti
2014	—	`conf`	Design of broad-band power amplifiers by means of an impedance transforming lossy equalizer. MIXDES Francesco Centurelli, Giuseppe Scotti, Pasquale Tommasino, Alessandro Trifiletti, Milena Djukanovic
2013	J	`jnl`	Improved Digital Background Calibration of Time-Interleaved Pipeline A/D Converters. IEEE Trans. Circuits Syst. II Express Briefs Francesco Centurelli, Pietro Monsurrò, Alessandro Trifiletti
2012	J	`jnl`	Efficient Digital Background Calibration of Time-Interleaved Pipeline Analog-to-Digital Converters. IEEE Trans. Circuits Syst. I Regul. Pap. Francesco Centurelli, Pietro Monsurrò, Alessandro Trifiletti
2011	—	`conf`	A class-AB flipped voltage follower output stage. ECCTD Francesco Centurelli, Pietro Monsurrò, Alessandro Trifiletti
2011	—	`conf`	A class-AB very low voltage amplifier and sample & hold circuit. ECCTD Francesco Centurelli, Pietro Monsurrò, Alessandro Trifiletti
2011	—	`conf`	A very low-voltage differential amplifier for opamp design. ECCTD Francesco Centurelli, Pietro Monsurrò, Giuseppe Scotti, Alessandro Trifiletti
2011	—	`conf`	An MDAC architecture with low sensitivity to finite opamp gain. ECCTD Francesco Centurelli, Pietro Monsurrò, Alessandro Trifiletti
2010	J	`jnl`	Behavioral Modeling for Calibration of Pipeline Analog-To-Digital Converters. IEEE Trans. Circuits Syst. I Regul. Pap. Francesco Centurelli, Pietro Monsurrò, Alessandro Trifiletti
2009	J	`jnl`	Design Solutions for Sample-and-Hold Circuits in CMOS Nanometer Technologies. IEEE Trans. Circuits Syst. II Express Briefs Francesco Centurelli, Pietro Monsurrò, Salvatore Pennisi, Giuseppe Scotti, Alessandro Trifiletti
2008	J	`jnl`	A Simple Technique for Fast Digital Background Calibration of A/D Converters. EURASIP J. Adv. Signal Process. Francesco Centurelli, Pietro Monsurrò, Alessandro Trifiletti
2008	C	`conf`	A gain-enhancing technique for very low-voltage amplifiers. ISCAS Francesco Centurelli, Pietro Monsurrò, Giuseppe Scotti, Alessandro Trifiletti
2007	J	`jnl`	A High-Speed Low-Voltage Phase Detector for Clock Recovery From NRZ Data. IEEE Trans. Circuits Syst. I Regul. Pap. Francesco Centurelli, Giuseppe Scotti, Alessandro Trifiletti
2007	—	`conf`	A Sample-and-Hold Circuit with Very Low Gain Error for Time Interleaving Applications. ECCTD Francesco Centurelli, Andrea Simonetti, Alessandro Trifiletti
2007	—	`conf`	A Statistical Model of Logic Gates for Monte Carlo Simulation Including On-Chip Variations. PATMOS Francesco Centurelli, Luca Giancane, Mauro Olivieri, Giuseppe Scotti, Alessandro Trifiletti
2007	C	`conf`	A distortion model for pipeline Analog-to-Digital converters. ISCAS Francesco Centurelli, Pietro Monsurrò, Alessandro Trifiletti
2007	J	`jnl`	CMOS High-CMRR Current Output Stages. IEEE Trans. Circuits Syst. II Express Briefs Francesco Centurelli, Alfio Dario Grasso, Salvatore Pennisi, Giuseppe Scotti, Alessandro Trifiletti
2007	—	`conf`	CMOS Miller OTA with Body-Biased Output Stage. ECCTD Alfio Dario Grasso, Salvatore Pennisi, Francesco Centurelli, Giuseppe Scotti, Alessandro Trifiletti
2007	—	`conf`	Power-constrained Bandwidth Optimization in Cascaded Open-loop Amplifiers. ECCTD Francesco Centurelli, Pietro Monsurrò, Alessandro Trifiletti
2006	C	`conf`	A model for the distortion due to switch on-resistance in sample-and-hold circuits. ISCAS Francesco Centurelli, Pietro Monsurrò, Alessandro Trifiletti
2006	C	`conf`	Validation of a statistical non-linear model of GaAs HEMT MMIC's by hypothesis testing and principal components analysis. ISCAS Marco Balsi, Francesco Centurelli, Piero Marietti, Giuseppe Scotti, Pasquale Tommasino, Alessandro Trifiletti, Giancarlo Valente
2005	J	`jnl`	A 10-Gb/s CMU/CDR chip-set in SiGe BiCMOS commercial technology with multistandard capability. IEEE Trans. Very Large Scale Integr. Syst. Francesco Centurelli, Alessandro Golfarelli, Jesus Guinea, Leonardo Masini, Damiana Morigi, Massimo Pozzoni, Giuseppe Scotti, Alessandro Trifiletti
2005	J	`jnl`	Analytic transient solution of SCFL logic gates. Int. J. Circuit Theory Appl. Alberto Maria Bersani, Francesco Centurelli, Luca Fontana, Alessandro Trifiletti
2005	—	`conf`	High-speed CMOS-to-ECL pad driver in 0.18µm CMOS. ISCAS (1) Francesco Centurelli, G. Lulli, Piero Marietti, Pietro Monsurrò, Giuseppe Scotti, Alessandro Trifiletti
2004	—	`conf`	A high-speed low-voltage phase detector for clock recovery from NRZ data. ISCAS (4) Francesco Centurelli, Massimo Pozzoni, Giuseppe Scotti, Alessandro Trifiletti
2004	—	`conf`	Robust three-state PFD architecture with enhanced frequency acquisition capabilities. ISCAS (4) Francesco Centurelli, Stefano Costi, Mauro Olivieri, Salvatore Pennisi, Alessandro Trifiletti
2003	—	`conf`	An accurate behavioral model of phase detectors for clock recovery circuits. ISCAS (4) Marco Balsi, Francesco Centurelli, Giuseppe Scotti, Pasquale Tommasino, Alessandro Trifiletti
2003	—	`conf`	Current output stage with improved CMRR. ICECS Francesco Centurelli, Salvatore Pennisi, Alessandro Trifiletti
2002	—	`conf`	A tree-like amplifier architecture for large gain-bandwidth product. ICECS Marco Balsi, Francesco Centurelli, Salvatore Pennisi, Alessandro Trifiletti
2002	—	`conf`	Bipolar differential cell with improved bandwidth performance. ICECS Marco Balsi, Francesco Centurelli, Salvatore Pennisi, Alessandro Trifiletti
2000	A	`conf`	A low-power clock and data recovery circuit for 2.5 Gb/s SDH receivers. ISLPED Andrea Pallotta, Francesco Centurelli, Alessandro Trifiletti
1998	—	`conf`	A monolithic 2.5-Gb/s clock and data recovery circuit based on Silicon bipolar technology. Broadband European Networks and Multimedia Services Andrea Pallotta, Francesco Centurelli, Francesco Loriga, Alessandro Trifiletti