Franc Brglez - RankMe

68 papers A* 11A 14B 3C 6Misc 1Journal 18Unranked 15

Year	Rank	Type	Title / Venue / Authors
2022	J	`jnl`	Asymptotic Experiments with Data Structures: Bipartite Graph Matchings and Covers. CoRR Eason Li, Franc Brglez
2018	J	`jnl`	On Uncensored Mean First-Passage-Time Performance Experiments with Multiwalk in R CoRR Franc Brglez
2017	J	`jnl`	Low-autocorrelation binary sequences: On improved merit factors and runtime predictions to achieve them. Appl. Soft Comput. Borko Boskovic, Franc Brglez, Janez Brest
2017	B	`conf`	On asymptotic complexity of the optimum Golomb ruler problem: From established stochastic methods to self-avoiding walks. CEC Franc Brglez, Borko Boskovic, Janez Brest
2014	J	`jnl`	Low-Autocorrelation Binary Sequences: on the Performance of Memetic-Tabu and Self-Avoiding Walk Solvers. CoRR Borko Boskovic, Franc Brglez, Janez Brest
2013	J	`jnl`	On Self-Avoiding Walks across n-Dimensional Dice and Combinatorial Optimization: An Introduction. CoRR Franc Brglez
2007	—	`conf`	High-contrast algorithm behavior: observation, hypothesis, and experimental design. Experimental Computer Science Matthias F. M. Stallmann, Franc Brglez
2007	—	`conf`	Performance testing of combinatorial solvers with isomorph class instances. Experimental Computer Science Franc Brglez, Jason A. Osborne
2005	A*	`conf`	Effective bounding techniques for solving unate and binate covering problems. DAC Xiao Yu Li, Matthias F. M. Stallmann, Franc Brglez
2005	J	`jnl`	On SAT instance classes and a method for reliable performance experiments with SAT solvers. Ann. Math. Artif. Intell. Franc Brglez, Xiao Yu Li, Matthias F. M. Stallmann
2003	A	`conf`	A Local Search SAT Solver Using an Effective Switching Strategy and an Efficient Unit Propagation. SAT Xiao Yu Li, Matthias F. M. Stallmann, Franc Brglez
2001	A*	`conf`	A Universal Client for Distributed Networked Design and Computing. DAC Franc Brglez, Hemang Lavana
2001	J	`jnl`	Design of experiments and evaluation of BDD ordering heuristics. Int. J. Softw. Tools Technol. Transf. Justin E. Harlow III, Franc Brglez
2001	J	`jnl`	Heuristics, Experimental Subjects, and Treatment Evaluation in Bigraph Crossing Minimization. ACM J. Exp. Algorithmics Matthias F. M. Stallmann, Franc Brglez, Debabrata Ghosh
2000	C	`conf`	OpenDesign: An Open User-Configurable Project Environment for Collaborative Design and Execution on the Internet. ICCD Hemang Lavana, Franc Brglez, Robert B. Reese, Gangadhar Konduri, Anantha P. Chandrakasan
2000	J	`jnl`	The Scientific Method and Design and Test. IEEE Des. Test Comput. Franc Brglez
1999	—	`conf`	Design of experiments in CAD: context and new data sets for ISCAS'99. ISCAS (6) Franc Brglez, Rolf Drechsler
1999	—	`conf`	Equivalence classes of circuit mutants for experimental design. ISCAS (6) Debabrata Ghosh, Franc Brglez
1999	—	`conf`	Evaluating iterative improvement heuristics for bigraph crossing minimization. ISCAS (6) Matthias F. M. Stallmann, Franc Brglez, Debabrata Ghosh
1999	A	`conf`	Heuristics and Experimental Design for Bigraph Crossing Number Minimization. ALENEX Matthias F. M. Stallmann, Franc Brglez, Debabrata Ghosh
1999	—	`conf`	Mirror, mirror, on the wall...is the new release any different at all? [BDDs]. ISCAS (6) Justin E. Harlow III, Franc Brglez
1999	—	`conf`	User-configurable experimental design flows on the web: the ISCAS'99 experiments. ISCAS (6) Hemang Lavana, Franc Brglez, Robert B. Reese
1998	B	`conf`	Design of Experiments for Evaluation of BDD Packages Using Controlled Circuit Mutations. FMCAD Justin E. Harlow III, Franc Brglez
1998	A	`conf`	Design of experiments in BDD variable ordering: lessons learned. ICCAD Justin E. Harlow III, Franc Brglez
1998	J	`jnl`	Effects of resource sharing on circuit delay: an assignment algorithm for clock period optimization. ACM Trans. Design Autom. Electr. Syst. Subhrajit Bhattacharya, Sujit Dey, Franc Brglez
1998	A	`conf`	Synthesis of Wiring Signature-Invariant Equivalence Class Circuit Mutants and Applications to Benchmarking. DATE Debabrata Ghosh, Nevin Kapur, Franc Brglez, Justin E. Harlow III
1998	—	`conf`	WebWise Tcl/Tk: A Safe-Tcl/Tk-based Toolkit Enhanced for the World Wide Web. Tcl/Tk Conference Hemang Lavana, Franc Brglez
1997	A*	`conf`	Executable Workflows: A Paradigm for Collaborative Design on the Internet. DAC Hemang Lavana, Amit Khetawat, Franc Brglez, Krzysztof Kozminski
1997	B	`conf`	Internet-based workflows: a paradigm for dynamically reconfigurable desktop environments. GROUP Hemang Lavana, Amit Khetawat, Franc Brglez
1997	—	`conf`	Towards a new benchmarking paradigm in EDA: analysis of equivalence class mutant circuit distributions. ISPD Nevin Kapur, Debabrata Ghosh, Franc Brglez
1996	J	`jnl`	Fast true delay estimation during high level synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Subhrajit Bhattacharya, Sujit Dey, Franc Brglez
1995	Misc	`conf`	Detectable perturbations: a paradigm for technology-specific multi-fault test generation. VTS Andrej Zemva, Franc Brglez
1995	A	`conf`	PROP: a recursive paradigm for area-efficient and performance oriented partitioning of large FPGA netlists. ICCAD Roman Kuznar, Franc Brglez
1995	—	`conf`	Partial scan selection for user-specified fault coverage. EURO-DAC Clay Gloster, Franc Brglez
1994	—	`conf`	A Functionality Fault Model: Feasibility and Applications. EDAC-ETC-EUROASIC Andrej Zemva, Franc Brglez, Krzysztof Kozminski, Baldomir Zajc
1994	—	`conf`	A unified cost model for min-cut partitioning with replication applied to optimization of large heterogeneous FPGA partitions. EURO-DAC Roman Kuznar, Baldomir Zajc, Franc Brglez
1994	A*	`conf`	Clock Period Optimization During Resource Sharing and Assignment. DAC Subhrajit Bhattacharya, Sujit Dey, Franc Brglez
1994	—	`conf`	Introduction of Permissible Bridges with Application to Logic Optimization after Technology Mapping. EDAC-ETC-EUROASIC Bernhard Rohfleisch, Franc Brglez
1994	A*	`conf`	Multi-way Netlist Partitioning into Heterogeneous FPGAs and Minimization of Total Device Cost and Interconnect. DAC Roman Kuznar, Franc Brglez, Baldomir Zajc
1994	A*	`conf`	Performance Analysis and Optimization of Schedules for Conditional and Loop-Intensive Specifications. DAC Subhrajit Bhattacharya, Sujit Dey, Franc Brglez
1994	A	`conf`	Provably correct high-level timing analysis without path sensitization. ICCAD Subhrajit Bhattacharya, Sujit Dey, Franc Brglez
1994	J	`jnl`	Report of the 1993 workshop on rapid prototyping of microelectronic systems for universities. SIGARCH Comput. Archit. News Phil Allen, Franc Brglez, Hal Carter, Robert Caverly, Jerry Dillion, Albert Lo, Ron Lomax, John Oldfield, Cesar Pina, T. J. Wilkinson
1993	J	`jnl`	A D&T Special Report on ACM/SIGDA Design Automation Benchmarks: Catalyst or Anathema? IEEE Des. Test Comput. Franc Brglez
1993	A*	`conf`	Cost Minimization of Partitions into Multiple Devices. DAC Roman Kuznar, Franc Brglez, Krzysztof Kozminski
1993	J	`jnl`	Transformations and resynthesis for testability of RT-level control-data path specifications. IEEE Trans. Very Large Scale Integr. Syst. Subhrajit Bhattacharya, Franc Brglez, Sujit Dey
1992	J	`jnl`	A framework and method for hierarchical test generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. John D. Calhoun, Franc Brglez
1992	A	`conf`	Automatic Pattern Generation for Diagnosis of Wiring Interconnect Faults. ITC Matthew Melton, Franc Brglez
1992	—	`conf`	Cellular scan test generation for sequential circuits. EURO-DAC Clay S. Gloster Jr., Franc Brglez
1992	A*	`conf`	Characterization of Boolean Functions for Rapid Matching in FPGA Technology Mapping. DAC Ulf Schlichtmann, Franc Brglez, Michael Hermann
1991	J	`jnl`	Circuit partitioning for logic synthesis. IEEE J. Solid State Circuits Sujit Dey, Franc Brglez, Gershon Kedem
1991	—	`conf`	Identification and Resynthesis of Pipelines in Sequential Networks. VLSI Sujit Dey, Franc Brglez, Gershon Kedem
1991	C	`conf`	Partitioning Sequential Circuits for Logic Optimization. ICCD Sujit Dey, Franc Brglez, Gershon Kedem
1990	C	`conf`	Built-in self-test with weighted random pattern hardware. ICCD Franc Brglez, Clay S. Gloster Jr., Gershon Kedem
1990	A*	`conf`	Corolla Based Circuit Partitioning and Resynthesis. DAC Sujit Dey, Franc Brglez, Gershon Kedem
1990	C	`conf`	OASIS: a silicon compiler for semi-custom design. RSP Gershon Kedem, Franc Brglez, Krzysztof Kozminski
1989	A	`conf`	A Framework and Method for Hierarchical Test Generation. ITC John D. Calhoun, Franc Brglez
1989	J	`jnl`	Boundary scan with built-in self-test. IEEE Des. Test Clay S. Gloster Jr., Franc Brglez
1989	A	`conf`	Hardware-Based Weighted Random Pattern Generation for Boundary Scan. ITC Franc Brglez, Gershon Kedem, Clay Gloster
1988	C	`conf`	A modular scan-based testability system. ICCD Franc Brglez, David Bryan, John D. Calhoun, Robert Lisanke
1988	A	`conf`	Boundary Scan with Cellular-Based Built-In Self-Test. ITC Clay Gloster, Franc Brglez
1988	C	`conf`	McMAP: a fast technology mapping procedure for multi-level logic synthesis. ICCD Robert Lisanke, Franc Brglez, Gershon Kedem
1987	A*	`conf`	Accelerated Transition Fault Simulation. DAC Michael H. Schultz, Franc Brglez
1987	J	`jnl`	Testability-Driven Random Test-Pattern Generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Robert Lisanke, Franc Brglez, Aart J. de Geus, David Gregory
1985	A	`conf`	A Fast Fault Grader: Analysis and Applications. ITC Franc Brglez
1985	A	`conf`	Fault Coverage Tools: Case Studies. ITC Franc Brglez
1984	A	`conf`	Applications of Testability Analysis: From ATPG to Critical Delay Path Tracing. ITC Franc Brglez, Philip Pownall, Robert Hum
1981	A*	`conf`	A set of programs for MOS design. DAC G. Sakauye, Anna Lubiw, J. Royle, R. Epplett, Jeffrey Tweedale, E. S. Y. Shew, E. Attfield, Franc Brglez, Philip S. Wilcox
1981	A	`conf`	Digital Signal Processing Considerations in Filter-Codec Testing. ITC Franc Brglez