Florian Zaruba

31 papers A* 2A 2C 5Journal 17Unranked 4

Year	Rank	Type	Title / Venue / Authors
2024	—	`conf`	11.3 Metis AIPU: A 12nm 15TOPS/W 209.6TOPS SoC for Cost- and Energy-Efficient Inference at the Edge. ISSCC Pascal Alexander Hager, Bert Moons, Stefan Cosemans, Ioannis A. Papistas, Bram Rooseleer, Jeroen Van Loon, Roel Uytterhoeven, Florian Zaruba, Spyridoula Koumousi, Milos Stanisavljevic, Stefan Mach, Sebastiaan Mutsaards, Riduan Khaddam Aljameh, Gua Hao Khov, Brecht Machiels, Cristian Olar, Anastasios Psarras, Sander Geursen, Jeroen Vermeeren, Yi Lu, Abhishek Maringanti, Deepak Ameta, Leonidas Katselas, Noah Hütter, Manuel Schmuck, Swetha Sivadas, Karishma Sharma, Manuel Oliveira, Ramon Aerne, Nitish Sharma, Timir Soni, Beatrice Bussolino, Djordje Pesut, Michele Pallaro, Andrei Podlesnii, Alexios Lyrakis, Yannick Ruffiner, Martino Dazzi, Johannes Thiele, Koen Goetschalckx, Nazareno Bruschi, Jonas Doevenspeck, Bram Verhoef, Stefan Linz, Giuseppe Garcea, Jonathan Ferguson, Ioannis Koltsidas, Evangelos Eleftheriou
2023	C	`conf`	Reducing Load-Use Dependency-Induced Performance Penalty in the Open-Source RISC-V CVA6 CPU. DSD Gianmarco Ottavi, Florian Zaruba, Luca Benini, Davide Rossi
2023	J	`jnl`	Sparse Stream Semantic Registers: A Lightweight ISA Extension Accelerating General Sparse Linear Algebra. CoRR Paul Scheffler, Florian Zaruba, Fabian Schuiki, Torsten Hoefler, Luca Benini
2023	J	`jnl`	Sparse Stream Semantic Registers: A Lightweight ISA Extension Accelerating General Sparse Linear Algebra. IEEE Trans. Parallel Distributed Syst. Paul Scheffler, Florian Zaruba, Fabian Schuiki, Torsten Hoefler, Luca Benini
2022	J	`jnl`	An Open-Source Platform for High-Performance Non-Coherent On-Chip Communication. IEEE Trans. Computers Andreas Kurth, Wolfgang Rönninger, Thomas Benz, Matheus A. Cavalcante, Fabian Schuiki, Florian Zaruba, Luca Benini
2021	—	`conf`	A 10-core SoC with 20 Fine-Grain Power Domains for Energy-Proportional Data-Parallel Processing over a Wide Voltage and Temperature Range. ESSCIRC Thomas Benz, Luca Bertaccini, Florian Zaruba, Fabian Schuiki, Frank K. Gürkaynak, Luca Benini
2021	A	`conf`	Banshee: A Fast LLVM-Based RISC-V Binary Translator. ICCAD Samuel Riedel, Fabian Schuiki, Paul Scheffler, Florian Zaruba, Luca Benini
2021	—	`—`	Energy-efficient high-performance computing. Florian Zaruba
2021	J	`jnl`	FPnew: An Open-Source Multiformat Floating-Point Unit Architecture for Energy-Proportional Transprecision Computing. IEEE Trans. Very Large Scale Integr. Syst. Stefan Mach, Fabian Schuiki, Florian Zaruba, Luca Benini
2021	A	`conf`	Indirection Stream Semantic Register Architecture for Efficient Sparse-Dense Linear Algebra. DATE Paul Scheffler, Florian Zaruba, Fabian Schuiki, Torsten Hoefler, Luca Benini
2021	J	`jnl`	Manticore: A 4096-Core RISC-V Chiplet Architecture for Ultraefficient Floating-Point Computing. IEEE Micro Florian Zaruba, Fabian Schuiki, Luca Benini
2021	J	`jnl`	Snitch: A Tiny Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating-Point Intensive Workloads. IEEE Trans. Computers Florian Zaruba, Fabian Schuiki, Torsten Hoefler, Luca Benini
2021	J	`jnl`	Stream Semantic Registers: A Lightweight RISC-V ISA Extension Achieving Full Compute Utilization in Single-Issue Cores. IEEE Trans. Computers Fabian Schuiki, Florian Zaruba, Torsten Hoefler, Luca Benini
2021	C	`conf`	Tiny-FPU: Low-Cost Floating-Point Support for Small RISC-V MCU Cores. ISCAS Luca Bertaccini, Matteo Perotti, Stefan Mach, Pasquale Davide Schiavone, Florian Zaruba, Luca Benini
2020	—	`conf`	A 4096-core RISC-V Chiplet Architecture for Ultra-efficient Floating-point Computing. Hot Chips Symposium Florian Zaruba, Fabian Schuiki, Luca Benini
2020	A*	`conf`	ATUNs: Modular and Scalable Support for Atomic Operations in a Shared Memory Multiprocessor. DAC Andreas Kurth, Samuel Riedel, Florian Zaruba, Torsten Hoefler, Luca Benini
2020	J	`jnl`	An Open-Source Platform for High-Performance Non-Coherent On-Chip Communication. CoRR Andreas Kurth, Wolfgang Rönninger, Thomas Benz, Matheus A. Cavalcante, Fabian Schuiki, Florian Zaruba, Luca Benini
2020	J	`jnl`	Ara: A 1-GHz+ Scalable and Energy-Efficient RISC-V Vector Processor With Multiprecision Floating-Point Support in 22-nm FD-SOI. IEEE Trans. Very Large Scale Integr. Syst. Matheus A. Cavalcante, Fabian Schuiki, Florian Zaruba, Michael Schaffner, Luca Benini
2020	A*	`conf`	BYOC: A "Bring Your Own Core" Framework for Heterogeneous-ISA Research. ASPLOS Jonathan Balkind, Katie Lim, Michael Schaffner, Fei Gao, Grigory Chirkov, Ang Li, Alexey Lavrov, Tri M. Nguyen, Yaosheng Fu, Florian Zaruba, Kunal Gulati, Luca Benini, David Wentzlaff
2020	J	`jnl`	FPnew: An Open-Source Multi-Format Floating-Point Unit Architecture for Energy-Proportional Transprecision Computing. CoRR Stefan Mach, Fabian Schuiki, Florian Zaruba, Luca Benini
2020	J	`jnl`	Indirection Stream Semantic Register Architecture for Efficient Sparse-Dense Linear Algebra. CoRR Paul Scheffler, Florian Zaruba, Fabian Schuiki, Torsten Hoefler, Luca Benini
2020	C	`conf`	Live Demonstration: Exploiting Body-Biasing for Static Corner Trimming and Maximum Energy Efficiency Operation in 22nm FDX Technology. ISCAS Alfio Di Mauro, Florian Zaruba, Fabian Schuiki, Stefan Mach, Luca Benini
2020	J	`jnl`	Manticore: A 4096-core RISC-V Chiplet Architecture for Ultra-efficient Floating-point Computing. CoRR Florian Zaruba, Fabian Schuiki, Luca Benini
2020	J	`jnl`	Snitch: A 10 kGE Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating-Point Intensive Workloads. CoRR Florian Zaruba, Fabian Schuiki, Torsten Hoefler, Luca Benini
2019	C	`conf`	A 0.80pJ/flop, 1.24Tflop/sW 8-to-64 bit Transprecision Floating-Point Unit for a 64 bit RISC-V Processor in 22nm FD-SOI. VLSI-SoC Stefan Mach, Fabian Schuiki, Florian Zaruba, Luca Benini
2019	J	`jnl`	Ara: A 1 GHz+ Scalable and Energy-Efficient RISC-V Vector Processor with Multi-Precision Floating Point Support in 22 nm FD-SOI. CoRR Matheus A. Cavalcante, Fabian Schuiki, Florian Zaruba, Michael Schaffner, Luca Benini
2019	J	`jnl`	Stream Semantic Registers: A Lightweight RISC-V ISA Extension Achieving Full Compute Utilization in Single-Issue Cores. CoRR Fabian Schuiki, Florian Zaruba, Torsten Hoefler, Luca Benini
2019	J	`jnl`	The Cost of Application-Class Processing: Energy and Performance Analysis of a Linux-Ready 1.7-GHz 64-Bit RISC-V Core in 22-nm FDSOI Technology. IEEE Trans. Very Large Scale Integr. Syst. Florian Zaruba, Luca Benini
2019	J	`jnl`	The Cost of Application-Class Processing: Energy and Performance Analysis of a Linux-ready 1.7GHz 64bit RISC-V Core in 22nm FDSOI Technology. CoRR Florian Zaruba, Luca Benini
2019	—	`conf`	The Floating Point Trinity: A Multi-modal Approach to Extreme Energy-Efficiency and Performance. ICECS Florian Zaruba, Fabian Schuiki, Stefan Mach, Luca Benini
2018	C	`conf`	An Open-Source Verification Framework for Open-Source Cores: A RISC-V Case Study. VLSI-SoC Pasquale Davide Schiavone, Ernesto Sánchez, Annachiara Ruospo, Francesco Minervini, Florian Zaruba, Germain Haugou, Luca Benini