Florian Huemer

19 papers A 2C 7Journal 2Unranked 8

Year	Rank	Type	Title / Venue / Authors
2026	A	`conf`	Partial-Evaluation Templates: Accelerating Partial Evaluation with Pre-compiled Templates. CGO Florian Huemer, Aleksandar Prokopec, David Leopoldseder, Raphael Mosaner, Hanspeter Mössenböck
2025	—	`conf`	Investigating the Effects of Permanent Faults in QDI Circuits: A Formal Perspective. ASYNC Raghda El Shehaby, Matthias Függer, Florian Huemer, Andreas Steininger
2025	—	`conf`	SeAL: A Provably Complete Fault-Injection Tool for Asynchronous Circuits. ICECS Raghda El Shehaby, Matthias Függer, Florian Huemer, Andreas Steininger
2024	C	`conf`	QDI Binary Comparator Networks and their Application in Combinational Logic. DDECS Florian Huemer
2024	A	`conf`	Taking a Closer Look: An Outlier-Driven Approach to Compilation-Time Optimization. ECOOP Florian Huemer, David Leopoldseder, Aleksandar Prokopec, Raphael Mosaner, Hanspeter Mössenböck
2023	—	`conf`	ζ: A Novel Approach for Mitigating Single Event Transient Effects in Quasi Delay Insensitive Logic. ASYNC Zaheer Tabassam, Andreas Steininger, Robert Najvirt, Florian Huemer
2022	C	`conf`	On SAT-Based Model Checking of Speed-Independent Circuits. DDECS Florian Huemer, Robert Najvirt, Andreas Steininger
2021	C	`conf`	An Automated Setup for Large-Scale Simulation-Based Fault-Injection Experiments on Asynchronous Digital Circuits. DSD Patrick Behal, Florian Huemer, Robert Najvirt, Andreas Steininger
2021	—	`conf`	Towards Explaining the Fault Sensitivity of Different QDI Pipeline Styles. ASYNC Patrick Behal, Florian Huemer, Robert Najvirt, Andreas Steininger, Zaheer Tabassam
2020	—	`conf`	Timing Domain Crossing using Muller Pipelines. ASYNC Florian Huemer, Andreas Steininger
2019	J	`jnl`	An Experimental Study of Metastability-Induced Glitching Behavior. J. Circuits Syst. Comput. Thomas Polzer, Florian Huemer, Andreas Steininger
2018	—	`conf`	Partially Systematic Constant-Weight Codes for Delay-Insensitive Communication. ASYNC Florian Huemer, Andreas Steininger
2018	J	`jnl`	Refined metastability characterization using a time-to-digital converter. Microelectron. Reliab. Thomas Polzer, Florian Huemer, Andreas Steininger
2018	—	`conf`	State Recovery for Coarse-Grain TMR Designs in FPGAs Using Partial Reconfiguration. DFT Markus Schütz, Andreas Steininger, Florian Huemer, Jakob Lechner
2018	C	`conf`	Using a Duplex Time-to-Digital Converter for Metastability Characterization of an FPGA. DDECS Florian Huemer, Thomas Polzer, Andreas Steininger
2017	C	`conf`	Measuring metastability using a time-to-digital converter. DDECS Thomas Polzer, Florian Huemer, Andreas Steininger
2016	C	`conf`	A new coding scheme for fault tolerant 4-phase delay-insensitive codes. ICCD Florian Huemer, Jakob Lechner, Andreas Steininger
2016	—	`conf`	Fault-Tolerant Clock Synchronization with High Precision. ISVLSI Attila Kinali, Florian Huemer, Christoph Lenzen
2015	C	`conf`	Methods for analysing and improving the fault resilience of delay-insensitive codes. ICCD Jakob Lechner, Andreas Steininger, Florian Huemer