Florian Hirner

16 papers A* 1A 3Journal 12
YearRankTypeTitle / Venue / Authors
2026 J jnl
A Flexible Hardware Design Tool for Fast Fourier and Number-Theoretic Transformation Architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Florian Krieger, Florian Hirner, Ahmet Can Mert, Sujoy Sinha Roy
2025 J jnl
A Flexible Hardware Design Tool for Fast Fourier and Number-Theoretic Transformation Architectures.
IACR Cryptol. ePrint Arch.
Florian Krieger, Florian Hirner, Ahmet Can Mert, Sujoy Sinha Roy
2025 J jnl
Accelerating Hash-Based Polynomial Commitment Schemes with Linear Prover Time.
IACR Trans. Cryptogr. Hardw. Embed. Syst.
Florian Hirner, Florian Krieger, Constantin Piber, Sujoy Sinha Roy
2025 J jnl
Chiplet-Based Techniques for Scalable and Memory-Aware Multi-Scalar Multiplication.
IACR Cryptol. ePrint Arch.
Florian Hirner, Florian Krieger, Sujoy Sinha Roy
2025 A conf
Exploring Large Integer Multiplication for Cryptography Targeting In-Memory Computing.
DATE
Florian Krieger, Florian Hirner, Sujoy Sinha Roy
2025 J jnl
High-Performance SIMD Software for Spielman Codes in Zero-Knowledge Proofs.
IACR Cryptol. ePrint Arch.
Florian Krieger, Christian Dobrouschek, Florian Hirner, Sujoy Sinha Roy
2024 A conf
Aloha-HE: A Low-Area Hardware Accelerator for Client-Side Operations in Homomorphic Encryption.
DATE
Florian Krieger, Florian Hirner, Ahmet Can Mert, Sujoy Sinha Roy
2024 J jnl
Exploring Large Integer Multiplication for Cryptography Targeting In-Memory Computing.
IACR Cryptol. ePrint Arch.
Florian Krieger, Florian Hirner, Sujoy Sinha Roy
2024 A conf
OpenNTT - An Automated Toolchain for Compiling High-Performance NTT Accelerators in FHE.
ICCAD
Florian Krieger, Florian Hirner, Ahmet Can Mert, Sujoy Sinha Roy
2024 J jnl
OpenNTT: An Automated Toolchain for Compiling High-Performance NTT Accelerators in FHE.
IACR Cryptol. ePrint Arch.
Florian Krieger, Florian Hirner, Ahmet Can Mert, Sujoy Sinha Roy
2024 J jnl
Orion's Ascent: Accelerating Hash-Based Zero Knowledge Proof on Hardware Platforms.
IACR Cryptol. ePrint Arch.
Florian Hirner, Florian Krieger, Constantin Piber, Sujoy Sinha Roy
2024 J jnl
Proteus: A Pipelined NTT Architecture Generator.
IEEE Trans. Very Large Scale Integr. Syst.
Florian Hirner, Ahmet Can Mert, Sujoy Sinha Roy
2024 A* conf
Whipping the Multivariate-based MAYO Signature Scheme using Hardware Platforms.
CCS
Florian Hirner, Michael Streibl, Florian Krieger, Ahmet Can Mert, Sujoy Sinha Roy
2023 J jnl
A Hardware Implementation of MAYO Signature Scheme.
IACR Cryptol. ePrint Arch.
Florian Hirner, Michael Streibl, Ahmet Can Mert, Sujoy Sinha Roy
2023 J jnl
Aloha-HE: A Low-Area Hardware Accelerator for Client-Side Operations in Homomorphic Encryption.
IACR Cryptol. ePrint Arch.
Florian Krieger, Florian Hirner, Ahmet Can Mert, Sujoy Sinha Roy
2023 J jnl
PROTEUS: A Tool to generate pipelined Number Theoretic Transform Architectures for FHE and ZKP applications.
IACR Cryptol. ePrint Arch.
Florian Hirner, Ahmet Can Mert, Sujoy Sinha Roy