Florentin Dartu

22 papers A* 9A 5C 2Journal 4Unranked 2

Year	Rank	Type	Title / Venue / Authors
2013	—	`conf`	To do or not to do hierarchical timing? ISPD Florentin Dartu, Qiuyang Wu
2010	J	`jnl`	Timed Input Pattern Generation for an Accurate Delay Calculation Under Multiple Input Switching. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Seung Hoon Choi, Kunhyuk Kang, Florentin Dartu, Kaushik Roy
2006	A	`conf`	Algorithms for MIS vector generation and pruning. ICCAD Kenneth S. Stevens, Florentin Dartu
2005	A	`conf`	Expanding the frequency range of AWE via time shifting. ICCAD Ahmed M. Shebaita, Chirayu S. Amin, Florentin Dartu, Yehea I. Ismail
2005	A*	`conf`	Piece-wise approximations of RLCK circuit responses using moment matching. DAC Chirayu S. Amin, Yehea I. Ismail, Florentin Dartu
2005	A*	`conf`	Statistical static timing analysis: how simple can we get? DAC Chirayu S. Amin, Noel Menezes, Kip Killpack, Florentin Dartu, Umakanta Choudhury, Nagib Hakim, Yehea I. Ismail
2005	—	`conf`	Variability modeling and variability-aware design in deep submicron integrated circuits. ACM Great Lakes Symposium on VLSI Florentin Dartu, Anirudh Devgan, Noel Menezes
2005	J	`jnl`	Weibull-based analytical waveform model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chirayu S. Amin, Florentin Dartu, Yehea I. Ismail
2004	A	`conf`	Modeling unbuffered latches for timing analysis. ICCAD Chirayu S. Amin, Florentin Dartu, Yehea I. Ismail
2004	A*	`conf`	Statistical gate delay model considering multiple input switching. DAC Aseem Agarwal, Florentin Dartu, David T. Blaauw
2003	A	`conf`	Weibull Based Analytical Waveform Model. ICCAD Chirayu S. Amin, Florentin Dartu, Yehea I. Ismail
2002	J	`jnl`	TETA: transistor-level waveform evaluation for timing analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Emrah Acar, Florentin Dartu, Lawrence T. Pileggi
2002	A*	`conf`	Timed pattern generation for noise-on-delay calculation. DAC Seung Hoon Choi, Kaushik Roy, Florentin Dartu
1998	A*	`conf`	TETA: Transistor-Level Engine for Timing Analysis. DAC Florentin Dartu, Lawrence T. Pileggi
1997	C	`conf`	CMOS Gate Delay Models for General RLC Loading. ICCD Ravishankar Arunachalam, Florentin Dartu, Lawrence T. Pileggi
1997	A*	`conf`	Calculating Worst-Case Gate Delays Due to Dominant Capacitance Coupling. DAC Florentin Dartu, Lawrence T. Pileggi
1996	A*	`conf`	An Explicit RC-Circuit Delay Approximation Based on the First Three Moments of the Impulse Response. DAC Bogdan Tutuianu, Florentin Dartu, Lawrence T. Pileggi
1996	J	`jnl`	Performance computation for precharacterized CMOS gates with RC loads. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Florentin Dartu, Noel Menezes, Lawrence T. Pileggi
1996	A*	`conf`	RC-Interconnect Macromodels for Timing Simulation. DAC Florentin Dartu, Bogdan Tutuianu, Lawrence T. Pileggi
1994	A*	`conf`	A Gate-Delay Model for high-Speed CMOS Circuits. DAC Florentin Dartu, Noel Menezes, Jessica Qian, Lawrence T. Pillage
1994	A	`conf`	RC interconnect synthesis-a moment fitting approach. ICCAD Noel Menezes, Satyamurthy Pullela, Florentin Dartu, Lawrence T. Pillage
1993	C	`conf`	Piecewise Linear Macromodels for Elementary Logic and Fuzzy Circuits. ISCAS Ion Constatin Tesu, Florentin Dartu